1 //=- HexagonInstrInfoV3.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon V3 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 def callv3 : SDNode<"HexagonISD::CALLv3", SDT_SPCall,
15 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;
17 def callv3nr : SDNode<"HexagonISD::CALLv3nr", SDT_SPCall,
18 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;
20 //===----------------------------------------------------------------------===//
22 //===----------------------------------------------------------------------===//
24 let isCall = 1, hasSideEffects = 1, validSubTargets = HasV3SubT,
25 Defs = VolatileV3.Regs, isPredicable = 1,
26 isExtended = 0, isExtendable = 1, opExtendable = 0,
27 isExtentSigned = 1, opExtentBits = 24, opExtentAlign = 2 in
28 class T_Call<string ExtStr>
29 : JInst<(outs), (ins calltarget:$dst),
30 "call " # ExtStr # "$dst", [], "", J_tc_2early_SLOT23> {
31 let BaseOpcode = "call";
35 let Inst{27-25} = 0b101;
36 let Inst{24-16,13-1} = dst{23-2};
40 let isCall = 1, hasSideEffects = 1, validSubTargets = HasV3SubT,
41 Defs = VolatileV3.Regs, isPredicated = 1,
42 isExtended = 0, isExtendable = 1, opExtendable = 1,
43 isExtentSigned = 1, opExtentBits = 17, opExtentAlign = 2 in
44 class T_CallPred<bit IfTrue, string ExtStr>
45 : JInst<(outs), (ins PredRegs:$Pu, calltarget:$dst),
46 CondStr<"$Pu", IfTrue, 0>.S # "call " # ExtStr # "$dst",
47 [], "", J_tc_2early_SLOT23> {
48 let BaseOpcode = "call";
49 let isPredicatedFalse = !if(IfTrue,0,1);
54 let Inst{27-24} = 0b1101;
55 let Inst{23-22,20-16,13,7-1} = dst{16-2};
56 let Inst{21} = !if(IfTrue,0,1);
61 multiclass T_Calls<string ExtStr> {
62 def NAME : T_Call<ExtStr>;
63 def t : T_CallPred<1, ExtStr>;
64 def f : T_CallPred<0, ExtStr>;
67 let isCodeGenOnly = 0 in
68 defm J2_call: T_Calls<"">, PredRel;
70 let isCodeGenOnly = 1, isCall = 1, hasSideEffects = 1, Defs = VolatileV3.Regs in
71 def CALLv3nr : T_Call<"">, PredRel;
73 //===----------------------------------------------------------------------===//
75 //===----------------------------------------------------------------------===//
78 //===----------------------------------------------------------------------===//
80 //===----------------------------------------------------------------------===//
81 // Call subroutine from register.
83 let isCodeGenOnly = 1, Defs = VolatileV3.Regs, validSubTargets = HasV3SubT in {
84 def CALLRv3nr : JUMPR_MISC_CALLR<0, 1>; // Call, no return.
88 //===----------------------------------------------------------------------===//
90 //===----------------------------------------------------------------------===//
92 //===----------------------------------------------------------------------===//
94 //===----------------------------------------------------------------------===//
97 let Defs = [USR_OVF], Itinerary = ALU64_tc_2_SLOT23,
98 validSubTargets = HasV3SubT, isCodeGenOnly = 0 in
99 def A2_addpsat : T_ALU64_arith<"add", 0b011, 0b101, 1, 0, 1>;
101 class T_ALU64_addsp_hl<string suffix, bits<3> MinOp>
102 : T_ALU64_rr<"add", suffix, 0b0011, 0b011, MinOp, 0, 0, "">;
104 let isCodeGenOnly = 0 in {
105 def A2_addspl : T_ALU64_addsp_hl<":raw:lo", 0b110>;
106 def A2_addsph : T_ALU64_addsp_hl<":raw:hi", 0b111>;
109 let hasSideEffects = 0, isCodeGenOnly = 1 in
110 def A2_addsp : ALU64_rr<(outs DoubleRegs:$Rd),
111 (ins IntRegs:$Rs, DoubleRegs:$Rt), "$Rd = add($Rs, $Rt)",
112 [(set (i64 DoubleRegs:$Rd), (i64 (add (i64 (sext (i32 IntRegs:$Rs))),
113 (i64 DoubleRegs:$Rt))))],
114 "", ALU64_tc_1_SLOT23>;
117 let hasSideEffects = 0 in
118 class T_XTYPE_MIN_MAX_P<bit isMax, bit isUnsigned>
119 : ALU64Inst<(outs DoubleRegs:$Rd), (ins DoubleRegs:$Rt, DoubleRegs:$Rs),
120 "$Rd = "#!if(isMax,"max","min")#!if(isUnsigned,"u","")
121 #"($Rt, $Rs)", [], "", ALU64_tc_2_SLOT23> {
128 let Inst{27-23} = 0b00111;
129 let Inst{22-21} = !if(isMax, 0b10, 0b01);
130 let Inst{20-16} = !if(isMax, Rt, Rs);
131 let Inst{12-8} = !if(isMax, Rs, Rt);
133 let Inst{6} = !if(isMax, 0b0, 0b1);
134 let Inst{5} = isUnsigned;
138 let isCodeGenOnly = 0 in {
139 def A2_minp : T_XTYPE_MIN_MAX_P<0, 0>;
140 def A2_minup : T_XTYPE_MIN_MAX_P<0, 1>;
141 def A2_maxp : T_XTYPE_MIN_MAX_P<1, 0>;
142 def A2_maxup : T_XTYPE_MIN_MAX_P<1, 1>;
145 multiclass MinMax_pats_p<PatFrag Op, InstHexagon Inst, InstHexagon SwapInst> {
146 defm: T_MinMax_pats<Op, DoubleRegs, i64, Inst, SwapInst>;
149 let AddedComplexity = 200 in {
150 defm: MinMax_pats_p<setge, A2_maxp, A2_minp>;
151 defm: MinMax_pats_p<setgt, A2_maxp, A2_minp>;
152 defm: MinMax_pats_p<setle, A2_minp, A2_maxp>;
153 defm: MinMax_pats_p<setlt, A2_minp, A2_maxp>;
154 defm: MinMax_pats_p<setuge, A2_maxup, A2_minup>;
155 defm: MinMax_pats_p<setugt, A2_maxup, A2_minup>;
156 defm: MinMax_pats_p<setule, A2_minup, A2_maxup>;
157 defm: MinMax_pats_p<setult, A2_minup, A2_maxup>;
160 //===----------------------------------------------------------------------===//
162 //===----------------------------------------------------------------------===//
167 //def : Pat <(brcond (i1 (seteq (i32 IntRegs:$src1), 0)), bb:$offset),
168 // (JMP_RegEzt (i32 IntRegs:$src1), bb:$offset)>, Requires<[HasV3T]>;
170 //def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), 0)), bb:$offset),
171 // (JMP_RegNzt (i32 IntRegs:$src1), bb:$offset)>, Requires<[HasV3T]>;
173 //def : Pat <(brcond (i1 (setle (i32 IntRegs:$src1), 0)), bb:$offset),
174 // (JMP_RegLezt (i32 IntRegs:$src1), bb:$offset)>, Requires<[HasV3T]>;
176 //def : Pat <(brcond (i1 (setge (i32 IntRegs:$src1), 0)), bb:$offset),
177 // (JMP_RegGezt (i32 IntRegs:$src1), bb:$offset)>, Requires<[HasV3T]>;
179 //def : Pat <(brcond (i1 (setgt (i32 IntRegs:$src1), -1)), bb:$offset),
180 // (JMP_RegGezt (i32 IntRegs:$src1), bb:$offset)>, Requires<[HasV3T]>;
182 // Map call instruction
183 def : Pat<(callv3 (i32 IntRegs:$dst)),
184 (J2_callr (i32 IntRegs:$dst))>, Requires<[HasV3T]>;
185 def : Pat<(callv3 tglobaladdr:$dst),
186 (J2_call tglobaladdr:$dst)>, Requires<[HasV3T]>;
187 def : Pat<(callv3 texternalsym:$dst),
188 (J2_call texternalsym:$dst)>, Requires<[HasV3T]>;
189 def : Pat<(callv3 tglobaltlsaddr:$dst),
190 (J2_call tglobaltlsaddr:$dst)>, Requires<[HasV3T]>;
192 def : Pat<(callv3nr (i32 IntRegs:$dst)),
193 (CALLRv3nr (i32 IntRegs:$dst))>, Requires<[HasV3T]>;
194 def : Pat<(callv3nr tglobaladdr:$dst),
195 (CALLv3nr tglobaladdr:$dst)>, Requires<[HasV3T]>;
196 def : Pat<(callv3nr texternalsym:$dst),
197 (CALLv3nr texternalsym:$dst)>, Requires<[HasV3T]>;
199 //===----------------------------------------------------------------------===//
200 // :raw form of vrcmpys:hi/lo insns
201 //===----------------------------------------------------------------------===//
202 // Vector reduce complex multiply by scalar.
203 let Defs = [USR_OVF], hasSideEffects = 0 in
204 class T_vrcmpRaw<string HiLo, bits<3>MajOp>:
205 MInst<(outs DoubleRegs:$Rdd),
206 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
207 "$Rdd = vrcmpys($Rss, $Rtt):<<1:sat:raw:"#HiLo, []> {
214 let Inst{27-24} = 0b1000;
215 let Inst{23-21} = MajOp;
216 let Inst{20-16} = Rss;
217 let Inst{12-8} = Rtt;
218 let Inst{7-5} = 0b100;
222 let isCodeGenOnly = 0 in {
223 def M2_vrcmpys_s1_h: T_vrcmpRaw<"hi", 0b101>;
224 def M2_vrcmpys_s1_l: T_vrcmpRaw<"lo", 0b111>;
227 // Assembler mapped to M2_vrcmpys_s1_h or M2_vrcmpys_s1_l
228 let hasSideEffects = 0, isCodeGenOnly = 1 in
230 : MInst<(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, IntRegs:$Rt),
231 "$Rdd=vrcmpys($Rss,$Rt):<<1:sat">;
233 // Vector reduce complex multiply by scalar with accumulation.
234 let Defs = [USR_OVF], hasSideEffects = 0 in
235 class T_vrcmpys_acc<string HiLo, bits<3>MajOp>:
236 MInst <(outs DoubleRegs:$Rxx),
237 (ins DoubleRegs:$_src_, DoubleRegs:$Rss, DoubleRegs:$Rtt),
238 "$Rxx += vrcmpys($Rss, $Rtt):<<1:sat:raw:"#HiLo, [],
246 let Inst{27-24} = 0b1010;
247 let Inst{23-21} = MajOp;
248 let Inst{20-16} = Rss;
249 let Inst{12-8} = Rtt;
250 let Inst{7-5} = 0b100;
254 let isCodeGenOnly = 0 in {
255 def M2_vrcmpys_acc_s1_h: T_vrcmpys_acc<"hi", 0b101>;
256 def M2_vrcmpys_acc_s1_l: T_vrcmpys_acc<"lo", 0b111>;
259 // Assembler mapped to M2_vrcmpys_acc_s1_h or M2_vrcmpys_acc_s1_l
261 let isCodeGenOnly = 1 in
262 def M2_vrcmpys_acc_s1
263 : MInst <(outs DoubleRegs:$dst),
264 (ins DoubleRegs:$dst2, DoubleRegs:$src1, IntRegs:$src2),
265 "$dst += vrcmpys($src1, $src2):<<1:sat", [],
268 let isCodeGenOnly = 0 in {
269 def M2_vrcmpys_s1rp_h : T_MType_vrcmpy <"vrcmpys", 0b101, 0b110, 1>;
270 def M2_vrcmpys_s1rp_l : T_MType_vrcmpy <"vrcmpys", 0b101, 0b111, 0>;
273 // Assembler mapped to M2_vrcmpys_s1rp_h or M2_vrcmpys_s1rp_l
274 let isCodeGenOnly = 1 in
276 : MInst <(outs IntRegs:$Rd), (ins DoubleRegs:$Rss, IntRegs:$Rt),
277 "$Rd=vrcmpys($Rss,$Rt):<<1:rnd:sat">;
280 // S2_cabacdecbin: Cabac decode bin.
281 let Defs = [P0], isPredicateLate = 1, Itinerary = S_3op_tc_1_SLOT23,
283 def S2_cabacdecbin : T_S3op_64 < "decbin", 0b11, 0b110, 0>;