1 //==- HexagonInstrInfo.td - Target Description for Hexagon -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 include "HexagonInstrFormats.td"
15 include "HexagonOperands.td"
17 // Pattern fragment that combines the value type and the register class
18 // into a single parameter.
19 // The pat frags in the definitions below need to have a named register,
20 // otherwise i32 will be assumed regardless of the register class. The
21 // name of the register does not matter.
22 def I1 : PatLeaf<(i1 PredRegs:$R)>;
23 def I32 : PatLeaf<(i32 IntRegs:$R)>;
24 def I64 : PatLeaf<(i64 DoubleRegs:$R)>;
25 def F32 : PatLeaf<(f32 IntRegs:$R)>;
26 def F64 : PatLeaf<(f64 DoubleRegs:$R)>;
28 // Pattern fragments to extract the low and high subregisters from a
30 def LoReg: OutPatFrag<(ops node:$Rs),
31 (EXTRACT_SUBREG (i64 $Rs), subreg_loreg)>;
32 def HiReg: OutPatFrag<(ops node:$Rs),
33 (EXTRACT_SUBREG (i64 $Rs), subreg_hireg)>;
35 // SDNode for converting immediate C to C-1.
36 def DEC_CONST_SIGNED : SDNodeXForm<imm, [{
37 // Return the byte immediate const-1 as an SDNode.
38 int32_t imm = N->getSExtValue();
39 return XformSToSM1Imm(imm);
42 // SDNode for converting immediate C to C-2.
43 def DEC2_CONST_SIGNED : SDNodeXForm<imm, [{
44 // Return the byte immediate const-2 as an SDNode.
45 int32_t imm = N->getSExtValue();
46 return XformSToSM2Imm(imm);
49 // SDNode for converting immediate C to C-3.
50 def DEC3_CONST_SIGNED : SDNodeXForm<imm, [{
51 // Return the byte immediate const-3 as an SDNode.
52 int32_t imm = N->getSExtValue();
53 return XformSToSM3Imm(imm);
56 // SDNode for converting immediate C to C-1.
57 def DEC_CONST_UNSIGNED : SDNodeXForm<imm, [{
58 // Return the byte immediate const-1 as an SDNode.
59 uint32_t imm = N->getZExtValue();
60 return XformUToUM1Imm(imm);
63 //===----------------------------------------------------------------------===//
65 //===----------------------------------------------------------------------===//
66 let hasSideEffects = 0, isCompare = 1, InputType = "imm", isExtendable = 1,
68 class T_CMP <string mnemonic, bits<2> MajOp, bit isNot, Operand ImmOp>
69 : ALU32Inst <(outs PredRegs:$dst),
70 (ins IntRegs:$src1, ImmOp:$src2),
71 "$dst = "#!if(isNot, "!","")#mnemonic#"($src1, #$src2)",
72 [], "",ALU32_2op_tc_2early_SLOT0123 >, ImmRegRel {
76 let CextOpcode = mnemonic;
77 let opExtentBits = !if(!eq(mnemonic, "cmp.gtu"), 9, 10);
78 let isExtentSigned = !if(!eq(mnemonic, "cmp.gtu"), 0, 1);
82 let Inst{27-24} = 0b0101;
83 let Inst{23-22} = MajOp;
84 let Inst{21} = !if(!eq(mnemonic, "cmp.gtu"), 0, src2{9});
85 let Inst{20-16} = src1;
86 let Inst{13-5} = src2{8-0};
92 def C2_cmpeqi : T_CMP <"cmp.eq", 0b00, 0, s10Ext>;
93 def C2_cmpgti : T_CMP <"cmp.gt", 0b01, 0, s10Ext>;
94 def C2_cmpgtui : T_CMP <"cmp.gtu", 0b10, 0, u9Ext>;
96 class T_CMP_pat <InstHexagon MI, PatFrag OpNode, PatLeaf ImmPred>
97 : Pat<(i1 (OpNode (i32 IntRegs:$src1), ImmPred:$src2)),
98 (MI IntRegs:$src1, ImmPred:$src2)>;
100 def : T_CMP_pat <C2_cmpeqi, seteq, s10ImmPred>;
101 def : T_CMP_pat <C2_cmpgti, setgt, s10ImmPred>;
102 def : T_CMP_pat <C2_cmpgtui, setugt, u9ImmPred>;
104 //===----------------------------------------------------------------------===//
106 //===----------------------------------------------------------------------===//
107 def SDTHexagonI64I32I32 : SDTypeProfile<1, 2,
108 [SDTCisVT<0, i64>, SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
110 def HexagonCOMBINE : SDNode<"HexagonISD::COMBINE", SDTHexagonI64I32I32>;
112 let hasSideEffects = 0, hasNewValue = 1, InputType = "reg" in
113 class T_ALU32_3op<string mnemonic, bits<3> MajOp, bits<3> MinOp, bit OpsRev,
115 : ALU32_rr<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
116 "$Rd = "#mnemonic#"($Rs, $Rt)",
117 [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel, PredRel {
118 let isCommutable = IsComm;
119 let BaseOpcode = mnemonic#_rr;
120 let CextOpcode = mnemonic;
128 let Inst{26-24} = MajOp;
129 let Inst{23-21} = MinOp;
130 let Inst{20-16} = !if(OpsRev,Rt,Rs);
131 let Inst{12-8} = !if(OpsRev,Rs,Rt);
135 let hasSideEffects = 0, hasNewValue = 1 in
136 class T_ALU32_3op_pred<string mnemonic, bits<3> MajOp, bits<3> MinOp,
137 bit OpsRev, bit PredNot, bit PredNew>
138 : ALU32_rr<(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt),
139 "if ("#!if(PredNot,"!","")#"$Pu"#!if(PredNew,".new","")#") "#
140 "$Rd = "#mnemonic#"($Rs, $Rt)",
141 [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel, PredNewRel {
142 let isPredicated = 1;
143 let isPredicatedFalse = PredNot;
144 let isPredicatedNew = PredNew;
145 let BaseOpcode = mnemonic#_rr;
146 let CextOpcode = mnemonic;
155 let Inst{26-24} = MajOp;
156 let Inst{23-21} = MinOp;
157 let Inst{20-16} = !if(OpsRev,Rt,Rs);
158 let Inst{13} = PredNew;
159 let Inst{12-8} = !if(OpsRev,Rs,Rt);
160 let Inst{7} = PredNot;
165 class T_ALU32_combineh<string Op1, string Op2, bits<3> MajOp, bits<3> MinOp,
167 : T_ALU32_3op<"", MajOp, MinOp, OpsRev, 0> {
168 let AsmString = "$Rd = combine($Rs"#Op1#", $Rt"#Op2#")";
171 def A2_combine_hh : T_ALU32_combineh<".h", ".h", 0b011, 0b100, 1>;
172 def A2_combine_hl : T_ALU32_combineh<".h", ".l", 0b011, 0b101, 1>;
173 def A2_combine_lh : T_ALU32_combineh<".l", ".h", 0b011, 0b110, 1>;
174 def A2_combine_ll : T_ALU32_combineh<".l", ".l", 0b011, 0b111, 1>;
176 class T_ALU32_3op_sfx<string mnemonic, string suffix, bits<3> MajOp,
177 bits<3> MinOp, bit OpsRev, bit IsComm>
178 : T_ALU32_3op<"", MajOp, MinOp, OpsRev, IsComm> {
179 let AsmString = "$Rd = "#mnemonic#"($Rs, $Rt)"#suffix;
182 def A2_svaddh : T_ALU32_3op<"vaddh", 0b110, 0b000, 0, 1>;
183 def A2_svsubh : T_ALU32_3op<"vsubh", 0b110, 0b100, 1, 0>;
185 let Defs = [USR_OVF], Itinerary = ALU32_3op_tc_2_SLOT0123 in {
186 def A2_svaddhs : T_ALU32_3op_sfx<"vaddh", ":sat", 0b110, 0b001, 0, 1>;
187 def A2_addsat : T_ALU32_3op_sfx<"add", ":sat", 0b110, 0b010, 0, 1>;
188 def A2_svadduhs : T_ALU32_3op_sfx<"vadduh", ":sat", 0b110, 0b011, 0, 1>;
189 def A2_svsubhs : T_ALU32_3op_sfx<"vsubh", ":sat", 0b110, 0b101, 1, 0>;
190 def A2_subsat : T_ALU32_3op_sfx<"sub", ":sat", 0b110, 0b110, 1, 0>;
191 def A2_svsubuhs : T_ALU32_3op_sfx<"vsubuh", ":sat", 0b110, 0b111, 1, 0>;
194 let Itinerary = ALU32_3op_tc_2_SLOT0123 in
195 def A2_svavghs : T_ALU32_3op_sfx<"vavgh", ":rnd", 0b111, 0b001, 0, 1>;
197 def A2_svavgh : T_ALU32_3op<"vavgh", 0b111, 0b000, 0, 1>;
198 def A2_svnavgh : T_ALU32_3op<"vnavgh", 0b111, 0b011, 1, 0>;
200 multiclass T_ALU32_3op_p<string mnemonic, bits<3> MajOp, bits<3> MinOp,
202 def t : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 0, 0>;
203 def f : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 1, 0>;
204 def tnew : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 0, 1>;
205 def fnew : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 1, 1>;
208 multiclass T_ALU32_3op_A2<string mnemonic, bits<3> MajOp, bits<3> MinOp,
209 bit OpsRev, bit IsComm> {
210 let isPredicable = 1 in
211 def A2_#NAME : T_ALU32_3op <mnemonic, MajOp, MinOp, OpsRev, IsComm>;
212 defm A2_p#NAME : T_ALU32_3op_p<mnemonic, MajOp, MinOp, OpsRev>;
215 defm add : T_ALU32_3op_A2<"add", 0b011, 0b000, 0, 1>;
216 defm and : T_ALU32_3op_A2<"and", 0b001, 0b000, 0, 1>;
217 defm or : T_ALU32_3op_A2<"or", 0b001, 0b001, 0, 1>;
218 defm sub : T_ALU32_3op_A2<"sub", 0b011, 0b001, 1, 0>;
219 defm xor : T_ALU32_3op_A2<"xor", 0b001, 0b011, 0, 1>;
221 // Pats for instruction selection.
222 class BinOp32_pat<SDNode Op, InstHexagon MI, ValueType ResT>
223 : Pat<(ResT (Op (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))),
224 (ResT (MI IntRegs:$Rs, IntRegs:$Rt))>;
226 def: BinOp32_pat<add, A2_add, i32>;
227 def: BinOp32_pat<and, A2_and, i32>;
228 def: BinOp32_pat<or, A2_or, i32>;
229 def: BinOp32_pat<sub, A2_sub, i32>;
230 def: BinOp32_pat<xor, A2_xor, i32>;
232 // A few special cases producing register pairs:
233 let OutOperandList = (outs DoubleRegs:$Rd), hasNewValue = 0 in {
234 def S2_packhl : T_ALU32_3op <"packhl", 0b101, 0b100, 0, 0>;
236 let isPredicable = 1 in
237 def A2_combinew : T_ALU32_3op <"combine", 0b101, 0b000, 0, 0>;
239 // Conditional combinew uses "newt/f" instead of "t/fnew".
240 def C2_ccombinewt : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 0, 0>;
241 def C2_ccombinewf : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 1, 0>;
242 def C2_ccombinewnewt : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 0, 1>;
243 def C2_ccombinewnewf : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 1, 1>;
246 let hasSideEffects = 0, hasNewValue = 1, isCompare = 1, InputType = "reg" in
247 class T_ALU32_3op_cmp<string mnemonic, bits<2> MinOp, bit IsNeg, bit IsComm>
248 : ALU32_rr<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
249 "$Pd = "#mnemonic#"($Rs, $Rt)",
250 [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel {
251 let CextOpcode = mnemonic;
252 let isCommutable = IsComm;
258 let Inst{27-24} = 0b0010;
259 let Inst{22-21} = MinOp;
260 let Inst{20-16} = Rs;
263 let Inst{3-2} = 0b00;
267 let Itinerary = ALU32_3op_tc_2early_SLOT0123 in {
268 def C2_cmpeq : T_ALU32_3op_cmp< "cmp.eq", 0b00, 0, 1>;
269 def C2_cmpgt : T_ALU32_3op_cmp< "cmp.gt", 0b10, 0, 0>;
270 def C2_cmpgtu : T_ALU32_3op_cmp< "cmp.gtu", 0b11, 0, 0>;
273 // Patfrag to convert the usual comparison patfrags (e.g. setlt) to ones
274 // that reverse the order of the operands.
275 class RevCmp<PatFrag F> : PatFrag<(ops node:$rhs, node:$lhs), F.Fragment>;
277 // Pats for compares. They use PatFrags as operands, not SDNodes,
278 // since seteq/setgt/etc. are defined as ParFrags.
279 class T_cmp32_rr_pat<InstHexagon MI, PatFrag Op, ValueType VT>
280 : Pat<(VT (Op (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))),
281 (VT (MI IntRegs:$Rs, IntRegs:$Rt))>;
283 def: T_cmp32_rr_pat<C2_cmpeq, seteq, i1>;
284 def: T_cmp32_rr_pat<C2_cmpgt, setgt, i1>;
285 def: T_cmp32_rr_pat<C2_cmpgtu, setugt, i1>;
287 def: T_cmp32_rr_pat<C2_cmpgt, RevCmp<setlt>, i1>;
288 def: T_cmp32_rr_pat<C2_cmpgtu, RevCmp<setult>, i1>;
290 let CextOpcode = "MUX", InputType = "reg", hasNewValue = 1 in
291 def C2_mux: ALU32_rr<(outs IntRegs:$Rd),
292 (ins PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt),
293 "$Rd = mux($Pu, $Rs, $Rt)", [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel {
299 let CextOpcode = "mux";
300 let InputType = "reg";
301 let hasSideEffects = 0;
304 let Inst{27-24} = 0b0100;
305 let Inst{20-16} = Rs;
311 def: Pat<(i32 (select (i1 PredRegs:$Pu), (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))),
312 (C2_mux PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt)>;
314 // Combines the two immediates into a double register.
315 // Increase complexity to make it greater than any complexity of a combine
316 // that involves a register.
318 let isReMaterializable = 1, isMoveImm = 1, isAsCheapAsAMove = 1,
319 isExtentSigned = 1, isExtendable = 1, opExtentBits = 8, opExtendable = 1,
320 AddedComplexity = 75 in
321 def A2_combineii: ALU32Inst <(outs DoubleRegs:$Rdd), (ins s8Ext:$s8, s8Imm:$S8),
322 "$Rdd = combine(#$s8, #$S8)",
323 [(set (i64 DoubleRegs:$Rdd),
324 (i64 (HexagonCOMBINE(i32 s8ExtPred:$s8), (i32 s8ImmPred:$S8))))]> {
330 let Inst{27-23} = 0b11000;
331 let Inst{22-16} = S8{7-1};
332 let Inst{13} = S8{0};
337 //===----------------------------------------------------------------------===//
338 // Template class for predicated ADD of a reg and an Immediate value.
339 //===----------------------------------------------------------------------===//
340 let hasNewValue = 1, hasSideEffects = 0 in
341 class T_Addri_Pred <bit PredNot, bit PredNew>
342 : ALU32_ri <(outs IntRegs:$Rd),
343 (ins PredRegs:$Pu, IntRegs:$Rs, s8Ext:$s8),
344 !if(PredNot, "if (!$Pu", "if ($Pu")#!if(PredNew,".new) $Rd = ",
345 ") $Rd = ")#"add($Rs, #$s8)"> {
351 let isPredicatedNew = PredNew;
354 let Inst{27-24} = 0b0100;
355 let Inst{23} = PredNot;
356 let Inst{22-21} = Pu;
357 let Inst{20-16} = Rs;
358 let Inst{13} = PredNew;
363 //===----------------------------------------------------------------------===//
364 // A2_addi: Add a signed immediate to a register.
365 //===----------------------------------------------------------------------===//
366 let hasNewValue = 1, hasSideEffects = 0 in
367 class T_Addri <Operand immOp>
368 : ALU32_ri <(outs IntRegs:$Rd),
369 (ins IntRegs:$Rs, immOp:$s16),
370 "$Rd = add($Rs, #$s16)", [], "", ALU32_ADDI_tc_1_SLOT0123> {
377 let Inst{27-21} = s16{15-9};
378 let Inst{20-16} = Rs;
379 let Inst{13-5} = s16{8-0};
383 //===----------------------------------------------------------------------===//
384 // Multiclass for ADD of a register and an immediate value.
385 //===----------------------------------------------------------------------===//
386 multiclass Addri_Pred<string mnemonic, bit PredNot> {
387 let isPredicatedFalse = PredNot in {
388 def NAME : T_Addri_Pred<PredNot, 0>;
390 def NAME#new : T_Addri_Pred<PredNot, 1>;
394 let isExtendable = 1, InputType = "imm" in
395 multiclass Addri_base<string mnemonic, SDNode OpNode> {
396 let CextOpcode = mnemonic, BaseOpcode = mnemonic#_ri in {
397 let opExtendable = 2, isExtentSigned = 1, opExtentBits = 16,
399 def A2_#NAME : T_Addri<s16Ext>;
401 let opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
402 hasSideEffects = 0, isPredicated = 1 in {
403 defm A2_p#NAME#t : Addri_Pred<mnemonic, 0>;
404 defm A2_p#NAME#f : Addri_Pred<mnemonic, 1>;
409 defm addi : Addri_base<"add", add>, ImmRegRel, PredNewRel;
411 def: Pat<(i32 (add I32:$Rs, s16ExtPred:$s16)),
412 (i32 (A2_addi I32:$Rs, imm:$s16))>;
414 //===----------------------------------------------------------------------===//
415 // Template class used for the following ALU32 instructions.
418 //===----------------------------------------------------------------------===//
419 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 10,
420 InputType = "imm", hasNewValue = 1 in
421 class T_ALU32ri_logical <string mnemonic, SDNode OpNode, bits<2> MinOp>
422 : ALU32_ri <(outs IntRegs:$Rd),
423 (ins IntRegs:$Rs, s10Ext:$s10),
424 "$Rd = "#mnemonic#"($Rs, #$s10)" ,
425 [(set (i32 IntRegs:$Rd), (OpNode (i32 IntRegs:$Rs), s10ExtPred:$s10))]> {
429 let CextOpcode = mnemonic;
433 let Inst{27-24} = 0b0110;
434 let Inst{23-22} = MinOp;
435 let Inst{21} = s10{9};
436 let Inst{20-16} = Rs;
437 let Inst{13-5} = s10{8-0};
441 def OR_ri : T_ALU32ri_logical<"or", or, 0b10>, ImmRegRel;
442 def AND_ri : T_ALU32ri_logical<"and", and, 0b00>, ImmRegRel;
444 // Subtract register from immediate
445 // Rd32=sub(#s10,Rs32)
446 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 10,
447 CextOpcode = "sub", InputType = "imm", hasNewValue = 1 in
448 def SUB_ri: ALU32_ri <(outs IntRegs:$Rd), (ins s10Ext:$s10, IntRegs:$Rs),
449 "$Rd = sub(#$s10, $Rs)" ,
450 [(set IntRegs:$Rd, (sub s10ExtPred:$s10, IntRegs:$Rs))] > ,
458 let Inst{27-22} = 0b011001;
459 let Inst{21} = s10{9};
460 let Inst{20-16} = Rs;
461 let Inst{13-5} = s10{8-0};
466 let hasSideEffects = 0 in
467 def A2_nop: ALU32Inst <(outs), (ins), "nop" > {
469 let Inst{27-24} = 0b1111;
471 // Rd = not(Rs) gets mapped to Rd=sub(#-1, Rs).
472 def : Pat<(not (i32 IntRegs:$src1)),
473 (SUB_ri -1, (i32 IntRegs:$src1))>;
475 let hasSideEffects = 0, hasNewValue = 1 in
476 class T_tfr16<bit isHi>
477 : ALU32Inst <(outs IntRegs:$Rx), (ins IntRegs:$src1, u16Imm:$u16),
478 "$Rx"#!if(isHi, ".h", ".l")#" = #$u16",
479 [], "$src1 = $Rx" > {
484 let Inst{27-26} = 0b00;
485 let Inst{25-24} = !if(isHi, 0b10, 0b01);
486 let Inst{23-22} = u16{15-14};
488 let Inst{20-16} = Rx;
489 let Inst{13-0} = u16{13-0};
492 def A2_tfril: T_tfr16<0>;
493 def A2_tfrih: T_tfr16<1>;
495 // Conditional transfer is an alias to conditional "Rd = add(Rs, #0)".
496 let isPredicated = 1, hasNewValue = 1, opNewValue = 0 in
497 class T_tfr_pred<bit isPredNot, bit isPredNew>
498 : ALU32Inst<(outs IntRegs:$dst),
499 (ins PredRegs:$src1, IntRegs:$src2),
500 "if ("#!if(isPredNot, "!", "")#
501 "$src1"#!if(isPredNew, ".new", "")#
507 let isPredicatedFalse = isPredNot;
508 let isPredicatedNew = isPredNew;
511 let Inst{27-24} = 0b0100;
512 let Inst{23} = isPredNot;
513 let Inst{13} = isPredNew;
516 let Inst{22-21} = src1;
517 let Inst{20-16} = src2;
520 let isPredicable = 1 in
521 class T_tfr : ALU32Inst<(outs IntRegs:$dst), (ins IntRegs:$src),
528 let Inst{27-21} = 0b0000011;
529 let Inst{20-16} = src;
534 let InputType = "reg", hasNewValue = 1, hasSideEffects = 0 in
535 multiclass tfr_base<string CextOp> {
536 let CextOpcode = CextOp, BaseOpcode = CextOp in {
540 def t : T_tfr_pred<0, 0>;
541 def f : T_tfr_pred<1, 0>;
543 def tnew : T_tfr_pred<0, 1>;
544 def fnew : T_tfr_pred<1, 1>;
548 // Assembler mapped to C2_ccombinew[t|f|newt|newf].
549 // Please don't add bits to this instruction as it'll be converted into
550 // 'combine' before object code emission.
551 let isPredicated = 1 in
552 class T_tfrp_pred<bit PredNot, bit PredNew>
553 : ALU32_rr <(outs DoubleRegs:$dst),
554 (ins PredRegs:$src1, DoubleRegs:$src2),
555 "if ("#!if(PredNot, "!", "")#"$src1"
556 #!if(PredNew, ".new", "")#") $dst = $src2" > {
557 let isPredicatedFalse = PredNot;
558 let isPredicatedNew = PredNew;
561 // Assembler mapped to A2_combinew.
562 // Please don't add bits to this instruction as it'll be converted into
563 // 'combine' before object code emission.
564 class T_tfrp : ALU32Inst <(outs DoubleRegs:$dst),
565 (ins DoubleRegs:$src),
568 let hasSideEffects = 0 in
569 multiclass TFR64_base<string BaseName> {
570 let BaseOpcode = BaseName in {
571 let isPredicable = 1 in
574 def t : T_tfrp_pred <0, 0>;
575 def f : T_tfrp_pred <1, 0>;
577 def tnew : T_tfrp_pred <0, 1>;
578 def fnew : T_tfrp_pred <1, 1>;
582 let InputType = "imm", isExtendable = 1, isExtentSigned = 1, opExtentBits = 12,
583 isMoveImm = 1, opExtendable = 2, BaseOpcode = "TFRI", CextOpcode = "TFR",
584 hasSideEffects = 0, isPredicated = 1, hasNewValue = 1 in
585 class T_TFRI_Pred<bit PredNot, bit PredNew>
586 : ALU32_ri<(outs IntRegs:$Rd), (ins PredRegs:$Pu, s12Ext:$s12),
587 "if ("#!if(PredNot,"!","")#"$Pu"#!if(PredNew,".new","")#") $Rd = #$s12",
588 [], "", ALU32_2op_tc_1_SLOT0123>, ImmRegRel, PredNewRel {
589 let isPredicatedFalse = PredNot;
590 let isPredicatedNew = PredNew;
597 let Inst{27-24} = 0b1110;
598 let Inst{23} = PredNot;
599 let Inst{22-21} = Pu;
601 let Inst{19-16,12-5} = s12;
602 let Inst{13} = PredNew;
606 def C2_cmoveit : T_TFRI_Pred<0, 0>;
607 def C2_cmoveif : T_TFRI_Pred<1, 0>;
608 def C2_cmovenewit : T_TFRI_Pred<0, 1>;
609 def C2_cmovenewif : T_TFRI_Pred<1, 1>;
611 let InputType = "imm", isExtendable = 1, isExtentSigned = 1,
612 CextOpcode = "TFR", BaseOpcode = "TFRI", hasNewValue = 1, opNewValue = 0,
613 isAsCheapAsAMove = 1 , opExtendable = 1, opExtentBits = 16, isMoveImm = 1,
614 isPredicated = 0, isPredicable = 1, isReMaterializable = 1 in
615 def A2_tfrsi : ALU32Inst<(outs IntRegs:$Rd), (ins s16Ext:$s16), "$Rd = #$s16",
616 [(set (i32 IntRegs:$Rd), s16ExtPred:$s16)], "", ALU32_2op_tc_1_SLOT0123>,
622 let Inst{27-24} = 0b1000;
623 let Inst{23-22,20-16,13-5} = s16;
627 defm A2_tfr : tfr_base<"TFR">, ImmRegRel, PredNewRel;
628 let isAsmParserOnly = 1 in
629 defm A2_tfrp : TFR64_base<"TFR64">, PredNewRel;
632 let isReMaterializable = 1, isMoveImm = 1, isAsCheapAsAMove = 1,
633 isAsmParserOnly = 1 in
634 def A2_tfrpi : ALU64_rr<(outs DoubleRegs:$dst), (ins s8Imm64:$src1),
636 [(set (i64 DoubleRegs:$dst), s8Imm64Pred:$src1)]>;
638 // TODO: see if this instruction can be deleted..
639 let isExtendable = 1, opExtendable = 1, opExtentBits = 6,
640 isAsmParserOnly = 1 in
641 def TFRI64_V4 : ALU64_rr<(outs DoubleRegs:$dst), (ins u6Ext:$src1),
644 //===----------------------------------------------------------------------===//
646 //===----------------------------------------------------------------------===//
649 //===----------------------------------------------------------------------===//
651 //===----------------------------------------------------------------------===//
652 // Scalar mux register immediate.
653 let hasSideEffects = 0, isExtentSigned = 1, CextOpcode = "MUX",
654 InputType = "imm", hasNewValue = 1, isExtendable = 1, opExtentBits = 8 in
655 class T_MUX1 <bit MajOp, dag ins, string AsmStr>
656 : ALU32Inst <(outs IntRegs:$Rd), ins, AsmStr>, ImmRegRel {
663 let Inst{27-24} = 0b0011;
664 let Inst{23} = MajOp;
665 let Inst{22-21} = Pu;
666 let Inst{20-16} = Rs;
672 let opExtendable = 2 in
673 def C2_muxri : T_MUX1<0b1, (ins PredRegs:$Pu, s8Ext:$s8, IntRegs:$Rs),
674 "$Rd = mux($Pu, #$s8, $Rs)">;
676 let opExtendable = 3 in
677 def C2_muxir : T_MUX1<0b0, (ins PredRegs:$Pu, IntRegs:$Rs, s8Ext:$s8),
678 "$Rd = mux($Pu, $Rs, #$s8)">;
680 def : Pat<(i32 (select I1:$Pu, s8ExtPred:$s8, I32:$Rs)),
681 (C2_muxri I1:$Pu, s8ExtPred:$s8, I32:$Rs)>;
683 def : Pat<(i32 (select I1:$Pu, I32:$Rs, s8ExtPred:$s8)),
684 (C2_muxir I1:$Pu, I32:$Rs, s8ExtPred:$s8)>;
686 // C2_muxii: Scalar mux immediates.
687 let isExtentSigned = 1, hasNewValue = 1, isExtendable = 1,
688 opExtentBits = 8, opExtendable = 2 in
689 def C2_muxii: ALU32Inst <(outs IntRegs:$Rd),
690 (ins PredRegs:$Pu, s8Ext:$s8, s8Imm:$S8),
691 "$Rd = mux($Pu, #$s8, #$S8)" ,
692 [(set (i32 IntRegs:$Rd),
693 (i32 (select I1:$Pu, s8ExtPred:$s8, s8ImmPred:$S8)))] > {
701 let Inst{27-25} = 0b101;
702 let Inst{24-23} = Pu;
703 let Inst{22-16} = S8{7-1};
704 let Inst{13} = S8{0};
709 //===----------------------------------------------------------------------===//
710 // template class for non-predicated alu32_2op instructions
711 // - aslh, asrh, sxtb, sxth, zxth
712 //===----------------------------------------------------------------------===//
713 let hasNewValue = 1, opNewValue = 0 in
714 class T_ALU32_2op <string mnemonic, bits<3> minOp> :
715 ALU32Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rs),
716 "$Rd = "#mnemonic#"($Rs)", [] > {
722 let Inst{27-24} = 0b0000;
723 let Inst{23-21} = minOp;
726 let Inst{20-16} = Rs;
729 //===----------------------------------------------------------------------===//
730 // template class for predicated alu32_2op instructions
731 // - aslh, asrh, sxtb, sxth, zxtb, zxth
732 //===----------------------------------------------------------------------===//
733 let hasSideEffects = 0, validSubTargets = HasV4SubT,
734 hasNewValue = 1, opNewValue = 0 in
735 class T_ALU32_2op_Pred <string mnemonic, bits<3> minOp, bit isPredNot,
737 ALU32Inst <(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs),
738 !if(isPredNot, "if (!$Pu", "if ($Pu")
739 #!if(isPredNew, ".new) ",") ")#"$Rd = "#mnemonic#"($Rs)"> {
746 let Inst{27-24} = 0b0000;
747 let Inst{23-21} = minOp;
749 let Inst{11} = isPredNot;
750 let Inst{10} = isPredNew;
753 let Inst{20-16} = Rs;
756 multiclass ALU32_2op_Pred<string mnemonic, bits<3> minOp, bit PredNot> {
757 let isPredicatedFalse = PredNot in {
758 def NAME : T_ALU32_2op_Pred<mnemonic, minOp, PredNot, 0>;
761 let isPredicatedNew = 1 in
762 def NAME#new : T_ALU32_2op_Pred<mnemonic, minOp, PredNot, 1>;
766 multiclass ALU32_2op_base<string mnemonic, bits<3> minOp> {
767 let BaseOpcode = mnemonic in {
768 let isPredicable = 1, hasSideEffects = 0 in
769 def A2_#NAME : T_ALU32_2op<mnemonic, minOp>;
771 let validSubTargets = HasV4SubT, isPredicated = 1, hasSideEffects = 0 in {
772 defm A4_p#NAME#t : ALU32_2op_Pred<mnemonic, minOp, 0>;
773 defm A4_p#NAME#f : ALU32_2op_Pred<mnemonic, minOp, 1>;
778 defm aslh : ALU32_2op_base<"aslh", 0b000>, PredNewRel;
779 defm asrh : ALU32_2op_base<"asrh", 0b001>, PredNewRel;
780 defm sxtb : ALU32_2op_base<"sxtb", 0b101>, PredNewRel;
781 defm sxth : ALU32_2op_base<"sxth", 0b111>, PredNewRel;
782 defm zxth : ALU32_2op_base<"zxth", 0b110>, PredNewRel;
784 // Rd=zxtb(Rs): assembler mapped to Rd=and(Rs,#255).
785 // Compiler would want to generate 'zxtb' instead of 'and' becuase 'zxtb' has
786 // predicated forms while 'and' doesn't. Since integrated assembler can't
787 // handle 'mapped' instructions, we need to encode 'zxtb' same as 'and' where
788 // immediate operand is set to '255'.
790 let hasNewValue = 1, opNewValue = 0 in
791 class T_ZXTB: ALU32Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rs),
792 "$Rd = zxtb($Rs)", [] > { // Rd = and(Rs,255)
799 let Inst{27-22} = 0b011000;
801 let Inst{20-16} = Rs;
802 let Inst{21} = s10{9};
803 let Inst{13-5} = s10{8-0};
806 //Rd=zxtb(Rs): assembler mapped to "Rd=and(Rs,#255)
807 multiclass ZXTB_base <string mnemonic, bits<3> minOp> {
808 let BaseOpcode = mnemonic in {
809 let isPredicable = 1, hasSideEffects = 0 in
810 def A2_#NAME : T_ZXTB;
812 let validSubTargets = HasV4SubT, isPredicated = 1, hasSideEffects = 0 in {
813 defm A4_p#NAME#t : ALU32_2op_Pred<mnemonic, minOp, 0>;
814 defm A4_p#NAME#f : ALU32_2op_Pred<mnemonic, minOp, 1>;
819 let isCodeGenOnly=0 in
820 defm zxtb : ZXTB_base<"zxtb",0b100>, PredNewRel;
822 def: Pat<(shl I32:$src1, (i32 16)), (A2_aslh I32:$src1)>;
823 def: Pat<(sra I32:$src1, (i32 16)), (A2_asrh I32:$src1)>;
824 def: Pat<(sext_inreg I32:$src1, i8), (A2_sxtb I32:$src1)>;
825 def: Pat<(sext_inreg I32:$src1, i16), (A2_sxth I32:$src1)>;
827 //===----------------------------------------------------------------------===//
828 // Template class for vector add and avg
829 //===----------------------------------------------------------------------===//
831 class T_VectALU_64 <string opc, bits<3> majOp, bits<3> minOp,
832 bit isSat, bit isRnd, bit isCrnd, bit SwapOps >
833 : ALU64_rr < (outs DoubleRegs:$Rdd),
834 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
835 "$Rdd = "#opc#"($Rss, $Rtt)"#!if(isRnd, ":rnd", "")
836 #!if(isCrnd,":crnd","")
837 #!if(isSat, ":sat", ""),
838 [], "", ALU64_tc_2_SLOT23 > {
845 let Inst{27-24} = 0b0011;
846 let Inst{23-21} = majOp;
847 let Inst{20-16} = !if (SwapOps, Rtt, Rss);
848 let Inst{12-8} = !if (SwapOps, Rss, Rtt);
849 let Inst{7-5} = minOp;
853 // ALU64 - Vector add
854 // Rdd=vadd[u][bhw](Rss,Rtt)
855 let Itinerary = ALU64_tc_1_SLOT23 in {
856 def A2_vaddub : T_VectALU_64 < "vaddub", 0b000, 0b000, 0, 0, 0, 0>;
857 def A2_vaddh : T_VectALU_64 < "vaddh", 0b000, 0b010, 0, 0, 0, 0>;
858 def A2_vaddw : T_VectALU_64 < "vaddw", 0b000, 0b101, 0, 0, 0, 0>;
861 // Rdd=vadd[u][bhw](Rss,Rtt):sat
862 let Defs = [USR_OVF] in {
863 def A2_vaddubs : T_VectALU_64 < "vaddub", 0b000, 0b001, 1, 0, 0, 0>;
864 def A2_vaddhs : T_VectALU_64 < "vaddh", 0b000, 0b011, 1, 0, 0, 0>;
865 def A2_vadduhs : T_VectALU_64 < "vadduh", 0b000, 0b100, 1, 0, 0, 0>;
866 def A2_vaddws : T_VectALU_64 < "vaddw", 0b000, 0b110, 1, 0, 0, 0>;
869 // ALU64 - Vector average
870 // Rdd=vavg[u][bhw](Rss,Rtt)
871 let Itinerary = ALU64_tc_1_SLOT23 in {
872 def A2_vavgub : T_VectALU_64 < "vavgub", 0b010, 0b000, 0, 0, 0, 0>;
873 def A2_vavgh : T_VectALU_64 < "vavgh", 0b010, 0b010, 0, 0, 0, 0>;
874 def A2_vavguh : T_VectALU_64 < "vavguh", 0b010, 0b101, 0, 0, 0, 0>;
875 def A2_vavgw : T_VectALU_64 < "vavgw", 0b011, 0b000, 0, 0, 0, 0>;
876 def A2_vavguw : T_VectALU_64 < "vavguw", 0b011, 0b011, 0, 0, 0, 0>;
879 // Rdd=vavg[u][bhw](Rss,Rtt)[:rnd|:crnd]
880 def A2_vavgubr : T_VectALU_64 < "vavgub", 0b010, 0b001, 0, 1, 0, 0>;
881 def A2_vavghr : T_VectALU_64 < "vavgh", 0b010, 0b011, 0, 1, 0, 0>;
882 def A2_vavghcr : T_VectALU_64 < "vavgh", 0b010, 0b100, 0, 0, 1, 0>;
883 def A2_vavguhr : T_VectALU_64 < "vavguh", 0b010, 0b110, 0, 1, 0, 0>;
885 def A2_vavgwr : T_VectALU_64 < "vavgw", 0b011, 0b001, 0, 1, 0, 0>;
886 def A2_vavgwcr : T_VectALU_64 < "vavgw", 0b011, 0b010, 0, 0, 1, 0>;
887 def A2_vavguwr : T_VectALU_64 < "vavguw", 0b011, 0b100, 0, 1, 0, 0>;
889 // Rdd=vnavg[bh](Rss,Rtt)
890 let Itinerary = ALU64_tc_1_SLOT23 in {
891 def A2_vnavgh : T_VectALU_64 < "vnavgh", 0b100, 0b000, 0, 0, 0, 1>;
892 def A2_vnavgw : T_VectALU_64 < "vnavgw", 0b100, 0b011, 0, 0, 0, 1>;
895 // Rdd=vnavg[bh](Rss,Rtt)[:rnd|:crnd]:sat
896 let Defs = [USR_OVF] in {
897 def A2_vnavghr : T_VectALU_64 < "vnavgh", 0b100, 0b001, 1, 1, 0, 1>;
898 def A2_vnavghcr : T_VectALU_64 < "vnavgh", 0b100, 0b010, 1, 0, 1, 1>;
899 def A2_vnavgwr : T_VectALU_64 < "vnavgw", 0b100, 0b100, 1, 1, 0, 1>;
900 def A2_vnavgwcr : T_VectALU_64 < "vnavgw", 0b100, 0b110, 1, 0, 1, 1>;
903 // Rdd=vsub[u][bh](Rss,Rtt)
904 let Itinerary = ALU64_tc_1_SLOT23 in {
905 def A2_vsubub : T_VectALU_64 < "vsubub", 0b001, 0b000, 0, 0, 0, 1>;
906 def A2_vsubh : T_VectALU_64 < "vsubh", 0b001, 0b010, 0, 0, 0, 1>;
907 def A2_vsubw : T_VectALU_64 < "vsubw", 0b001, 0b101, 0, 0, 0, 1>;
910 // Rdd=vsub[u][bh](Rss,Rtt):sat
911 let Defs = [USR_OVF] in {
912 def A2_vsububs : T_VectALU_64 < "vsubub", 0b001, 0b001, 1, 0, 0, 1>;
913 def A2_vsubhs : T_VectALU_64 < "vsubh", 0b001, 0b011, 1, 0, 0, 1>;
914 def A2_vsubuhs : T_VectALU_64 < "vsubuh", 0b001, 0b100, 1, 0, 0, 1>;
915 def A2_vsubws : T_VectALU_64 < "vsubw", 0b001, 0b110, 1, 0, 0, 1>;
918 // Rdd=vmax[u][bhw](Rss,Rtt)
919 def A2_vmaxb : T_VectALU_64 < "vmaxb", 0b110, 0b110, 0, 0, 0, 1>;
920 def A2_vmaxub : T_VectALU_64 < "vmaxub", 0b110, 0b000, 0, 0, 0, 1>;
921 def A2_vmaxh : T_VectALU_64 < "vmaxh", 0b110, 0b001, 0, 0, 0, 1>;
922 def A2_vmaxuh : T_VectALU_64 < "vmaxuh", 0b110, 0b010, 0, 0, 0, 1>;
923 def A2_vmaxw : T_VectALU_64 < "vmaxw", 0b110, 0b011, 0, 0, 0, 1>;
924 def A2_vmaxuw : T_VectALU_64 < "vmaxuw", 0b101, 0b101, 0, 0, 0, 1>;
926 // Rdd=vmin[u][bhw](Rss,Rtt)
927 def A2_vminb : T_VectALU_64 < "vminb", 0b110, 0b111, 0, 0, 0, 1>;
928 def A2_vminub : T_VectALU_64 < "vminub", 0b101, 0b000, 0, 0, 0, 1>;
929 def A2_vminh : T_VectALU_64 < "vminh", 0b101, 0b001, 0, 0, 0, 1>;
930 def A2_vminuh : T_VectALU_64 < "vminuh", 0b101, 0b010, 0, 0, 0, 1>;
931 def A2_vminw : T_VectALU_64 < "vminw", 0b101, 0b011, 0, 0, 0, 1>;
932 def A2_vminuw : T_VectALU_64 < "vminuw", 0b101, 0b100, 0, 0, 0, 1>;
934 //===----------------------------------------------------------------------===//
935 // Template class for vector compare
936 //===----------------------------------------------------------------------===//
937 let hasSideEffects = 0 in
938 class T_vcmp <string Str, bits<4> minOp>
939 : ALU64_rr <(outs PredRegs:$Pd),
940 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
941 "$Pd = "#Str#"($Rss, $Rtt)", [],
942 "", ALU64_tc_2early_SLOT23> {
949 let Inst{27-23} = 0b00100;
950 let Inst{13} = minOp{3};
951 let Inst{7-5} = minOp{2-0};
953 let Inst{20-16} = Rss;
954 let Inst{12-8} = Rtt;
957 class T_vcmp_pat<InstHexagon MI, PatFrag Op, ValueType T>
958 : Pat<(i1 (Op (T DoubleRegs:$Rss), (T DoubleRegs:$Rtt))),
959 (i1 (MI DoubleRegs:$Rss, DoubleRegs:$Rtt))>;
961 // Vector compare bytes
962 def A2_vcmpbeq : T_vcmp <"vcmpb.eq", 0b0110>;
963 def A2_vcmpbgtu : T_vcmp <"vcmpb.gtu", 0b0111>;
965 // Vector compare halfwords
966 def A2_vcmpheq : T_vcmp <"vcmph.eq", 0b0011>;
967 def A2_vcmphgt : T_vcmp <"vcmph.gt", 0b0100>;
968 def A2_vcmphgtu : T_vcmp <"vcmph.gtu", 0b0101>;
970 // Vector compare words
971 def A2_vcmpweq : T_vcmp <"vcmpw.eq", 0b0000>;
972 def A2_vcmpwgt : T_vcmp <"vcmpw.gt", 0b0001>;
973 def A2_vcmpwgtu : T_vcmp <"vcmpw.gtu", 0b0010>;
975 def: T_vcmp_pat<A2_vcmpbeq, seteq, v8i8>;
976 def: T_vcmp_pat<A2_vcmpbgtu, setugt, v8i8>;
977 def: T_vcmp_pat<A2_vcmpheq, seteq, v4i16>;
978 def: T_vcmp_pat<A2_vcmphgt, setgt, v4i16>;
979 def: T_vcmp_pat<A2_vcmphgtu, setugt, v4i16>;
980 def: T_vcmp_pat<A2_vcmpweq, seteq, v2i32>;
981 def: T_vcmp_pat<A2_vcmpwgt, setgt, v2i32>;
982 def: T_vcmp_pat<A2_vcmpwgtu, setugt, v2i32>;
984 //===----------------------------------------------------------------------===//
986 //===----------------------------------------------------------------------===//
989 //===----------------------------------------------------------------------===//
991 //===----------------------------------------------------------------------===//
993 //===----------------------------------------------------------------------===//
995 //===----------------------------------------------------------------------===//
998 //===----------------------------------------------------------------------===//
1000 //===----------------------------------------------------------------------===//// Add.
1001 //===----------------------------------------------------------------------===//
1003 // Add/Subtract halfword
1004 // Rd=add(Rt.L,Rs.[HL])[:sat]
1005 // Rd=sub(Rt.L,Rs.[HL])[:sat]
1006 // Rd=add(Rt.[LH],Rs.[HL])[:sat][:<16]
1007 // Rd=sub(Rt.[LH],Rs.[HL])[:sat][:<16]
1008 //===----------------------------------------------------------------------===//
1010 let hasNewValue = 1, opNewValue = 0 in
1011 class T_XTYPE_ADD_SUB <bits<2> LHbits, bit isSat, bit hasShift, bit isSub>
1012 : ALU64Inst <(outs IntRegs:$Rd), (ins IntRegs:$Rt, IntRegs:$Rs),
1013 "$Rd = "#!if(isSub,"sub","add")#"($Rt."
1014 #!if(hasShift, !if(LHbits{1},"h","l"),"l") #", $Rs."
1015 #!if(hasShift, !if(LHbits{0},"h)","l)"), !if(LHbits{1},"h)","l)"))
1016 #!if(isSat,":sat","")
1017 #!if(hasShift,":<<16",""), [], "", ALU64_tc_1_SLOT23> {
1021 let IClass = 0b1101;
1023 let Inst{27-23} = 0b01010;
1024 let Inst{22} = hasShift;
1025 let Inst{21} = isSub;
1026 let Inst{7} = isSat;
1027 let Inst{6-5} = LHbits;
1029 let Inst{12-8} = Rt;
1030 let Inst{20-16} = Rs;
1033 //Rd=sub(Rt.L,Rs.[LH])
1034 def A2_subh_l16_ll : T_XTYPE_ADD_SUB <0b00, 0, 0, 1>;
1035 def A2_subh_l16_hl : T_XTYPE_ADD_SUB <0b10, 0, 0, 1>;
1037 //Rd=add(Rt.L,Rs.[LH])
1038 def A2_addh_l16_ll : T_XTYPE_ADD_SUB <0b00, 0, 0, 0>;
1039 def A2_addh_l16_hl : T_XTYPE_ADD_SUB <0b10, 0, 0, 0>;
1041 let Itinerary = ALU64_tc_2_SLOT23, Defs = [USR_OVF] in {
1042 //Rd=sub(Rt.L,Rs.[LH]):sat
1043 def A2_subh_l16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 0, 1>;
1044 def A2_subh_l16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 0, 1>;
1046 //Rd=add(Rt.L,Rs.[LH]):sat
1047 def A2_addh_l16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 0, 0>;
1048 def A2_addh_l16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 0, 0>;
1051 //Rd=sub(Rt.[LH],Rs.[LH]):<<16
1052 def A2_subh_h16_ll : T_XTYPE_ADD_SUB <0b00, 0, 1, 1>;
1053 def A2_subh_h16_lh : T_XTYPE_ADD_SUB <0b01, 0, 1, 1>;
1054 def A2_subh_h16_hl : T_XTYPE_ADD_SUB <0b10, 0, 1, 1>;
1055 def A2_subh_h16_hh : T_XTYPE_ADD_SUB <0b11, 0, 1, 1>;
1057 //Rd=add(Rt.[LH],Rs.[LH]):<<16
1058 def A2_addh_h16_ll : T_XTYPE_ADD_SUB <0b00, 0, 1, 0>;
1059 def A2_addh_h16_lh : T_XTYPE_ADD_SUB <0b01, 0, 1, 0>;
1060 def A2_addh_h16_hl : T_XTYPE_ADD_SUB <0b10, 0, 1, 0>;
1061 def A2_addh_h16_hh : T_XTYPE_ADD_SUB <0b11, 0, 1, 0>;
1063 let Itinerary = ALU64_tc_2_SLOT23, Defs = [USR_OVF] in {
1064 //Rd=sub(Rt.[LH],Rs.[LH]):sat:<<16
1065 def A2_subh_h16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 1, 1>;
1066 def A2_subh_h16_sat_lh : T_XTYPE_ADD_SUB <0b01, 1, 1, 1>;
1067 def A2_subh_h16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 1, 1>;
1068 def A2_subh_h16_sat_hh : T_XTYPE_ADD_SUB <0b11, 1, 1, 1>;
1070 //Rd=add(Rt.[LH],Rs.[LH]):sat:<<16
1071 def A2_addh_h16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 1, 0>;
1072 def A2_addh_h16_sat_lh : T_XTYPE_ADD_SUB <0b01, 1, 1, 0>;
1073 def A2_addh_h16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 1, 0>;
1074 def A2_addh_h16_sat_hh : T_XTYPE_ADD_SUB <0b11, 1, 1, 0>;
1078 def: Pat<(sext_inreg (add I32:$src1, I32:$src2), i16),
1079 (A2_addh_l16_ll I32:$src1, I32:$src2)>;
1081 def: Pat<(sra (add (shl I32:$src1, (i32 16)), I32:$src2), (i32 16)),
1082 (A2_addh_l16_hl I32:$src1, I32:$src2)>;
1084 def: Pat<(shl (add I32:$src1, I32:$src2), (i32 16)),
1085 (A2_addh_h16_ll I32:$src1, I32:$src2)>;
1087 // Subtract halfword.
1088 def: Pat<(sext_inreg (sub I32:$src1, I32:$src2), i16),
1089 (A2_subh_l16_ll I32:$src1, I32:$src2)>;
1091 def: Pat<(shl (sub I32:$src1, I32:$src2), (i32 16)),
1092 (A2_subh_h16_ll I32:$src1, I32:$src2)>;
1094 let hasSideEffects = 0, hasNewValue = 1 in
1095 def S2_parityp: ALU64Inst<(outs IntRegs:$Rd),
1096 (ins DoubleRegs:$Rs, DoubleRegs:$Rt),
1097 "$Rd = parity($Rs, $Rt)", [], "", ALU64_tc_2_SLOT23> {
1102 let IClass = 0b1101;
1103 let Inst{27-24} = 0b0000;
1104 let Inst{20-16} = Rs;
1105 let Inst{12-8} = Rt;
1109 let hasNewValue = 1, opNewValue = 0, hasSideEffects = 0 in
1110 class T_XTYPE_MIN_MAX < bit isMax, bit isUnsigned >
1111 : ALU64Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rt, IntRegs:$Rs),
1112 "$Rd = "#!if(isMax,"max","min")#!if(isUnsigned,"u","")
1113 #"($Rt, $Rs)", [], "", ALU64_tc_2_SLOT23> {
1118 let IClass = 0b1101;
1120 let Inst{27-23} = 0b01011;
1121 let Inst{22-21} = !if(isMax, 0b10, 0b01);
1122 let Inst{7} = isUnsigned;
1124 let Inst{12-8} = !if(isMax, Rs, Rt);
1125 let Inst{20-16} = !if(isMax, Rt, Rs);
1128 def A2_min : T_XTYPE_MIN_MAX < 0, 0 >;
1129 def A2_minu : T_XTYPE_MIN_MAX < 0, 1 >;
1130 def A2_max : T_XTYPE_MIN_MAX < 1, 0 >;
1131 def A2_maxu : T_XTYPE_MIN_MAX < 1, 1 >;
1133 // Here, depending on the operand being selected, we'll either generate a
1134 // min or max instruction.
1136 // (a>b)?a:b --> max(a,b) => Here check performed is '>' and the value selected
1137 // is the larger of two. So, the corresponding HexagonInst is passed in 'Inst'.
1138 // (a>b)?b:a --> min(a,b) => Here check performed is '>' but the smaller value
1139 // is selected and the corresponding HexagonInst is passed in 'SwapInst'.
1141 multiclass T_MinMax_pats <PatFrag Op, RegisterClass RC, ValueType VT,
1142 InstHexagon Inst, InstHexagon SwapInst> {
1143 def: Pat<(select (i1 (Op (VT RC:$src1), (VT RC:$src2))),
1144 (VT RC:$src1), (VT RC:$src2)),
1145 (Inst RC:$src1, RC:$src2)>;
1146 def: Pat<(select (i1 (Op (VT RC:$src1), (VT RC:$src2))),
1147 (VT RC:$src2), (VT RC:$src1)),
1148 (SwapInst RC:$src1, RC:$src2)>;
1152 multiclass MinMax_pats <PatFrag Op, InstHexagon Inst, InstHexagon SwapInst> {
1153 defm: T_MinMax_pats<Op, IntRegs, i32, Inst, SwapInst>;
1155 def: Pat<(sext_inreg (i32 (select (i1 (Op (i32 PositiveHalfWord:$src1),
1156 (i32 PositiveHalfWord:$src2))),
1157 (i32 PositiveHalfWord:$src1),
1158 (i32 PositiveHalfWord:$src2))), i16),
1159 (Inst IntRegs:$src1, IntRegs:$src2)>;
1161 def: Pat<(sext_inreg (i32 (select (i1 (Op (i32 PositiveHalfWord:$src1),
1162 (i32 PositiveHalfWord:$src2))),
1163 (i32 PositiveHalfWord:$src2),
1164 (i32 PositiveHalfWord:$src1))), i16),
1165 (SwapInst IntRegs:$src1, IntRegs:$src2)>;
1168 let AddedComplexity = 200 in {
1169 defm: MinMax_pats<setge, A2_max, A2_min>;
1170 defm: MinMax_pats<setgt, A2_max, A2_min>;
1171 defm: MinMax_pats<setle, A2_min, A2_max>;
1172 defm: MinMax_pats<setlt, A2_min, A2_max>;
1173 defm: MinMax_pats<setuge, A2_maxu, A2_minu>;
1174 defm: MinMax_pats<setugt, A2_maxu, A2_minu>;
1175 defm: MinMax_pats<setule, A2_minu, A2_maxu>;
1176 defm: MinMax_pats<setult, A2_minu, A2_maxu>;
1179 class T_cmp64_rr<string mnemonic, bits<3> MinOp, bit IsComm>
1180 : ALU64_rr<(outs PredRegs:$Pd), (ins DoubleRegs:$Rs, DoubleRegs:$Rt),
1181 "$Pd = "#mnemonic#"($Rs, $Rt)", [], "", ALU64_tc_2early_SLOT23> {
1183 let isCommutable = IsComm;
1184 let hasSideEffects = 0;
1190 let IClass = 0b1101;
1191 let Inst{27-21} = 0b0010100;
1192 let Inst{20-16} = Rs;
1193 let Inst{12-8} = Rt;
1194 let Inst{7-5} = MinOp;
1198 def C2_cmpeqp : T_cmp64_rr<"cmp.eq", 0b000, 1>;
1199 def C2_cmpgtp : T_cmp64_rr<"cmp.gt", 0b010, 0>;
1200 def C2_cmpgtup : T_cmp64_rr<"cmp.gtu", 0b100, 0>;
1202 class T_cmp64_rr_pat<InstHexagon MI, PatFrag CmpOp>
1203 : Pat<(i1 (CmpOp (i64 DoubleRegs:$Rs), (i64 DoubleRegs:$Rt))),
1204 (i1 (MI DoubleRegs:$Rs, DoubleRegs:$Rt))>;
1206 def: T_cmp64_rr_pat<C2_cmpeqp, seteq>;
1207 def: T_cmp64_rr_pat<C2_cmpgtp, setgt>;
1208 def: T_cmp64_rr_pat<C2_cmpgtup, setugt>;
1209 def: T_cmp64_rr_pat<C2_cmpgtp, RevCmp<setlt>>;
1210 def: T_cmp64_rr_pat<C2_cmpgtup, RevCmp<setult>>;
1212 def C2_vmux : ALU64_rr<(outs DoubleRegs:$Rd),
1213 (ins PredRegs:$Pu, DoubleRegs:$Rs, DoubleRegs:$Rt),
1214 "$Rd = vmux($Pu, $Rs, $Rt)", [], "", ALU64_tc_1_SLOT23> {
1215 let hasSideEffects = 0;
1222 let IClass = 0b1101;
1223 let Inst{27-24} = 0b0001;
1224 let Inst{20-16} = Rs;
1225 let Inst{12-8} = Rt;
1230 class T_ALU64_rr<string mnemonic, string suffix, bits<4> RegType,
1231 bits<3> MajOp, bits<3> MinOp, bit OpsRev, bit IsComm,
1233 : ALU64_rr<(outs DoubleRegs:$Rd), (ins DoubleRegs:$Rs, DoubleRegs:$Rt),
1234 "$Rd = " #mnemonic# "($Rs, " #Op2Pfx# "$Rt)" #suffix, [],
1235 "", ALU64_tc_1_SLOT23> {
1236 let hasSideEffects = 0;
1237 let isCommutable = IsComm;
1243 let IClass = 0b1101;
1244 let Inst{27-24} = RegType;
1245 let Inst{23-21} = MajOp;
1246 let Inst{20-16} = !if (OpsRev,Rt,Rs);
1247 let Inst{12-8} = !if (OpsRev,Rs,Rt);
1248 let Inst{7-5} = MinOp;
1252 class T_ALU64_arith<string mnemonic, bits<3> MajOp, bits<3> MinOp, bit IsSat,
1253 bit OpsRev, bit IsComm>
1254 : T_ALU64_rr<mnemonic, !if(IsSat,":sat",""), 0b0011, MajOp, MinOp, OpsRev,
1257 def A2_addp : T_ALU64_arith<"add", 0b000, 0b111, 0, 0, 1>;
1258 def A2_subp : T_ALU64_arith<"sub", 0b001, 0b111, 0, 1, 0>;
1260 def: Pat<(i64 (add I64:$Rs, I64:$Rt)), (A2_addp I64:$Rs, I64:$Rt)>;
1261 def: Pat<(i64 (sub I64:$Rs, I64:$Rt)), (A2_subp I64:$Rs, I64:$Rt)>;
1263 class T_ALU64_logical<string mnemonic, bits<3> MinOp, bit OpsRev, bit IsComm,
1265 : T_ALU64_rr<mnemonic, "", 0b0011, 0b111, MinOp, OpsRev, IsComm,
1268 def A2_andp : T_ALU64_logical<"and", 0b000, 0, 1, 0>;
1269 def A2_orp : T_ALU64_logical<"or", 0b010, 0, 1, 0>;
1270 def A2_xorp : T_ALU64_logical<"xor", 0b100, 0, 1, 0>;
1272 def: Pat<(i64 (and I64:$Rs, I64:$Rt)), (A2_andp I64:$Rs, I64:$Rt)>;
1273 def: Pat<(i64 (or I64:$Rs, I64:$Rt)), (A2_orp I64:$Rs, I64:$Rt)>;
1274 def: Pat<(i64 (xor I64:$Rs, I64:$Rt)), (A2_xorp I64:$Rs, I64:$Rt)>;
1276 //===----------------------------------------------------------------------===//
1278 //===----------------------------------------------------------------------===//
1280 //===----------------------------------------------------------------------===//
1282 //===----------------------------------------------------------------------===//
1284 //===----------------------------------------------------------------------===//
1286 //===----------------------------------------------------------------------===//
1288 //===----------------------------------------------------------------------===//
1290 //===----------------------------------------------------------------------===//
1292 //===----------------------------------------------------------------------===//
1294 //===----------------------------------------------------------------------===//
1296 //===----------------------------------------------------------------------===//
1298 //===----------------------------------------------------------------------===//
1299 // Logical reductions on predicates.
1301 // Looping instructions.
1303 // Pipelined looping instructions.
1305 // Logical operations on predicates.
1306 let hasSideEffects = 0 in
1307 class T_LOGICAL_1OP<string MnOp, bits<2> OpBits>
1308 : CRInst<(outs PredRegs:$Pd), (ins PredRegs:$Ps),
1309 "$Pd = " # MnOp # "($Ps)", [], "", CR_tc_2early_SLOT23> {
1313 let IClass = 0b0110;
1314 let Inst{27-23} = 0b10111;
1315 let Inst{22-21} = OpBits;
1317 let Inst{17-16} = Ps;
1322 def C2_any8 : T_LOGICAL_1OP<"any8", 0b00>;
1323 def C2_all8 : T_LOGICAL_1OP<"all8", 0b01>;
1324 def C2_not : T_LOGICAL_1OP<"not", 0b10>;
1326 def: Pat<(i1 (not (i1 PredRegs:$Ps))),
1327 (C2_not PredRegs:$Ps)>;
1329 let hasSideEffects = 0 in
1330 class T_LOGICAL_2OP<string MnOp, bits<3> OpBits, bit IsNeg, bit Rev>
1331 : CRInst<(outs PredRegs:$Pd), (ins PredRegs:$Ps, PredRegs:$Pt),
1332 "$Pd = " # MnOp # "($Ps, " # !if (IsNeg,"!","") # "$Pt)",
1333 [], "", CR_tc_2early_SLOT23> {
1338 let IClass = 0b0110;
1339 let Inst{27-24} = 0b1011;
1340 let Inst{23-21} = OpBits;
1342 let Inst{17-16} = !if(Rev,Pt,Ps); // Rs and Rt are reversed for some
1343 let Inst{13} = 0b0; // instructions.
1344 let Inst{9-8} = !if(Rev,Ps,Pt);
1348 def C2_and : T_LOGICAL_2OP<"and", 0b000, 0, 1>;
1349 def C2_or : T_LOGICAL_2OP<"or", 0b001, 0, 1>;
1350 def C2_xor : T_LOGICAL_2OP<"xor", 0b010, 0, 0>;
1351 def C2_andn : T_LOGICAL_2OP<"and", 0b011, 1, 1>;
1352 def C2_orn : T_LOGICAL_2OP<"or", 0b111, 1, 1>;
1354 def: Pat<(i1 (and I1:$Ps, I1:$Pt)), (C2_and I1:$Ps, I1:$Pt)>;
1355 def: Pat<(i1 (or I1:$Ps, I1:$Pt)), (C2_or I1:$Ps, I1:$Pt)>;
1356 def: Pat<(i1 (xor I1:$Ps, I1:$Pt)), (C2_xor I1:$Ps, I1:$Pt)>;
1357 def: Pat<(i1 (and I1:$Ps, (not I1:$Pt))), (C2_andn I1:$Ps, I1:$Pt)>;
1358 def: Pat<(i1 (or I1:$Ps, (not I1:$Pt))), (C2_orn I1:$Ps, I1:$Pt)>;
1360 let hasSideEffects = 0, hasNewValue = 1 in
1361 def C2_vitpack : SInst<(outs IntRegs:$Rd), (ins PredRegs:$Ps, PredRegs:$Pt),
1362 "$Rd = vitpack($Ps, $Pt)", [], "", S_2op_tc_1_SLOT23> {
1367 let IClass = 0b1000;
1368 let Inst{27-24} = 0b1001;
1369 let Inst{22-21} = 0b00;
1370 let Inst{17-16} = Ps;
1375 let hasSideEffects = 0 in
1376 def C2_mask : SInst<(outs DoubleRegs:$Rd), (ins PredRegs:$Pt),
1377 "$Rd = mask($Pt)", [], "", S_2op_tc_1_SLOT23> {
1381 let IClass = 0b1000;
1382 let Inst{27-24} = 0b0110;
1387 // User control register transfer.
1388 //===----------------------------------------------------------------------===//
1390 //===----------------------------------------------------------------------===//
1392 //===----------------------------------------------------------------------===//
1394 //===----------------------------------------------------------------------===//
1396 def retflag : SDNode<"HexagonISD::RET_FLAG", SDTNone,
1397 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1398 def eh_return: SDNode<"HexagonISD::EH_RETURN", SDTNone, [SDNPHasChain]>;
1400 def SDHexagonBR_JT: SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
1401 def HexagonBR_JT: SDNode<"HexagonISD::BR_JT", SDHexagonBR_JT, [SDNPHasChain]>;
1403 class CondStr<string CReg, bit True, bit New> {
1404 string S = "if (" # !if(True,"","!") # CReg # !if(New,".new","") # ") ";
1406 class JumpOpcStr<string Mnemonic, bit New, bit Taken> {
1407 string S = Mnemonic # !if(New, !if(Taken,":t",":nt"), "");
1410 let isBranch = 1, isBarrier = 1, Defs = [PC], hasSideEffects = 0,
1412 isExtendable = 1, opExtendable = 0, isExtentSigned = 1,
1413 opExtentBits = 24, opExtentAlign = 2, InputType = "imm" in
1414 class T_JMP<string ExtStr>
1415 : JInst<(outs), (ins brtarget:$dst),
1416 "jump " # ExtStr # "$dst",
1417 [], "", J_tc_2early_SLOT23> {
1419 let IClass = 0b0101;
1421 let Inst{27-25} = 0b100;
1422 let Inst{24-16} = dst{23-15};
1423 let Inst{13-1} = dst{14-2};
1426 let isBranch = 1, Defs = [PC], hasSideEffects = 0, isPredicated = 1,
1427 isExtendable = 1, opExtendable = 1, isExtentSigned = 1,
1428 opExtentBits = 17, opExtentAlign = 2, InputType = "imm" in
1429 class T_JMP_c<bit PredNot, bit isPredNew, bit isTak, string ExtStr>
1430 : JInst<(outs), (ins PredRegs:$src, brtarget:$dst),
1431 CondStr<"$src", !if(PredNot,0,1), isPredNew>.S #
1432 JumpOpcStr<"jump", isPredNew, isTak>.S # " " #
1434 [], "", J_tc_2early_SLOT23>, ImmRegRel {
1435 let isTaken = isTak;
1436 let isPredicatedFalse = PredNot;
1437 let isPredicatedNew = isPredNew;
1441 let IClass = 0b0101;
1443 let Inst{27-24} = 0b1100;
1444 let Inst{21} = PredNot;
1445 let Inst{12} = !if(isPredNew, isTak, zero);
1446 let Inst{11} = isPredNew;
1447 let Inst{9-8} = src;
1448 let Inst{23-22} = dst{16-15};
1449 let Inst{20-16} = dst{14-10};
1450 let Inst{13} = dst{9};
1451 let Inst{7-1} = dst{8-2};
1454 multiclass JMP_Pred<bit PredNot, string ExtStr> {
1455 def NAME : T_JMP_c<PredNot, 0, 0, ExtStr>;
1457 def NAME#newpt : T_JMP_c<PredNot, 1, 1, ExtStr>; // taken
1458 def NAME#new : T_JMP_c<PredNot, 1, 0, ExtStr>; // not taken
1461 multiclass JMP_base<string BaseOp, string ExtStr> {
1462 let BaseOpcode = BaseOp in {
1463 def NAME : T_JMP<ExtStr>;
1464 defm t : JMP_Pred<0, ExtStr>;
1465 defm f : JMP_Pred<1, ExtStr>;
1469 // Jumps to address stored in a register, JUMPR_MISC
1470 // if ([[!]P[.new]]) jumpr[:t/nt] Rs
1471 let isBranch = 1, isIndirectBranch = 1, isBarrier = 1, Defs = [PC],
1472 isPredicable = 1, hasSideEffects = 0, InputType = "reg" in
1474 : JRInst<(outs), (ins IntRegs:$dst),
1475 "jumpr $dst", [], "", J_tc_2early_SLOT2> {
1478 let IClass = 0b0101;
1479 let Inst{27-21} = 0b0010100;
1480 let Inst{20-16} = dst;
1483 let isBranch = 1, isIndirectBranch = 1, Defs = [PC], isPredicated = 1,
1484 hasSideEffects = 0, InputType = "reg" in
1485 class T_JMPr_c <bit PredNot, bit isPredNew, bit isTak>
1486 : JRInst <(outs), (ins PredRegs:$src, IntRegs:$dst),
1487 CondStr<"$src", !if(PredNot,0,1), isPredNew>.S #
1488 JumpOpcStr<"jumpr", isPredNew, isTak>.S # " $dst", [],
1489 "", J_tc_2early_SLOT2> {
1491 let isTaken = isTak;
1492 let isPredicatedFalse = PredNot;
1493 let isPredicatedNew = isPredNew;
1497 let IClass = 0b0101;
1499 let Inst{27-22} = 0b001101;
1500 let Inst{21} = PredNot;
1501 let Inst{20-16} = dst;
1502 let Inst{12} = !if(isPredNew, isTak, zero);
1503 let Inst{11} = isPredNew;
1504 let Inst{9-8} = src;
1507 multiclass JMPR_Pred<bit PredNot> {
1508 def NAME: T_JMPr_c<PredNot, 0, 0>;
1510 def NAME#newpt : T_JMPr_c<PredNot, 1, 1>; // taken
1511 def NAME#new : T_JMPr_c<PredNot, 1, 0>; // not taken
1514 multiclass JMPR_base<string BaseOp> {
1515 let BaseOpcode = BaseOp in {
1517 defm t : JMPR_Pred<0>;
1518 defm f : JMPR_Pred<1>;
1522 let isCall = 1, hasSideEffects = 1 in
1523 class JUMPR_MISC_CALLR<bit isPred, bit isPredNot,
1524 dag InputDag = (ins IntRegs:$Rs)>
1525 : JRInst<(outs), InputDag,
1526 !if(isPred, !if(isPredNot, "if (!$Pu) callr $Rs",
1527 "if ($Pu) callr $Rs"),
1529 [], "", J_tc_2early_SLOT2> {
1532 let isPredicated = isPred;
1533 let isPredicatedFalse = isPredNot;
1535 let IClass = 0b0101;
1536 let Inst{27-25} = 0b000;
1537 let Inst{24-23} = !if (isPred, 0b10, 0b01);
1539 let Inst{21} = isPredNot;
1540 let Inst{9-8} = !if (isPred, Pu, 0b00);
1541 let Inst{20-16} = Rs;
1545 let Defs = VolatileV3.Regs in {
1546 def J2_callrt : JUMPR_MISC_CALLR<1, 0, (ins PredRegs:$Pu, IntRegs:$Rs)>;
1547 def J2_callrf : JUMPR_MISC_CALLR<1, 1, (ins PredRegs:$Pu, IntRegs:$Rs)>;
1550 let isTerminator = 1, hasSideEffects = 0 in {
1551 defm J2_jump : JMP_base<"JMP", "">, PredNewRel;
1553 // Deal with explicit assembly
1554 // - never extened a jump #, always extend a jump ##
1555 let isAsmParserOnly = 1 in {
1556 defm J2_jump_ext : JMP_base<"JMP", "##">;
1557 defm J2_jump_noext : JMP_base<"JMP", "#">;
1560 defm J2_jumpr : JMPR_base<"JMPr">, PredNewRel;
1562 let isReturn = 1, isCodeGenOnly = 1 in
1563 defm JMPret : JMPR_base<"JMPret">, PredNewRel;
1566 def: Pat<(br bb:$dst),
1567 (J2_jump brtarget:$dst)>;
1569 (JMPret (i32 R31))>;
1570 def: Pat<(brcond (i1 PredRegs:$src1), bb:$offset),
1571 (J2_jumpt PredRegs:$src1, bb:$offset)>;
1573 // A return through builtin_eh_return.
1574 let isReturn = 1, isTerminator = 1, isBarrier = 1, hasSideEffects = 0,
1575 isCodeGenOnly = 1, Defs = [PC], Uses = [R28], isPredicable = 0 in
1576 def EH_RETURN_JMPR : T_JMPr;
1578 def: Pat<(eh_return),
1579 (EH_RETURN_JMPR (i32 R31))>;
1580 def: Pat<(HexagonBR_JT (i32 IntRegs:$dst)),
1581 (J2_jumpr IntRegs:$dst)>;
1582 def: Pat<(brind (i32 IntRegs:$dst)),
1583 (J2_jumpr IntRegs:$dst)>;
1585 //===----------------------------------------------------------------------===//
1587 //===----------------------------------------------------------------------===//
1589 //===----------------------------------------------------------------------===//
1591 //===----------------------------------------------------------------------===//
1592 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, AddedComplexity = 20 in
1593 class T_load_io <string mnemonic, RegisterClass RC, bits<4> MajOp,
1595 : LDInst<(outs RC:$dst), (ins IntRegs:$src1, ImmOp:$offset),
1596 "$dst = "#mnemonic#"($src1 + #$offset)", []>, AddrModeRel {
1601 bits<11> offsetBits;
1603 string ImmOpStr = !cast<string>(ImmOp);
1604 let offsetBits = !if (!eq(ImmOpStr, "s11_3Ext"), offset{13-3},
1605 !if (!eq(ImmOpStr, "s11_2Ext"), offset{12-2},
1606 !if (!eq(ImmOpStr, "s11_1Ext"), offset{11-1},
1607 /* s11_0Ext */ offset{10-0})));
1608 let opExtentBits = !if (!eq(ImmOpStr, "s11_3Ext"), 14,
1609 !if (!eq(ImmOpStr, "s11_2Ext"), 13,
1610 !if (!eq(ImmOpStr, "s11_1Ext"), 12,
1611 /* s11_0Ext */ 11)));
1612 let hasNewValue = !if (!eq(ImmOpStr, "s11_3Ext"), 0, 1);
1614 let IClass = 0b1001;
1617 let Inst{26-25} = offsetBits{10-9};
1618 let Inst{24-21} = MajOp;
1619 let Inst{20-16} = src1;
1620 let Inst{13-5} = offsetBits{8-0};
1621 let Inst{4-0} = dst;
1624 let opExtendable = 3, isExtentSigned = 0, isPredicated = 1 in
1625 class T_pload_io <string mnemonic, RegisterClass RC, bits<4>MajOp,
1626 Operand ImmOp, bit isNot, bit isPredNew>
1627 : LDInst<(outs RC:$dst),
1628 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset),
1629 "if ("#!if(isNot, "!$src1", "$src1")
1630 #!if(isPredNew, ".new", "")
1631 #") $dst = "#mnemonic#"($src2 + #$offset)",
1632 [],"", V2LDST_tc_ld_SLOT01> , AddrModeRel {
1638 string ImmOpStr = !cast<string>(ImmOp);
1640 let offsetBits = !if (!eq(ImmOpStr, "u6_3Ext"), offset{8-3},
1641 !if (!eq(ImmOpStr, "u6_2Ext"), offset{7-2},
1642 !if (!eq(ImmOpStr, "u6_1Ext"), offset{6-1},
1643 /* u6_0Ext */ offset{5-0})));
1644 let opExtentBits = !if (!eq(ImmOpStr, "u6_3Ext"), 9,
1645 !if (!eq(ImmOpStr, "u6_2Ext"), 8,
1646 !if (!eq(ImmOpStr, "u6_1Ext"), 7,
1648 let hasNewValue = !if (!eq(ImmOpStr, "u6_3Ext"), 0, 1);
1649 let isPredicatedNew = isPredNew;
1650 let isPredicatedFalse = isNot;
1652 let IClass = 0b0100;
1656 let Inst{26} = isNot;
1657 let Inst{25} = isPredNew;
1658 let Inst{24-21} = MajOp;
1659 let Inst{20-16} = src2;
1661 let Inst{12-11} = src1;
1662 let Inst{10-5} = offsetBits;
1663 let Inst{4-0} = dst;
1666 let isExtendable = 1, hasSideEffects = 0, addrMode = BaseImmOffset in
1667 multiclass LD_Idxd<string mnemonic, string CextOp, RegisterClass RC,
1668 Operand ImmOp, Operand predImmOp, bits<4>MajOp> {
1669 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
1670 let isPredicable = 1 in
1671 def L2_#NAME#_io : T_load_io <mnemonic, RC, MajOp, ImmOp>;
1674 def L2_p#NAME#t_io : T_pload_io <mnemonic, RC, MajOp, predImmOp, 0, 0>;
1675 def L2_p#NAME#f_io : T_pload_io <mnemonic, RC, MajOp, predImmOp, 1, 0>;
1678 def L2_p#NAME#tnew_io : T_pload_io <mnemonic, RC, MajOp, predImmOp, 0, 1>;
1679 def L2_p#NAME#fnew_io : T_pload_io <mnemonic, RC, MajOp, predImmOp, 1, 1>;
1683 let accessSize = ByteAccess in {
1684 defm loadrb: LD_Idxd <"memb", "LDrib", IntRegs, s11_0Ext, u6_0Ext, 0b1000>;
1685 defm loadrub: LD_Idxd <"memub", "LDriub", IntRegs, s11_0Ext, u6_0Ext, 0b1001>;
1688 let accessSize = HalfWordAccess, opExtentAlign = 1 in {
1689 defm loadrh: LD_Idxd <"memh", "LDrih", IntRegs, s11_1Ext, u6_1Ext, 0b1010>;
1690 defm loadruh: LD_Idxd <"memuh", "LDriuh", IntRegs, s11_1Ext, u6_1Ext, 0b1011>;
1693 let accessSize = WordAccess, opExtentAlign = 2 in
1694 defm loadri: LD_Idxd <"memw", "LDriw", IntRegs, s11_2Ext, u6_2Ext, 0b1100>;
1696 let accessSize = DoubleWordAccess, opExtentAlign = 3 in
1697 defm loadrd: LD_Idxd <"memd", "LDrid", DoubleRegs, s11_3Ext, u6_3Ext, 0b1110>;
1699 let accessSize = HalfWordAccess, opExtentAlign = 1 in {
1700 def L2_loadbsw2_io: T_load_io<"membh", IntRegs, 0b0001, s11_1Ext>;
1701 def L2_loadbzw2_io: T_load_io<"memubh", IntRegs, 0b0011, s11_1Ext>;
1704 let accessSize = WordAccess, opExtentAlign = 2 in {
1705 def L2_loadbzw4_io: T_load_io<"memubh", DoubleRegs, 0b0101, s11_2Ext>;
1706 def L2_loadbsw4_io: T_load_io<"membh", DoubleRegs, 0b0111, s11_2Ext>;
1709 // Patterns to select load-indexed (i.e. load from base+offset).
1710 multiclass Loadx_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred,
1712 def: Pat<(VT (Load AddrFI:$fi)), (VT (MI AddrFI:$fi, 0))>;
1713 def: Pat<(VT (Load (add (i32 IntRegs:$Rs), ImmPred:$Off))),
1714 (VT (MI IntRegs:$Rs, imm:$Off))>;
1715 def: Pat<(VT (Load (i32 IntRegs:$Rs))), (VT (MI IntRegs:$Rs, 0))>;
1718 let AddedComplexity = 20 in {
1719 defm: Loadx_pat<load, i32, s11_2ExtPred, L2_loadri_io>;
1720 defm: Loadx_pat<load, i64, s11_3ExtPred, L2_loadrd_io>;
1721 defm: Loadx_pat<atomic_load_8 , i32, s11_0ExtPred, L2_loadrub_io>;
1722 defm: Loadx_pat<atomic_load_16, i32, s11_1ExtPred, L2_loadruh_io>;
1723 defm: Loadx_pat<atomic_load_32, i32, s11_2ExtPred, L2_loadri_io>;
1724 defm: Loadx_pat<atomic_load_64, i64, s11_3ExtPred, L2_loadrd_io>;
1726 defm: Loadx_pat<extloadi1, i32, s11_0ExtPred, L2_loadrub_io>;
1727 defm: Loadx_pat<extloadi8, i32, s11_0ExtPred, L2_loadrub_io>;
1728 defm: Loadx_pat<extloadi16, i32, s11_1ExtPred, L2_loadruh_io>;
1729 defm: Loadx_pat<sextloadi8, i32, s11_0ExtPred, L2_loadrb_io>;
1730 defm: Loadx_pat<sextloadi16, i32, s11_1ExtPred, L2_loadrh_io>;
1731 defm: Loadx_pat<zextloadi1, i32, s11_0ExtPred, L2_loadrub_io>;
1732 defm: Loadx_pat<zextloadi8, i32, s11_0ExtPred, L2_loadrub_io>;
1733 defm: Loadx_pat<zextloadi16, i32, s11_1ExtPred, L2_loadruh_io>;
1737 // Sign-extending loads of i1 need to replicate the lowest bit throughout
1738 // the 32-bit value. Since the loaded value can only be 0 or 1, 0-v should
1740 let AddedComplexity = 20 in
1741 def: Pat<(i32 (sextloadi1 (i32 IntRegs:$Rs))),
1742 (SUB_ri 0, (L2_loadrub_io IntRegs:$Rs, 0))>;
1744 //===----------------------------------------------------------------------===//
1745 // Post increment load
1746 //===----------------------------------------------------------------------===//
1747 //===----------------------------------------------------------------------===//
1748 // Template class for non-predicated post increment loads with immediate offset.
1749 //===----------------------------------------------------------------------===//
1750 let hasSideEffects = 0, addrMode = PostInc in
1751 class T_load_pi <string mnemonic, RegisterClass RC, Operand ImmOp,
1753 : LDInstPI <(outs RC:$dst, IntRegs:$dst2),
1754 (ins IntRegs:$src1, ImmOp:$offset),
1755 "$dst = "#mnemonic#"($src1++#$offset)" ,
1764 string ImmOpStr = !cast<string>(ImmOp);
1765 let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3},
1766 !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
1767 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
1768 /* s4_0Imm */ offset{3-0})));
1769 let hasNewValue = !if (!eq(ImmOpStr, "s4_3Imm"), 0, 1);
1771 let IClass = 0b1001;
1773 let Inst{27-25} = 0b101;
1774 let Inst{24-21} = MajOp;
1775 let Inst{20-16} = src1;
1776 let Inst{13-12} = 0b00;
1777 let Inst{8-5} = offsetBits;
1778 let Inst{4-0} = dst;
1781 //===----------------------------------------------------------------------===//
1782 // Template class for predicated post increment loads with immediate offset.
1783 //===----------------------------------------------------------------------===//
1784 let isPredicated = 1, hasSideEffects = 0, addrMode = PostInc in
1785 class T_pload_pi <string mnemonic, RegisterClass RC, Operand ImmOp,
1786 bits<4> MajOp, bit isPredNot, bit isPredNew >
1787 : LDInst <(outs RC:$dst, IntRegs:$dst2),
1788 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset),
1789 !if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1790 ") ")#"$dst = "#mnemonic#"($src2++#$offset)",
1800 let isPredicatedNew = isPredNew;
1801 let isPredicatedFalse = isPredNot;
1803 string ImmOpStr = !cast<string>(ImmOp);
1804 let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3},
1805 !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
1806 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
1807 /* s4_0Imm */ offset{3-0})));
1808 let hasNewValue = !if (!eq(ImmOpStr, "s4_3Imm"), 0, 1);
1810 let IClass = 0b1001;
1812 let Inst{27-25} = 0b101;
1813 let Inst{24-21} = MajOp;
1814 let Inst{20-16} = src2;
1816 let Inst{12} = isPredNew;
1817 let Inst{11} = isPredNot;
1818 let Inst{10-9} = src1;
1819 let Inst{8-5} = offsetBits;
1820 let Inst{4-0} = dst;
1823 //===----------------------------------------------------------------------===//
1824 // Multiclass for post increment loads with immediate offset.
1825 //===----------------------------------------------------------------------===//
1827 multiclass LD_PostInc <string mnemonic, string BaseOp, RegisterClass RC,
1828 Operand ImmOp, bits<4> MajOp> {
1829 let BaseOpcode = "POST_"#BaseOp in {
1830 let isPredicable = 1 in
1831 def L2_#NAME#_pi : T_load_pi < mnemonic, RC, ImmOp, MajOp>;
1834 def L2_p#NAME#t_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 0, 0>;
1835 def L2_p#NAME#f_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 1, 0>;
1838 def L2_p#NAME#tnew_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 0, 1>;
1839 def L2_p#NAME#fnew_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 1, 1>;
1843 // post increment byte loads with immediate offset
1844 let accessSize = ByteAccess in {
1845 defm loadrb : LD_PostInc <"memb", "LDrib", IntRegs, s4_0Imm, 0b1000>;
1846 defm loadrub : LD_PostInc <"memub", "LDriub", IntRegs, s4_0Imm, 0b1001>;
1849 // post increment halfword loads with immediate offset
1850 let accessSize = HalfWordAccess, opExtentAlign = 1 in {
1851 defm loadrh : LD_PostInc <"memh", "LDrih", IntRegs, s4_1Imm, 0b1010>;
1852 defm loadruh : LD_PostInc <"memuh", "LDriuh", IntRegs, s4_1Imm, 0b1011>;
1855 // post increment word loads with immediate offset
1856 let accessSize = WordAccess, opExtentAlign = 2 in
1857 defm loadri : LD_PostInc <"memw", "LDriw", IntRegs, s4_2Imm, 0b1100>;
1859 // post increment doubleword loads with immediate offset
1860 let accessSize = DoubleWordAccess, opExtentAlign = 3 in
1861 defm loadrd : LD_PostInc <"memd", "LDrid", DoubleRegs, s4_3Imm, 0b1110>;
1863 // Rd=memb[u]h(Rx++#s4:1)
1864 // Rdd=memb[u]h(Rx++#s4:2)
1865 let accessSize = HalfWordAccess, opExtentAlign = 1 in {
1866 def L2_loadbsw2_pi : T_load_pi <"membh", IntRegs, s4_1Imm, 0b0001>;
1867 def L2_loadbzw2_pi : T_load_pi <"memubh", IntRegs, s4_1Imm, 0b0011>;
1869 let accessSize = WordAccess, opExtentAlign = 2, hasNewValue = 0 in {
1870 def L2_loadbsw4_pi : T_load_pi <"membh", DoubleRegs, s4_2Imm, 0b0111>;
1871 def L2_loadbzw4_pi : T_load_pi <"memubh", DoubleRegs, s4_2Imm, 0b0101>;
1874 //===----------------------------------------------------------------------===//
1875 // Template class for post increment loads with register offset.
1876 //===----------------------------------------------------------------------===//
1877 let hasSideEffects = 0, addrMode = PostInc in
1878 class T_load_pr <string mnemonic, RegisterClass RC, bits<4> MajOp,
1879 MemAccessSize AccessSz>
1880 : LDInstPI <(outs RC:$dst, IntRegs:$_dst_),
1881 (ins IntRegs:$src1, ModRegs:$src2),
1882 "$dst = "#mnemonic#"($src1++$src2)" ,
1883 [], "$src1 = $_dst_" > {
1888 let accessSize = AccessSz;
1889 let IClass = 0b1001;
1891 let Inst{27-25} = 0b110;
1892 let Inst{24-21} = MajOp;
1893 let Inst{20-16} = src1;
1894 let Inst{13} = src2;
1897 let Inst{4-0} = dst;
1900 let hasNewValue = 1 in {
1901 def L2_loadrb_pr : T_load_pr <"memb", IntRegs, 0b1000, ByteAccess>;
1902 def L2_loadrub_pr : T_load_pr <"memub", IntRegs, 0b1001, ByteAccess>;
1903 def L2_loadrh_pr : T_load_pr <"memh", IntRegs, 0b1010, HalfWordAccess>;
1904 def L2_loadruh_pr : T_load_pr <"memuh", IntRegs, 0b1011, HalfWordAccess>;
1905 def L2_loadri_pr : T_load_pr <"memw", IntRegs, 0b1100, WordAccess>;
1907 def L2_loadbzw2_pr : T_load_pr <"memubh", IntRegs, 0b0011, HalfWordAccess>;
1910 def L2_loadrd_pr : T_load_pr <"memd", DoubleRegs, 0b1110, DoubleWordAccess>;
1911 def L2_loadbzw4_pr : T_load_pr <"memubh", DoubleRegs, 0b0101, WordAccess>;
1914 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 13,
1915 isPseudo = 1, Defs = [R10,R11,D5], hasSideEffects = 0 in
1916 def LDriw_pred : LDInst2<(outs PredRegs:$dst),
1918 "Error; should not emit",
1921 let Defs = [R29, R30, R31], Uses = [R30], hasSideEffects = 0 in
1922 def L2_deallocframe : LDInst<(outs), (ins),
1925 let IClass = 0b1001;
1927 let Inst{27-16} = 0b000000011110;
1929 let Inst{4-0} = 0b11110;
1932 // Load / Post increment circular addressing mode.
1933 let Uses = [CS], hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
1934 class T_load_pcr<string mnemonic, RegisterClass RC, bits<4> MajOp>
1935 : LDInst <(outs RC:$dst, IntRegs:$_dst_),
1936 (ins IntRegs:$Rz, ModRegs:$Mu),
1937 "$dst = "#mnemonic#"($Rz ++ I:circ($Mu))", [],
1943 let IClass = 0b1001;
1945 let Inst{27-25} = 0b100;
1946 let Inst{24-21} = MajOp;
1947 let Inst{20-16} = Rz;
1952 let Inst{4-0} = dst;
1955 let accessSize = ByteAccess in {
1956 def L2_loadrb_pcr : T_load_pcr <"memb", IntRegs, 0b1000>;
1957 def L2_loadrub_pcr : T_load_pcr <"memub", IntRegs, 0b1001>;
1960 let accessSize = HalfWordAccess in {
1961 def L2_loadrh_pcr : T_load_pcr <"memh", IntRegs, 0b1010>;
1962 def L2_loadruh_pcr : T_load_pcr <"memuh", IntRegs, 0b1011>;
1963 def L2_loadbsw2_pcr : T_load_pcr <"membh", IntRegs, 0b0001>;
1964 def L2_loadbzw2_pcr : T_load_pcr <"memubh", IntRegs, 0b0011>;
1967 let accessSize = WordAccess in {
1968 def L2_loadri_pcr : T_load_pcr <"memw", IntRegs, 0b1100>;
1969 let hasNewValue = 0 in {
1970 def L2_loadbzw4_pcr : T_load_pcr <"memubh", DoubleRegs, 0b0101>;
1971 def L2_loadbsw4_pcr : T_load_pcr <"membh", DoubleRegs, 0b0111>;
1975 let accessSize = DoubleWordAccess in
1976 def L2_loadrd_pcr : T_load_pcr <"memd", DoubleRegs, 0b1110>;
1978 //===----------------------------------------------------------------------===//
1979 // Circular loads with immediate offset.
1980 //===----------------------------------------------------------------------===//
1981 let Uses = [CS], mayLoad = 1, hasSideEffects = 0, hasNewValue = 1 in
1982 class T_load_pci <string mnemonic, RegisterClass RC,
1983 Operand ImmOp, bits<4> MajOp>
1984 : LDInstPI<(outs RC:$dst, IntRegs:$_dst_),
1985 (ins IntRegs:$Rz, ImmOp:$offset, ModRegs:$Mu),
1986 "$dst = "#mnemonic#"($Rz ++ #$offset:circ($Mu))", [],
1994 string ImmOpStr = !cast<string>(ImmOp);
1995 let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3},
1996 !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
1997 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
1998 /* s4_0Imm */ offset{3-0})));
1999 let IClass = 0b1001;
2000 let Inst{27-25} = 0b100;
2001 let Inst{24-21} = MajOp;
2002 let Inst{20-16} = Rz;
2006 let Inst{8-5} = offsetBits;
2007 let Inst{4-0} = dst;
2010 // Byte variants of circ load
2011 let accessSize = ByteAccess in {
2012 def L2_loadrb_pci : T_load_pci <"memb", IntRegs, s4_0Imm, 0b1000>;
2013 def L2_loadrub_pci : T_load_pci <"memub", IntRegs, s4_0Imm, 0b1001>;
2016 // Half word variants of circ load
2017 let accessSize = HalfWordAccess in {
2018 def L2_loadrh_pci : T_load_pci <"memh", IntRegs, s4_1Imm, 0b1010>;
2019 def L2_loadruh_pci : T_load_pci <"memuh", IntRegs, s4_1Imm, 0b1011>;
2020 def L2_loadbzw2_pci : T_load_pci <"memubh", IntRegs, s4_1Imm, 0b0011>;
2021 def L2_loadbsw2_pci : T_load_pci <"membh", IntRegs, s4_1Imm, 0b0001>;
2024 // Word variants of circ load
2025 let accessSize = WordAccess in
2026 def L2_loadri_pci : T_load_pci <"memw", IntRegs, s4_2Imm, 0b1100>;
2028 let accessSize = WordAccess, hasNewValue = 0 in {
2029 def L2_loadbzw4_pci : T_load_pci <"memubh", DoubleRegs, s4_2Imm, 0b0101>;
2030 def L2_loadbsw4_pci : T_load_pci <"membh", DoubleRegs, s4_2Imm, 0b0111>;
2033 let accessSize = DoubleWordAccess, hasNewValue = 0 in
2034 def L2_loadrd_pci : T_load_pci <"memd", DoubleRegs, s4_3Imm, 0b1110>;
2036 // L[24]_load[wd]_locked: Load word/double with lock.
2038 class T_load_locked <string mnemonic, RegisterClass RC>
2039 : LD0Inst <(outs RC:$dst),
2041 "$dst = "#mnemonic#"($src)"> {
2044 let IClass = 0b1001;
2045 let Inst{27-21} = 0b0010000;
2046 let Inst{20-16} = src;
2047 let Inst{13-12} = !if (!eq(mnemonic, "memd_locked"), 0b01, 0b00);
2048 let Inst{4-0} = dst;
2050 let hasNewValue = 1, accessSize = WordAccess, opNewValue = 0 in
2051 def L2_loadw_locked : T_load_locked <"memw_locked", IntRegs>;
2052 let accessSize = DoubleWordAccess in
2053 def L4_loadd_locked : T_load_locked <"memd_locked", DoubleRegs>;
2055 // S[24]_store[wd]_locked: Store word/double conditionally.
2056 let isSoloAX = 1, isPredicateLate = 1 in
2057 class T_store_locked <string mnemonic, RegisterClass RC>
2058 : ST0Inst <(outs PredRegs:$Pd), (ins IntRegs:$Rs, RC:$Rt),
2059 mnemonic#"($Rs, $Pd) = $Rt"> {
2064 let IClass = 0b1010;
2065 let Inst{27-23} = 0b00001;
2066 let Inst{22} = !if (!eq(mnemonic, "memw_locked"), 0b0, 0b1);
2068 let Inst{20-16} = Rs;
2069 let Inst{12-8} = Rt;
2073 let accessSize = WordAccess in
2074 def S2_storew_locked : T_store_locked <"memw_locked", IntRegs>;
2076 let accessSize = DoubleWordAccess in
2077 def S4_stored_locked : T_store_locked <"memd_locked", DoubleRegs>;
2079 //===----------------------------------------------------------------------===//
2080 // Bit-reversed loads with auto-increment register
2081 //===----------------------------------------------------------------------===//
2082 let hasSideEffects = 0 in
2083 class T_load_pbr<string mnemonic, RegisterClass RC,
2084 MemAccessSize addrSize, bits<4> majOp>
2086 <(outs RC:$dst, IntRegs:$_dst_),
2087 (ins IntRegs:$Rz, ModRegs:$Mu),
2088 "$dst = "#mnemonic#"($Rz ++ $Mu:brev)" ,
2089 [] , "$Rz = $_dst_" > {
2091 let accessSize = addrSize;
2097 let IClass = 0b1001;
2099 let Inst{27-25} = 0b111;
2100 let Inst{24-21} = majOp;
2101 let Inst{20-16} = Rz;
2105 let Inst{4-0} = dst;
2108 let hasNewValue =1, opNewValue = 0 in {
2109 def L2_loadrb_pbr : T_load_pbr <"memb", IntRegs, ByteAccess, 0b1000>;
2110 def L2_loadrub_pbr : T_load_pbr <"memub", IntRegs, ByteAccess, 0b1001>;
2111 def L2_loadrh_pbr : T_load_pbr <"memh", IntRegs, HalfWordAccess, 0b1010>;
2112 def L2_loadruh_pbr : T_load_pbr <"memuh", IntRegs, HalfWordAccess, 0b1011>;
2113 def L2_loadbsw2_pbr : T_load_pbr <"membh", IntRegs, HalfWordAccess, 0b0001>;
2114 def L2_loadbzw2_pbr : T_load_pbr <"memubh", IntRegs, HalfWordAccess, 0b0011>;
2115 def L2_loadri_pbr : T_load_pbr <"memw", IntRegs, WordAccess, 0b1100>;
2118 def L2_loadbzw4_pbr : T_load_pbr <"memubh", DoubleRegs, WordAccess, 0b0101>;
2119 def L2_loadbsw4_pbr : T_load_pbr <"membh", DoubleRegs, WordAccess, 0b0111>;
2120 def L2_loadrd_pbr : T_load_pbr <"memd", DoubleRegs, DoubleWordAccess, 0b1110>;
2122 //===----------------------------------------------------------------------===//
2124 //===----------------------------------------------------------------------===//
2126 //===----------------------------------------------------------------------===//
2128 //===----------------------------------------------------------------------===//
2129 //===----------------------------------------------------------------------===//
2131 //===----------------------------------------------------------------------===//
2133 //===----------------------------------------------------------------------===//
2135 //===----------------------------------------------------------------------===//
2136 //===----------------------------------------------------------------------===//
2138 //===----------------------------------------------------------------------===//
2140 //===----------------------------------------------------------------------===//
2142 //===----------------------------------------------------------------------===//
2144 //===----------------------------------------------------------------------===//
2146 // MPYS / Multipy signed/unsigned halfwords
2147 //Rd=mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:rnd][:sat]
2148 //===----------------------------------------------------------------------===//
2150 let hasNewValue = 1, opNewValue = 0 in
2151 class T_M2_mpy < bits<2> LHbits, bit isSat, bit isRnd,
2152 bit hasShift, bit isUnsigned>
2153 : MInst < (outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
2154 "$Rd = "#!if(isUnsigned,"mpyu","mpy")#"($Rs."#!if(LHbits{1},"h","l")
2155 #", $Rt."#!if(LHbits{0},"h)","l)")
2156 #!if(hasShift,":<<1","")
2157 #!if(isRnd,":rnd","")
2158 #!if(isSat,":sat",""),
2159 [], "", M_tc_3x_SLOT23 > {
2164 let IClass = 0b1110;
2166 let Inst{27-24} = 0b1100;
2167 let Inst{23} = hasShift;
2168 let Inst{22} = isUnsigned;
2169 let Inst{21} = isRnd;
2170 let Inst{7} = isSat;
2171 let Inst{6-5} = LHbits;
2173 let Inst{20-16} = Rs;
2174 let Inst{12-8} = Rt;
2177 //Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1]
2178 def M2_mpy_ll_s1: T_M2_mpy<0b00, 0, 0, 1, 0>;
2179 def M2_mpy_ll_s0: T_M2_mpy<0b00, 0, 0, 0, 0>;
2180 def M2_mpy_lh_s1: T_M2_mpy<0b01, 0, 0, 1, 0>;
2181 def M2_mpy_lh_s0: T_M2_mpy<0b01, 0, 0, 0, 0>;
2182 def M2_mpy_hl_s1: T_M2_mpy<0b10, 0, 0, 1, 0>;
2183 def M2_mpy_hl_s0: T_M2_mpy<0b10, 0, 0, 0, 0>;
2184 def M2_mpy_hh_s1: T_M2_mpy<0b11, 0, 0, 1, 0>;
2185 def M2_mpy_hh_s0: T_M2_mpy<0b11, 0, 0, 0, 0>;
2187 //Rd=mpyu(Rs.[H|L],Rt.[H|L])[:<<1]
2188 def M2_mpyu_ll_s1: T_M2_mpy<0b00, 0, 0, 1, 1>;
2189 def M2_mpyu_ll_s0: T_M2_mpy<0b00, 0, 0, 0, 1>;
2190 def M2_mpyu_lh_s1: T_M2_mpy<0b01, 0, 0, 1, 1>;
2191 def M2_mpyu_lh_s0: T_M2_mpy<0b01, 0, 0, 0, 1>;
2192 def M2_mpyu_hl_s1: T_M2_mpy<0b10, 0, 0, 1, 1>;
2193 def M2_mpyu_hl_s0: T_M2_mpy<0b10, 0, 0, 0, 1>;
2194 def M2_mpyu_hh_s1: T_M2_mpy<0b11, 0, 0, 1, 1>;
2195 def M2_mpyu_hh_s0: T_M2_mpy<0b11, 0, 0, 0, 1>;
2197 //Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1]:rnd
2198 def M2_mpy_rnd_ll_s1: T_M2_mpy <0b00, 0, 1, 1, 0>;
2199 def M2_mpy_rnd_ll_s0: T_M2_mpy <0b00, 0, 1, 0, 0>;
2200 def M2_mpy_rnd_lh_s1: T_M2_mpy <0b01, 0, 1, 1, 0>;
2201 def M2_mpy_rnd_lh_s0: T_M2_mpy <0b01, 0, 1, 0, 0>;
2202 def M2_mpy_rnd_hl_s1: T_M2_mpy <0b10, 0, 1, 1, 0>;
2203 def M2_mpy_rnd_hl_s0: T_M2_mpy <0b10, 0, 1, 0, 0>;
2204 def M2_mpy_rnd_hh_s1: T_M2_mpy <0b11, 0, 1, 1, 0>;
2205 def M2_mpy_rnd_hh_s0: T_M2_mpy <0b11, 0, 1, 0, 0>;
2207 //Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1][:sat]
2208 //Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1][:rnd][:sat]
2209 let Defs = [USR_OVF] in {
2210 def M2_mpy_sat_ll_s1: T_M2_mpy <0b00, 1, 0, 1, 0>;
2211 def M2_mpy_sat_ll_s0: T_M2_mpy <0b00, 1, 0, 0, 0>;
2212 def M2_mpy_sat_lh_s1: T_M2_mpy <0b01, 1, 0, 1, 0>;
2213 def M2_mpy_sat_lh_s0: T_M2_mpy <0b01, 1, 0, 0, 0>;
2214 def M2_mpy_sat_hl_s1: T_M2_mpy <0b10, 1, 0, 1, 0>;
2215 def M2_mpy_sat_hl_s0: T_M2_mpy <0b10, 1, 0, 0, 0>;
2216 def M2_mpy_sat_hh_s1: T_M2_mpy <0b11, 1, 0, 1, 0>;
2217 def M2_mpy_sat_hh_s0: T_M2_mpy <0b11, 1, 0, 0, 0>;
2219 def M2_mpy_sat_rnd_ll_s1: T_M2_mpy <0b00, 1, 1, 1, 0>;
2220 def M2_mpy_sat_rnd_ll_s0: T_M2_mpy <0b00, 1, 1, 0, 0>;
2221 def M2_mpy_sat_rnd_lh_s1: T_M2_mpy <0b01, 1, 1, 1, 0>;
2222 def M2_mpy_sat_rnd_lh_s0: T_M2_mpy <0b01, 1, 1, 0, 0>;
2223 def M2_mpy_sat_rnd_hl_s1: T_M2_mpy <0b10, 1, 1, 1, 0>;
2224 def M2_mpy_sat_rnd_hl_s0: T_M2_mpy <0b10, 1, 1, 0, 0>;
2225 def M2_mpy_sat_rnd_hh_s1: T_M2_mpy <0b11, 1, 1, 1, 0>;
2226 def M2_mpy_sat_rnd_hh_s0: T_M2_mpy <0b11, 1, 1, 0, 0>;
2229 //===----------------------------------------------------------------------===//
2231 // MPYS / Multipy signed/unsigned halfwords and add/subtract the
2232 // result from the accumulator.
2233 //Rx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat]
2234 //===----------------------------------------------------------------------===//
2236 let hasNewValue = 1, opNewValue = 0 in
2237 class T_M2_mpy_acc < bits<2> LHbits, bit isSat, bit isNac,
2238 bit hasShift, bit isUnsigned >
2239 : MInst_acc<(outs IntRegs:$Rx), (ins IntRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt),
2240 "$Rx "#!if(isNac,"-= ","+= ")#!if(isUnsigned,"mpyu","mpy")
2241 #"($Rs."#!if(LHbits{1},"h","l")
2242 #", $Rt."#!if(LHbits{0},"h)","l)")
2243 #!if(hasShift,":<<1","")
2244 #!if(isSat,":sat",""),
2245 [], "$dst2 = $Rx", M_tc_3x_SLOT23 > {
2250 let IClass = 0b1110;
2251 let Inst{27-24} = 0b1110;
2252 let Inst{23} = hasShift;
2253 let Inst{22} = isUnsigned;
2254 let Inst{21} = isNac;
2255 let Inst{7} = isSat;
2256 let Inst{6-5} = LHbits;
2258 let Inst{20-16} = Rs;
2259 let Inst{12-8} = Rt;
2262 //Rx += mpy(Rs.[H|L],Rt.[H|L])[:<<1]
2263 def M2_mpy_acc_ll_s1: T_M2_mpy_acc <0b00, 0, 0, 1, 0>;
2264 def M2_mpy_acc_ll_s0: T_M2_mpy_acc <0b00, 0, 0, 0, 0>;
2265 def M2_mpy_acc_lh_s1: T_M2_mpy_acc <0b01, 0, 0, 1, 0>;
2266 def M2_mpy_acc_lh_s0: T_M2_mpy_acc <0b01, 0, 0, 0, 0>;
2267 def M2_mpy_acc_hl_s1: T_M2_mpy_acc <0b10, 0, 0, 1, 0>;
2268 def M2_mpy_acc_hl_s0: T_M2_mpy_acc <0b10, 0, 0, 0, 0>;
2269 def M2_mpy_acc_hh_s1: T_M2_mpy_acc <0b11, 0, 0, 1, 0>;
2270 def M2_mpy_acc_hh_s0: T_M2_mpy_acc <0b11, 0, 0, 0, 0>;
2272 //Rx += mpyu(Rs.[H|L],Rt.[H|L])[:<<1]
2273 def M2_mpyu_acc_ll_s1: T_M2_mpy_acc <0b00, 0, 0, 1, 1>;
2274 def M2_mpyu_acc_ll_s0: T_M2_mpy_acc <0b00, 0, 0, 0, 1>;
2275 def M2_mpyu_acc_lh_s1: T_M2_mpy_acc <0b01, 0, 0, 1, 1>;
2276 def M2_mpyu_acc_lh_s0: T_M2_mpy_acc <0b01, 0, 0, 0, 1>;
2277 def M2_mpyu_acc_hl_s1: T_M2_mpy_acc <0b10, 0, 0, 1, 1>;
2278 def M2_mpyu_acc_hl_s0: T_M2_mpy_acc <0b10, 0, 0, 0, 1>;
2279 def M2_mpyu_acc_hh_s1: T_M2_mpy_acc <0b11, 0, 0, 1, 1>;
2280 def M2_mpyu_acc_hh_s0: T_M2_mpy_acc <0b11, 0, 0, 0, 1>;
2282 //Rx -= mpy(Rs.[H|L],Rt.[H|L])[:<<1]
2283 def M2_mpy_nac_ll_s1: T_M2_mpy_acc <0b00, 0, 1, 1, 0>;
2284 def M2_mpy_nac_ll_s0: T_M2_mpy_acc <0b00, 0, 1, 0, 0>;
2285 def M2_mpy_nac_lh_s1: T_M2_mpy_acc <0b01, 0, 1, 1, 0>;
2286 def M2_mpy_nac_lh_s0: T_M2_mpy_acc <0b01, 0, 1, 0, 0>;
2287 def M2_mpy_nac_hl_s1: T_M2_mpy_acc <0b10, 0, 1, 1, 0>;
2288 def M2_mpy_nac_hl_s0: T_M2_mpy_acc <0b10, 0, 1, 0, 0>;
2289 def M2_mpy_nac_hh_s1: T_M2_mpy_acc <0b11, 0, 1, 1, 0>;
2290 def M2_mpy_nac_hh_s0: T_M2_mpy_acc <0b11, 0, 1, 0, 0>;
2292 //Rx -= mpyu(Rs.[H|L],Rt.[H|L])[:<<1]
2293 def M2_mpyu_nac_ll_s1: T_M2_mpy_acc <0b00, 0, 1, 1, 1>;
2294 def M2_mpyu_nac_ll_s0: T_M2_mpy_acc <0b00, 0, 1, 0, 1>;
2295 def M2_mpyu_nac_lh_s1: T_M2_mpy_acc <0b01, 0, 1, 1, 1>;
2296 def M2_mpyu_nac_lh_s0: T_M2_mpy_acc <0b01, 0, 1, 0, 1>;
2297 def M2_mpyu_nac_hl_s1: T_M2_mpy_acc <0b10, 0, 1, 1, 1>;
2298 def M2_mpyu_nac_hl_s0: T_M2_mpy_acc <0b10, 0, 1, 0, 1>;
2299 def M2_mpyu_nac_hh_s1: T_M2_mpy_acc <0b11, 0, 1, 1, 1>;
2300 def M2_mpyu_nac_hh_s0: T_M2_mpy_acc <0b11, 0, 1, 0, 1>;
2302 //Rx += mpy(Rs.[H|L],Rt.[H|L])[:<<1]:sat
2303 def M2_mpy_acc_sat_ll_s1: T_M2_mpy_acc <0b00, 1, 0, 1, 0>;
2304 def M2_mpy_acc_sat_ll_s0: T_M2_mpy_acc <0b00, 1, 0, 0, 0>;
2305 def M2_mpy_acc_sat_lh_s1: T_M2_mpy_acc <0b01, 1, 0, 1, 0>;
2306 def M2_mpy_acc_sat_lh_s0: T_M2_mpy_acc <0b01, 1, 0, 0, 0>;
2307 def M2_mpy_acc_sat_hl_s1: T_M2_mpy_acc <0b10, 1, 0, 1, 0>;
2308 def M2_mpy_acc_sat_hl_s0: T_M2_mpy_acc <0b10, 1, 0, 0, 0>;
2309 def M2_mpy_acc_sat_hh_s1: T_M2_mpy_acc <0b11, 1, 0, 1, 0>;
2310 def M2_mpy_acc_sat_hh_s0: T_M2_mpy_acc <0b11, 1, 0, 0, 0>;
2312 //Rx -= mpy(Rs.[H|L],Rt.[H|L])[:<<1]:sat
2313 def M2_mpy_nac_sat_ll_s1: T_M2_mpy_acc <0b00, 1, 1, 1, 0>;
2314 def M2_mpy_nac_sat_ll_s0: T_M2_mpy_acc <0b00, 1, 1, 0, 0>;
2315 def M2_mpy_nac_sat_lh_s1: T_M2_mpy_acc <0b01, 1, 1, 1, 0>;
2316 def M2_mpy_nac_sat_lh_s0: T_M2_mpy_acc <0b01, 1, 1, 0, 0>;
2317 def M2_mpy_nac_sat_hl_s1: T_M2_mpy_acc <0b10, 1, 1, 1, 0>;
2318 def M2_mpy_nac_sat_hl_s0: T_M2_mpy_acc <0b10, 1, 1, 0, 0>;
2319 def M2_mpy_nac_sat_hh_s1: T_M2_mpy_acc <0b11, 1, 1, 1, 0>;
2320 def M2_mpy_nac_sat_hh_s0: T_M2_mpy_acc <0b11, 1, 1, 0, 0>;
2322 //===----------------------------------------------------------------------===//
2324 // MPYS / Multipy signed/unsigned halfwords and add/subtract the
2325 // result from the 64-bit destination register.
2326 //Rxx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat]
2327 //===----------------------------------------------------------------------===//
2329 class T_M2_mpyd_acc < bits<2> LHbits, bit isNac, bit hasShift, bit isUnsigned>
2330 : MInst_acc<(outs DoubleRegs:$Rxx),
2331 (ins DoubleRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt),
2332 "$Rxx "#!if(isNac,"-= ","+= ")#!if(isUnsigned,"mpyu","mpy")
2333 #"($Rs."#!if(LHbits{1},"h","l")
2334 #", $Rt."#!if(LHbits{0},"h)","l)")
2335 #!if(hasShift,":<<1",""),
2336 [], "$dst2 = $Rxx", M_tc_3x_SLOT23 > {
2341 let IClass = 0b1110;
2343 let Inst{27-24} = 0b0110;
2344 let Inst{23} = hasShift;
2345 let Inst{22} = isUnsigned;
2346 let Inst{21} = isNac;
2348 let Inst{6-5} = LHbits;
2349 let Inst{4-0} = Rxx;
2350 let Inst{20-16} = Rs;
2351 let Inst{12-8} = Rt;
2354 def M2_mpyd_acc_hh_s0: T_M2_mpyd_acc <0b11, 0, 0, 0>;
2355 def M2_mpyd_acc_hl_s0: T_M2_mpyd_acc <0b10, 0, 0, 0>;
2356 def M2_mpyd_acc_lh_s0: T_M2_mpyd_acc <0b01, 0, 0, 0>;
2357 def M2_mpyd_acc_ll_s0: T_M2_mpyd_acc <0b00, 0, 0, 0>;
2359 def M2_mpyd_acc_hh_s1: T_M2_mpyd_acc <0b11, 0, 1, 0>;
2360 def M2_mpyd_acc_hl_s1: T_M2_mpyd_acc <0b10, 0, 1, 0>;
2361 def M2_mpyd_acc_lh_s1: T_M2_mpyd_acc <0b01, 0, 1, 0>;
2362 def M2_mpyd_acc_ll_s1: T_M2_mpyd_acc <0b00, 0, 1, 0>;
2364 def M2_mpyd_nac_hh_s0: T_M2_mpyd_acc <0b11, 1, 0, 0>;
2365 def M2_mpyd_nac_hl_s0: T_M2_mpyd_acc <0b10, 1, 0, 0>;
2366 def M2_mpyd_nac_lh_s0: T_M2_mpyd_acc <0b01, 1, 0, 0>;
2367 def M2_mpyd_nac_ll_s0: T_M2_mpyd_acc <0b00, 1, 0, 0>;
2369 def M2_mpyd_nac_hh_s1: T_M2_mpyd_acc <0b11, 1, 1, 0>;
2370 def M2_mpyd_nac_hl_s1: T_M2_mpyd_acc <0b10, 1, 1, 0>;
2371 def M2_mpyd_nac_lh_s1: T_M2_mpyd_acc <0b01, 1, 1, 0>;
2372 def M2_mpyd_nac_ll_s1: T_M2_mpyd_acc <0b00, 1, 1, 0>;
2374 def M2_mpyud_acc_hh_s0: T_M2_mpyd_acc <0b11, 0, 0, 1>;
2375 def M2_mpyud_acc_hl_s0: T_M2_mpyd_acc <0b10, 0, 0, 1>;
2376 def M2_mpyud_acc_lh_s0: T_M2_mpyd_acc <0b01, 0, 0, 1>;
2377 def M2_mpyud_acc_ll_s0: T_M2_mpyd_acc <0b00, 0, 0, 1>;
2379 def M2_mpyud_acc_hh_s1: T_M2_mpyd_acc <0b11, 0, 1, 1>;
2380 def M2_mpyud_acc_hl_s1: T_M2_mpyd_acc <0b10, 0, 1, 1>;
2381 def M2_mpyud_acc_lh_s1: T_M2_mpyd_acc <0b01, 0, 1, 1>;
2382 def M2_mpyud_acc_ll_s1: T_M2_mpyd_acc <0b00, 0, 1, 1>;
2384 def M2_mpyud_nac_hh_s0: T_M2_mpyd_acc <0b11, 1, 0, 1>;
2385 def M2_mpyud_nac_hl_s0: T_M2_mpyd_acc <0b10, 1, 0, 1>;
2386 def M2_mpyud_nac_lh_s0: T_M2_mpyd_acc <0b01, 1, 0, 1>;
2387 def M2_mpyud_nac_ll_s0: T_M2_mpyd_acc <0b00, 1, 0, 1>;
2389 def M2_mpyud_nac_hh_s1: T_M2_mpyd_acc <0b11, 1, 1, 1>;
2390 def M2_mpyud_nac_hl_s1: T_M2_mpyd_acc <0b10, 1, 1, 1>;
2391 def M2_mpyud_nac_lh_s1: T_M2_mpyd_acc <0b01, 1, 1, 1>;
2392 def M2_mpyud_nac_ll_s1: T_M2_mpyd_acc <0b00, 1, 1, 1>;
2394 //===----------------------------------------------------------------------===//
2395 // Template Class -- Vector Multipy
2396 // Used for complex multiply real or imaginary, dual multiply and even halfwords
2397 //===----------------------------------------------------------------------===//
2398 class T_M2_vmpy < string opc, bits<3> MajOp, bits<3> MinOp, bit hasShift,
2399 bit isRnd, bit isSat >
2400 : MInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
2401 "$Rdd = "#opc#"($Rss, $Rtt)"#!if(hasShift,":<<1","")
2402 #!if(isRnd,":rnd","")
2403 #!if(isSat,":sat",""),
2409 let IClass = 0b1110;
2411 let Inst{27-24} = 0b1000;
2412 let Inst{23-21} = MajOp;
2413 let Inst{7-5} = MinOp;
2414 let Inst{4-0} = Rdd;
2415 let Inst{20-16} = Rss;
2416 let Inst{12-8} = Rtt;
2419 // Vector complex multiply imaginary: Rdd=vcmpyi(Rss,Rtt)[:<<1]:sat
2420 let Defs = [USR_OVF] in {
2421 def M2_vcmpy_s1_sat_i: T_M2_vmpy <"vcmpyi", 0b110, 0b110, 1, 0, 1>;
2422 def M2_vcmpy_s0_sat_i: T_M2_vmpy <"vcmpyi", 0b010, 0b110, 0, 0, 1>;
2425 // Vector complex multiply real: Rdd=vcmpyr(Rss,Rtt)[:<<1]:sat
2426 def M2_vcmpy_s1_sat_r: T_M2_vmpy <"vcmpyr", 0b101, 0b110, 1, 0, 1>;
2427 def M2_vcmpy_s0_sat_r: T_M2_vmpy <"vcmpyr", 0b001, 0b110, 0, 0, 1>;
2429 // Vector dual multiply: Rdd=vdmpy(Rss,Rtt)[:<<1]:sat
2430 def M2_vdmpys_s1: T_M2_vmpy <"vdmpy", 0b100, 0b100, 1, 0, 1>;
2431 def M2_vdmpys_s0: T_M2_vmpy <"vdmpy", 0b000, 0b100, 0, 0, 1>;
2433 // Vector multiply even halfwords: Rdd=vmpyeh(Rss,Rtt)[:<<1]:sat
2434 def M2_vmpy2es_s1: T_M2_vmpy <"vmpyeh", 0b100, 0b110, 1, 0, 1>;
2435 def M2_vmpy2es_s0: T_M2_vmpy <"vmpyeh", 0b000, 0b110, 0, 0, 1>;
2437 //Rdd=vmpywoh(Rss,Rtt)[:<<1][:rnd]:sat
2438 def M2_mmpyh_s0: T_M2_vmpy <"vmpywoh", 0b000, 0b111, 0, 0, 1>;
2439 def M2_mmpyh_s1: T_M2_vmpy <"vmpywoh", 0b100, 0b111, 1, 0, 1>;
2440 def M2_mmpyh_rs0: T_M2_vmpy <"vmpywoh", 0b001, 0b111, 0, 1, 1>;
2441 def M2_mmpyh_rs1: T_M2_vmpy <"vmpywoh", 0b101, 0b111, 1, 1, 1>;
2443 //Rdd=vmpyweh(Rss,Rtt)[:<<1][:rnd]:sat
2444 def M2_mmpyl_s0: T_M2_vmpy <"vmpyweh", 0b000, 0b101, 0, 0, 1>;
2445 def M2_mmpyl_s1: T_M2_vmpy <"vmpyweh", 0b100, 0b101, 1, 0, 1>;
2446 def M2_mmpyl_rs0: T_M2_vmpy <"vmpyweh", 0b001, 0b101, 0, 1, 1>;
2447 def M2_mmpyl_rs1: T_M2_vmpy <"vmpyweh", 0b101, 0b101, 1, 1, 1>;
2449 //Rdd=vmpywouh(Rss,Rtt)[:<<1][:rnd]:sat
2450 def M2_mmpyuh_s0: T_M2_vmpy <"vmpywouh", 0b010, 0b111, 0, 0, 1>;
2451 def M2_mmpyuh_s1: T_M2_vmpy <"vmpywouh", 0b110, 0b111, 1, 0, 1>;
2452 def M2_mmpyuh_rs0: T_M2_vmpy <"vmpywouh", 0b011, 0b111, 0, 1, 1>;
2453 def M2_mmpyuh_rs1: T_M2_vmpy <"vmpywouh", 0b111, 0b111, 1, 1, 1>;
2455 //Rdd=vmpyweuh(Rss,Rtt)[:<<1][:rnd]:sat
2456 def M2_mmpyul_s0: T_M2_vmpy <"vmpyweuh", 0b010, 0b101, 0, 0, 1>;
2457 def M2_mmpyul_s1: T_M2_vmpy <"vmpyweuh", 0b110, 0b101, 1, 0, 1>;
2458 def M2_mmpyul_rs0: T_M2_vmpy <"vmpyweuh", 0b011, 0b101, 0, 1, 1>;
2459 def M2_mmpyul_rs1: T_M2_vmpy <"vmpyweuh", 0b111, 0b101, 1, 1, 1>;
2461 let hasNewValue = 1, opNewValue = 0 in
2462 class T_MType_mpy <string mnemonic, bits<4> RegTyBits, RegisterClass RC,
2463 bits<3> MajOp, bits<3> MinOp, bit isSat = 0, bit isRnd = 0,
2464 string op2Suffix = "", bit isRaw = 0, bit isHi = 0 >
2465 : MInst <(outs IntRegs:$dst), (ins RC:$src1, RC:$src2),
2467 #"($src1, $src2"#op2Suffix#")"
2468 #!if(MajOp{2}, ":<<1", "")
2469 #!if(isRnd, ":rnd", "")
2470 #!if(isSat, ":sat", "")
2471 #!if(isRaw, !if(isHi, ":raw:hi", ":raw:lo"), ""), [] > {
2476 let IClass = 0b1110;
2478 let Inst{27-24} = RegTyBits;
2479 let Inst{23-21} = MajOp;
2480 let Inst{20-16} = src1;
2482 let Inst{12-8} = src2;
2483 let Inst{7-5} = MinOp;
2484 let Inst{4-0} = dst;
2487 class T_MType_vrcmpy <string mnemonic, bits<3> MajOp, bits<3> MinOp, bit isHi>
2488 : T_MType_mpy <mnemonic, 0b1001, DoubleRegs, MajOp, MinOp, 1, 1, "", 1, isHi>;
2490 class T_MType_dd <string mnemonic, bits<3> MajOp, bits<3> MinOp,
2491 bit isSat = 0, bit isRnd = 0 >
2492 : T_MType_mpy <mnemonic, 0b1001, DoubleRegs, MajOp, MinOp, isSat, isRnd>;
2494 class T_MType_rr1 <string mnemonic, bits<3> MajOp, bits<3> MinOp,
2495 bit isSat = 0, bit isRnd = 0 >
2496 : T_MType_mpy<mnemonic, 0b1101, IntRegs, MajOp, MinOp, isSat, isRnd>;
2498 class T_MType_rr2 <string mnemonic, bits<3> MajOp, bits<3> MinOp,
2499 bit isSat = 0, bit isRnd = 0, string op2str = "" >
2500 : T_MType_mpy<mnemonic, 0b1101, IntRegs, MajOp, MinOp, isSat, isRnd, op2str>;
2502 def M2_vradduh : T_MType_dd <"vradduh", 0b000, 0b001, 0, 0>;
2503 def M2_vdmpyrs_s0 : T_MType_dd <"vdmpy", 0b000, 0b000, 1, 1>;
2504 def M2_vdmpyrs_s1 : T_MType_dd <"vdmpy", 0b100, 0b000, 1, 1>;
2506 let CextOpcode = "mpyi", InputType = "reg" in
2507 def M2_mpyi : T_MType_rr1 <"mpyi", 0b000, 0b000>, ImmRegRel;
2509 def M2_mpy_up : T_MType_rr1 <"mpy", 0b000, 0b001>;
2510 def M2_mpyu_up : T_MType_rr1 <"mpyu", 0b010, 0b001>;
2512 def M2_dpmpyss_rnd_s0 : T_MType_rr1 <"mpy", 0b001, 0b001, 0, 1>;
2514 def M2_vmpy2s_s0pack : T_MType_rr1 <"vmpyh", 0b001, 0b111, 1, 1>;
2515 def M2_vmpy2s_s1pack : T_MType_rr1 <"vmpyh", 0b101, 0b111, 1, 1>;
2517 def M2_hmmpyh_rs1 : T_MType_rr2 <"mpy", 0b101, 0b100, 1, 1, ".h">;
2518 def M2_hmmpyl_rs1 : T_MType_rr2 <"mpy", 0b111, 0b100, 1, 1, ".l">;
2520 def M2_cmpyrs_s0 : T_MType_rr2 <"cmpy", 0b001, 0b110, 1, 1>;
2521 def M2_cmpyrs_s1 : T_MType_rr2 <"cmpy", 0b101, 0b110, 1, 1>;
2522 def M2_cmpyrsc_s0 : T_MType_rr2 <"cmpy", 0b011, 0b110, 1, 1, "*">;
2523 def M2_cmpyrsc_s1 : T_MType_rr2 <"cmpy", 0b111, 0b110, 1, 1, "*">;
2526 def M2_vraddh : T_MType_dd <"vraddh", 0b001, 0b111, 0>;
2527 def M2_mpysu_up : T_MType_rr1 <"mpysu", 0b011, 0b001, 0>;
2528 def M2_mpy_up_s1 : T_MType_rr1 <"mpy", 0b101, 0b010, 0>;
2529 def M2_mpy_up_s1_sat : T_MType_rr1 <"mpy", 0b111, 0b000, 1>;
2531 def M2_hmmpyh_s1 : T_MType_rr2 <"mpy", 0b101, 0b000, 1, 0, ".h">;
2532 def M2_hmmpyl_s1 : T_MType_rr2 <"mpy", 0b101, 0b001, 1, 0, ".l">;
2534 def: Pat<(i32 (mul I32:$src1, I32:$src2)), (M2_mpyi I32:$src1, I32:$src2)>;
2535 def: Pat<(i32 (mulhs I32:$src1, I32:$src2)), (M2_mpy_up I32:$src1, I32:$src2)>;
2536 def: Pat<(i32 (mulhu I32:$src1, I32:$src2)), (M2_mpyu_up I32:$src1, I32:$src2)>;
2538 let hasNewValue = 1, opNewValue = 0 in
2539 class T_MType_mpy_ri <bit isNeg, Operand ImmOp, list<dag> pattern>
2540 : MInst < (outs IntRegs:$Rd), (ins IntRegs:$Rs, ImmOp:$u8),
2541 "$Rd ="#!if(isNeg, "- ", "+ ")#"mpyi($Rs, #$u8)" ,
2542 pattern, "", M_tc_3x_SLOT23> {
2547 let IClass = 0b1110;
2549 let Inst{27-24} = 0b0000;
2550 let Inst{23} = isNeg;
2553 let Inst{20-16} = Rs;
2554 let Inst{12-5} = u8;
2557 let isExtendable = 1, opExtentBits = 8, opExtendable = 2 in
2558 def M2_mpysip : T_MType_mpy_ri <0, u8Ext,
2559 [(set (i32 IntRegs:$Rd), (mul IntRegs:$Rs, u8ExtPred:$u8))]>;
2561 def M2_mpysin : T_MType_mpy_ri <1, u8Imm,
2562 [(set (i32 IntRegs:$Rd), (ineg (mul IntRegs:$Rs,
2565 // Assember mapped to M2_mpyi
2566 let isAsmParserOnly = 1 in
2567 def M2_mpyui : MInst<(outs IntRegs:$dst),
2568 (ins IntRegs:$src1, IntRegs:$src2),
2569 "$dst = mpyui($src1, $src2)">;
2572 // s9 is NOT the same as m9 - but it works.. so far.
2573 // Assembler maps to either Rd=+mpyi(Rs,#u8) or Rd=-mpyi(Rs,#u8)
2574 // depending on the value of m9. See Arch Spec.
2575 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 9,
2576 CextOpcode = "mpyi", InputType = "imm", hasNewValue = 1,
2577 isAsmParserOnly = 1 in
2578 def M2_mpysmi : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9Ext:$src2),
2579 "$dst = mpyi($src1, #$src2)",
2580 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
2581 s9ExtPred:$src2))]>, ImmRegRel;
2583 let hasNewValue = 1, isExtendable = 1, opExtentBits = 8, opExtendable = 3,
2584 InputType = "imm" in
2585 class T_MType_acc_ri <string mnemonic, bits<3> MajOp, Operand ImmOp,
2586 list<dag> pattern = []>
2587 : MInst < (outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, ImmOp:$src3),
2588 "$dst "#mnemonic#"($src2, #$src3)",
2589 pattern, "$src1 = $dst", M_tc_2_SLOT23> {
2594 let IClass = 0b1110;
2596 let Inst{27-26} = 0b00;
2597 let Inst{25-23} = MajOp;
2598 let Inst{20-16} = src2;
2600 let Inst{12-5} = src3;
2601 let Inst{4-0} = dst;
2604 let InputType = "reg", hasNewValue = 1 in
2605 class T_MType_acc_rr <string mnemonic, bits<3> MajOp, bits<3> MinOp,
2606 bit isSwap = 0, list<dag> pattern = [], bit hasNot = 0,
2607 bit isSat = 0, bit isShift = 0>
2608 : MInst < (outs IntRegs:$dst),
2609 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
2610 "$dst "#mnemonic#"($src2, "#!if(hasNot, "~$src3)","$src3)")
2611 #!if(isShift, ":<<1", "")
2612 #!if(isSat, ":sat", ""),
2613 pattern, "$src1 = $dst", M_tc_2_SLOT23 > {
2618 let IClass = 0b1110;
2620 let Inst{27-24} = 0b1111;
2621 let Inst{23-21} = MajOp;
2622 let Inst{20-16} = !if(isSwap, src3, src2);
2624 let Inst{12-8} = !if(isSwap, src2, src3);
2625 let Inst{7-5} = MinOp;
2626 let Inst{4-0} = dst;
2629 let CextOpcode = "MPYI_acc", Itinerary = M_tc_3x_SLOT23 in {
2630 def M2_macsip : T_MType_acc_ri <"+= mpyi", 0b010, u8Ext,
2631 [(set (i32 IntRegs:$dst),
2632 (add (mul IntRegs:$src2, u8ExtPred:$src3),
2633 IntRegs:$src1))]>, ImmRegRel;
2635 def M2_maci : T_MType_acc_rr <"+= mpyi", 0b000, 0b000, 0,
2636 [(set (i32 IntRegs:$dst),
2637 (add (mul IntRegs:$src2, IntRegs:$src3),
2638 IntRegs:$src1))]>, ImmRegRel;
2641 let CextOpcode = "ADD_acc" in {
2642 let isExtentSigned = 1 in
2643 def M2_accii : T_MType_acc_ri <"+= add", 0b100, s8Ext,
2644 [(set (i32 IntRegs:$dst),
2645 (add (add (i32 IntRegs:$src2), s8_16ExtPred:$src3),
2646 (i32 IntRegs:$src1)))]>, ImmRegRel;
2648 def M2_acci : T_MType_acc_rr <"+= add", 0b000, 0b001, 0,
2649 [(set (i32 IntRegs:$dst),
2650 (add (add (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
2651 (i32 IntRegs:$src1)))]>, ImmRegRel;
2654 let CextOpcode = "SUB_acc" in {
2655 let isExtentSigned = 1 in
2656 def M2_naccii : T_MType_acc_ri <"-= add", 0b101, s8Ext>, ImmRegRel;
2658 def M2_nacci : T_MType_acc_rr <"-= add", 0b100, 0b001, 0>, ImmRegRel;
2661 let Itinerary = M_tc_3x_SLOT23 in
2662 def M2_macsin : T_MType_acc_ri <"-= mpyi", 0b011, u8Ext>;
2664 def M2_xor_xacc : T_MType_acc_rr < "^= xor", 0b100, 0b011, 0>;
2665 def M2_subacc : T_MType_acc_rr <"+= sub", 0b000, 0b011, 1>;
2667 class T_MType_acc_pat1 <InstHexagon MI, SDNode firstOp, SDNode secOp,
2669 : Pat <(secOp IntRegs:$src1, (firstOp IntRegs:$src2, ImmPred:$src3)),
2670 (MI IntRegs:$src1, IntRegs:$src2, ImmPred:$src3)>;
2672 class T_MType_acc_pat2 <InstHexagon MI, SDNode firstOp, SDNode secOp>
2673 : Pat <(i32 (secOp IntRegs:$src1, (firstOp IntRegs:$src2, IntRegs:$src3))),
2674 (MI IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
2676 def : T_MType_acc_pat2 <M2_xor_xacc, xor, xor>;
2677 def : T_MType_acc_pat1 <M2_macsin, mul, sub, u8ExtPred>;
2679 def : T_MType_acc_pat1 <M2_naccii, add, sub, s8_16ExtPred>;
2680 def : T_MType_acc_pat2 <M2_nacci, add, sub>;
2682 //===----------------------------------------------------------------------===//
2683 // Template Class -- XType Vector Instructions
2684 //===----------------------------------------------------------------------===//
2685 class T_XTYPE_Vect < string opc, bits<3> MajOp, bits<3> MinOp, bit isConj >
2686 : MInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
2687 "$Rdd = "#opc#"($Rss, $Rtt"#!if(isConj,"*)",")"),
2693 let IClass = 0b1110;
2695 let Inst{27-24} = 0b1000;
2696 let Inst{23-21} = MajOp;
2697 let Inst{7-5} = MinOp;
2698 let Inst{4-0} = Rdd;
2699 let Inst{20-16} = Rss;
2700 let Inst{12-8} = Rtt;
2703 class T_XTYPE_Vect_acc < string opc, bits<3> MajOp, bits<3> MinOp, bit isConj >
2704 : MInst <(outs DoubleRegs:$Rdd),
2705 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt),
2706 "$Rdd += "#opc#"($Rss, $Rtt"#!if(isConj,"*)",")"),
2707 [], "$dst2 = $Rdd",M_tc_3x_SLOT23 > {
2712 let IClass = 0b1110;
2714 let Inst{27-24} = 0b1010;
2715 let Inst{23-21} = MajOp;
2716 let Inst{7-5} = MinOp;
2717 let Inst{4-0} = Rdd;
2718 let Inst{20-16} = Rss;
2719 let Inst{12-8} = Rtt;
2722 class T_XTYPE_Vect_diff < bits<3> MajOp, string opc >
2723 : MInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rtt, DoubleRegs:$Rss),
2724 "$Rdd = "#opc#"($Rtt, $Rss)",
2725 [], "",M_tc_2_SLOT23 > {
2730 let IClass = 0b1110;
2732 let Inst{27-24} = 0b1000;
2733 let Inst{23-21} = MajOp;
2734 let Inst{7-5} = 0b000;
2735 let Inst{4-0} = Rdd;
2736 let Inst{20-16} = Rss;
2737 let Inst{12-8} = Rtt;
2740 // Vector reduce add unsigned bytes: Rdd32=vrmpybu(Rss32,Rtt32)
2741 def A2_vraddub: T_XTYPE_Vect <"vraddub", 0b010, 0b001, 0>;
2742 def A2_vraddub_acc: T_XTYPE_Vect_acc <"vraddub", 0b010, 0b001, 0>;
2744 // Vector sum of absolute differences unsigned bytes: Rdd=vrsadub(Rss,Rtt)
2745 def A2_vrsadub: T_XTYPE_Vect <"vrsadub", 0b010, 0b010, 0>;
2746 def A2_vrsadub_acc: T_XTYPE_Vect_acc <"vrsadub", 0b010, 0b010, 0>;
2748 // Vector absolute difference words: Rdd=vabsdiffw(Rtt,Rss)
2749 def M2_vabsdiffw: T_XTYPE_Vect_diff<0b001, "vabsdiffw">;
2751 // Vector absolute difference: Rdd=vabsdiffh(Rtt,Rss)
2752 def M2_vabsdiffh: T_XTYPE_Vect_diff<0b011, "vabsdiffh">;
2754 // Vector reduce complex multiply real or imaginary:
2755 // Rdd[+]=vrcmpy[ir](Rss,Rtt[*])
2756 def M2_vrcmpyi_s0: T_XTYPE_Vect <"vrcmpyi", 0b000, 0b000, 0>;
2757 def M2_vrcmpyi_s0c: T_XTYPE_Vect <"vrcmpyi", 0b010, 0b000, 1>;
2758 def M2_vrcmaci_s0: T_XTYPE_Vect_acc <"vrcmpyi", 0b000, 0b000, 0>;
2759 def M2_vrcmaci_s0c: T_XTYPE_Vect_acc <"vrcmpyi", 0b010, 0b000, 1>;
2761 def M2_vrcmpyr_s0: T_XTYPE_Vect <"vrcmpyr", 0b000, 0b001, 0>;
2762 def M2_vrcmpyr_s0c: T_XTYPE_Vect <"vrcmpyr", 0b011, 0b001, 1>;
2763 def M2_vrcmacr_s0: T_XTYPE_Vect_acc <"vrcmpyr", 0b000, 0b001, 0>;
2764 def M2_vrcmacr_s0c: T_XTYPE_Vect_acc <"vrcmpyr", 0b011, 0b001, 1>;
2766 // Vector reduce halfwords:
2767 // Rdd[+]=vrmpyh(Rss,Rtt)
2768 def M2_vrmpy_s0: T_XTYPE_Vect <"vrmpyh", 0b000, 0b010, 0>;
2769 def M2_vrmac_s0: T_XTYPE_Vect_acc <"vrmpyh", 0b000, 0b010, 0>;
2771 //===----------------------------------------------------------------------===//
2772 // Template Class -- Vector Multipy with accumulation.
2773 // Used for complex multiply real or imaginary, dual multiply and even halfwords
2774 //===----------------------------------------------------------------------===//
2775 let Defs = [USR_OVF] in
2776 class T_M2_vmpy_acc_sat < string opc, bits<3> MajOp, bits<3> MinOp,
2777 bit hasShift, bit isRnd >
2778 : MInst <(outs DoubleRegs:$Rxx),
2779 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt),
2780 "$Rxx += "#opc#"($Rss, $Rtt)"#!if(hasShift,":<<1","")
2781 #!if(isRnd,":rnd","")#":sat",
2782 [], "$dst2 = $Rxx",M_tc_3x_SLOT23 > {
2787 let IClass = 0b1110;
2789 let Inst{27-24} = 0b1010;
2790 let Inst{23-21} = MajOp;
2791 let Inst{7-5} = MinOp;
2792 let Inst{4-0} = Rxx;
2793 let Inst{20-16} = Rss;
2794 let Inst{12-8} = Rtt;
2797 class T_M2_vmpy_acc < string opc, bits<3> MajOp, bits<3> MinOp,
2798 bit hasShift, bit isRnd >
2799 : MInst <(outs DoubleRegs:$Rxx),
2800 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt),
2801 "$Rxx += "#opc#"($Rss, $Rtt)"#!if(hasShift,":<<1","")
2802 #!if(isRnd,":rnd",""),
2803 [], "$dst2 = $Rxx",M_tc_3x_SLOT23 > {
2808 let IClass = 0b1110;
2810 let Inst{27-24} = 0b1010;
2811 let Inst{23-21} = MajOp;
2812 let Inst{7-5} = MinOp;
2813 let Inst{4-0} = Rxx;
2814 let Inst{20-16} = Rss;
2815 let Inst{12-8} = Rtt;
2818 // Vector multiply word by signed half with accumulation
2819 // Rxx+=vmpyw[eo]h(Rss,Rtt)[:<<1][:rnd]:sat
2820 def M2_mmacls_s1: T_M2_vmpy_acc_sat <"vmpyweh", 0b100, 0b101, 1, 0>;
2821 def M2_mmacls_s0: T_M2_vmpy_acc_sat <"vmpyweh", 0b000, 0b101, 0, 0>;
2822 def M2_mmacls_rs1: T_M2_vmpy_acc_sat <"vmpyweh", 0b101, 0b101, 1, 1>;
2823 def M2_mmacls_rs0: T_M2_vmpy_acc_sat <"vmpyweh", 0b001, 0b101, 0, 1>;
2825 def M2_mmachs_s1: T_M2_vmpy_acc_sat <"vmpywoh", 0b100, 0b111, 1, 0>;
2826 def M2_mmachs_s0: T_M2_vmpy_acc_sat <"vmpywoh", 0b000, 0b111, 0, 0>;
2827 def M2_mmachs_rs1: T_M2_vmpy_acc_sat <"vmpywoh", 0b101, 0b111, 1, 1>;
2828 def M2_mmachs_rs0: T_M2_vmpy_acc_sat <"vmpywoh", 0b001, 0b111, 0, 1>;
2830 // Vector multiply word by unsigned half with accumulation
2831 // Rxx+=vmpyw[eo]uh(Rss,Rtt)[:<<1][:rnd]:sat
2832 def M2_mmaculs_s1: T_M2_vmpy_acc_sat <"vmpyweuh", 0b110, 0b101, 1, 0>;
2833 def M2_mmaculs_s0: T_M2_vmpy_acc_sat <"vmpyweuh", 0b010, 0b101, 0, 0>;
2834 def M2_mmaculs_rs1: T_M2_vmpy_acc_sat <"vmpyweuh", 0b111, 0b101, 1, 1>;
2835 def M2_mmaculs_rs0: T_M2_vmpy_acc_sat <"vmpyweuh", 0b011, 0b101, 0, 1>;
2837 def M2_mmacuhs_s1: T_M2_vmpy_acc_sat <"vmpywouh", 0b110, 0b111, 1, 0>;
2838 def M2_mmacuhs_s0: T_M2_vmpy_acc_sat <"vmpywouh", 0b010, 0b111, 0, 0>;
2839 def M2_mmacuhs_rs1: T_M2_vmpy_acc_sat <"vmpywouh", 0b111, 0b111, 1, 1>;
2840 def M2_mmacuhs_rs0: T_M2_vmpy_acc_sat <"vmpywouh", 0b011, 0b111, 0, 1>;
2842 // Vector multiply even halfwords with accumulation
2843 // Rxx+=vmpyeh(Rss,Rtt)[:<<1][:sat]
2844 def M2_vmac2es: T_M2_vmpy_acc <"vmpyeh", 0b001, 0b010, 0, 0>;
2845 def M2_vmac2es_s1: T_M2_vmpy_acc_sat <"vmpyeh", 0b100, 0b110, 1, 0>;
2846 def M2_vmac2es_s0: T_M2_vmpy_acc_sat <"vmpyeh", 0b000, 0b110, 0, 0>;
2848 // Vector dual multiply with accumulation
2849 // Rxx+=vdmpy(Rss,Rtt)[:sat]
2850 def M2_vdmacs_s1: T_M2_vmpy_acc_sat <"vdmpy", 0b100, 0b100, 1, 0>;
2851 def M2_vdmacs_s0: T_M2_vmpy_acc_sat <"vdmpy", 0b000, 0b100, 0, 0>;
2853 // Vector complex multiply real or imaginary with accumulation
2854 // Rxx+=vcmpy[ir](Rss,Rtt):sat
2855 def M2_vcmac_s0_sat_r: T_M2_vmpy_acc_sat <"vcmpyr", 0b001, 0b100, 0, 0>;
2856 def M2_vcmac_s0_sat_i: T_M2_vmpy_acc_sat <"vcmpyi", 0b010, 0b100, 0, 0>;
2858 //===----------------------------------------------------------------------===//
2859 // Template Class -- Multiply signed/unsigned halfwords with and without
2860 // saturation and rounding
2861 //===----------------------------------------------------------------------===//
2862 class T_M2_mpyd < bits<2> LHbits, bit isRnd, bit hasShift, bit isUnsigned >
2863 : MInst < (outs DoubleRegs:$Rdd), (ins IntRegs:$Rs, IntRegs:$Rt),
2864 "$Rdd = "#!if(isUnsigned,"mpyu","mpy")#"($Rs."#!if(LHbits{1},"h","l")
2865 #", $Rt."#!if(LHbits{0},"h)","l)")
2866 #!if(hasShift,":<<1","")
2867 #!if(isRnd,":rnd",""),
2873 let IClass = 0b1110;
2875 let Inst{27-24} = 0b0100;
2876 let Inst{23} = hasShift;
2877 let Inst{22} = isUnsigned;
2878 let Inst{21} = isRnd;
2879 let Inst{6-5} = LHbits;
2880 let Inst{4-0} = Rdd;
2881 let Inst{20-16} = Rs;
2882 let Inst{12-8} = Rt;
2885 def M2_mpyd_hh_s0: T_M2_mpyd<0b11, 0, 0, 0>;
2886 def M2_mpyd_hl_s0: T_M2_mpyd<0b10, 0, 0, 0>;
2887 def M2_mpyd_lh_s0: T_M2_mpyd<0b01, 0, 0, 0>;
2888 def M2_mpyd_ll_s0: T_M2_mpyd<0b00, 0, 0, 0>;
2890 def M2_mpyd_hh_s1: T_M2_mpyd<0b11, 0, 1, 0>;
2891 def M2_mpyd_hl_s1: T_M2_mpyd<0b10, 0, 1, 0>;
2892 def M2_mpyd_lh_s1: T_M2_mpyd<0b01, 0, 1, 0>;
2893 def M2_mpyd_ll_s1: T_M2_mpyd<0b00, 0, 1, 0>;
2895 def M2_mpyd_rnd_hh_s0: T_M2_mpyd<0b11, 1, 0, 0>;
2896 def M2_mpyd_rnd_hl_s0: T_M2_mpyd<0b10, 1, 0, 0>;
2897 def M2_mpyd_rnd_lh_s0: T_M2_mpyd<0b01, 1, 0, 0>;
2898 def M2_mpyd_rnd_ll_s0: T_M2_mpyd<0b00, 1, 0, 0>;
2900 def M2_mpyd_rnd_hh_s1: T_M2_mpyd<0b11, 1, 1, 0>;
2901 def M2_mpyd_rnd_hl_s1: T_M2_mpyd<0b10, 1, 1, 0>;
2902 def M2_mpyd_rnd_lh_s1: T_M2_mpyd<0b01, 1, 1, 0>;
2903 def M2_mpyd_rnd_ll_s1: T_M2_mpyd<0b00, 1, 1, 0>;
2905 //Rdd=mpyu(Rs.[HL],Rt.[HL])[:<<1]
2906 def M2_mpyud_hh_s0: T_M2_mpyd<0b11, 0, 0, 1>;
2907 def M2_mpyud_hl_s0: T_M2_mpyd<0b10, 0, 0, 1>;
2908 def M2_mpyud_lh_s0: T_M2_mpyd<0b01, 0, 0, 1>;
2909 def M2_mpyud_ll_s0: T_M2_mpyd<0b00, 0, 0, 1>;
2911 def M2_mpyud_hh_s1: T_M2_mpyd<0b11, 0, 1, 1>;
2912 def M2_mpyud_hl_s1: T_M2_mpyd<0b10, 0, 1, 1>;
2913 def M2_mpyud_lh_s1: T_M2_mpyd<0b01, 0, 1, 1>;
2914 def M2_mpyud_ll_s1: T_M2_mpyd<0b00, 0, 1, 1>;
2916 //===----------------------------------------------------------------------===//
2917 // Template Class for xtype mpy:
2920 // multiply 32X32 and use full result
2921 //===----------------------------------------------------------------------===//
2922 let hasSideEffects = 0 in
2923 class T_XTYPE_mpy64 <string mnemonic, bits<3> MajOp, bits<3> MinOp,
2924 bit isSat, bit hasShift, bit isConj>
2925 : MInst <(outs DoubleRegs:$Rdd),
2926 (ins IntRegs:$Rs, IntRegs:$Rt),
2927 "$Rdd = "#mnemonic#"($Rs, $Rt"#!if(isConj,"*)",")")
2928 #!if(hasShift,":<<1","")
2929 #!if(isSat,":sat",""),
2935 let IClass = 0b1110;
2937 let Inst{27-24} = 0b0101;
2938 let Inst{23-21} = MajOp;
2939 let Inst{20-16} = Rs;
2940 let Inst{12-8} = Rt;
2941 let Inst{7-5} = MinOp;
2942 let Inst{4-0} = Rdd;
2945 //===----------------------------------------------------------------------===//
2946 // Template Class for xtype mpy with accumulation into 64-bit:
2949 // multiply 32X32 and use full result
2950 //===----------------------------------------------------------------------===//
2951 class T_XTYPE_mpy64_acc <string op1, string op2, bits<3> MajOp, bits<3> MinOp,
2952 bit isSat, bit hasShift, bit isConj>
2953 : MInst <(outs DoubleRegs:$Rxx),
2954 (ins DoubleRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt),
2955 "$Rxx "#op2#"= "#op1#"($Rs, $Rt"#!if(isConj,"*)",")")
2956 #!if(hasShift,":<<1","")
2957 #!if(isSat,":sat",""),
2959 [] , "$dst2 = $Rxx" > {
2964 let IClass = 0b1110;
2966 let Inst{27-24} = 0b0111;
2967 let Inst{23-21} = MajOp;
2968 let Inst{20-16} = Rs;
2969 let Inst{12-8} = Rt;
2970 let Inst{7-5} = MinOp;
2971 let Inst{4-0} = Rxx;
2974 // MPY - Multiply and use full result
2975 // Rdd = mpy[u](Rs,Rt)
2976 def M2_dpmpyss_s0 : T_XTYPE_mpy64 < "mpy", 0b000, 0b000, 0, 0, 0>;
2977 def M2_dpmpyuu_s0 : T_XTYPE_mpy64 < "mpyu", 0b010, 0b000, 0, 0, 0>;
2979 // Rxx[+-]= mpy[u](Rs,Rt)
2980 def M2_dpmpyss_acc_s0 : T_XTYPE_mpy64_acc < "mpy", "+", 0b000, 0b000, 0, 0, 0>;
2981 def M2_dpmpyss_nac_s0 : T_XTYPE_mpy64_acc < "mpy", "-", 0b001, 0b000, 0, 0, 0>;
2982 def M2_dpmpyuu_acc_s0 : T_XTYPE_mpy64_acc < "mpyu", "+", 0b010, 0b000, 0, 0, 0>;
2983 def M2_dpmpyuu_nac_s0 : T_XTYPE_mpy64_acc < "mpyu", "-", 0b011, 0b000, 0, 0, 0>;
2985 // Complex multiply real or imaginary
2986 // Rxx=cmpy[ir](Rs,Rt)
2987 def M2_cmpyi_s0 : T_XTYPE_mpy64 < "cmpyi", 0b000, 0b001, 0, 0, 0>;
2988 def M2_cmpyr_s0 : T_XTYPE_mpy64 < "cmpyr", 0b000, 0b010, 0, 0, 0>;
2990 // Rxx+=cmpy[ir](Rs,Rt)
2991 def M2_cmaci_s0 : T_XTYPE_mpy64_acc < "cmpyi", "+", 0b000, 0b001, 0, 0, 0>;
2992 def M2_cmacr_s0 : T_XTYPE_mpy64_acc < "cmpyr", "+", 0b000, 0b010, 0, 0, 0>;
2995 // Rdd=cmpy(Rs,Rt)[:<<]:sat
2996 def M2_cmpys_s0 : T_XTYPE_mpy64 < "cmpy", 0b000, 0b110, 1, 0, 0>;
2997 def M2_cmpys_s1 : T_XTYPE_mpy64 < "cmpy", 0b100, 0b110, 1, 1, 0>;
2999 // Rdd=cmpy(Rs,Rt*)[:<<]:sat
3000 def M2_cmpysc_s0 : T_XTYPE_mpy64 < "cmpy", 0b010, 0b110, 1, 0, 1>;
3001 def M2_cmpysc_s1 : T_XTYPE_mpy64 < "cmpy", 0b110, 0b110, 1, 1, 1>;
3003 // Rxx[-+]=cmpy(Rs,Rt)[:<<1]:sat
3004 def M2_cmacs_s0 : T_XTYPE_mpy64_acc < "cmpy", "+", 0b000, 0b110, 1, 0, 0>;
3005 def M2_cnacs_s0 : T_XTYPE_mpy64_acc < "cmpy", "-", 0b000, 0b111, 1, 0, 0>;
3006 def M2_cmacs_s1 : T_XTYPE_mpy64_acc < "cmpy", "+", 0b100, 0b110, 1, 1, 0>;
3007 def M2_cnacs_s1 : T_XTYPE_mpy64_acc < "cmpy", "-", 0b100, 0b111, 1, 1, 0>;
3009 // Rxx[-+]=cmpy(Rs,Rt*)[:<<1]:sat
3010 def M2_cmacsc_s0 : T_XTYPE_mpy64_acc < "cmpy", "+", 0b010, 0b110, 1, 0, 1>;
3011 def M2_cnacsc_s0 : T_XTYPE_mpy64_acc < "cmpy", "-", 0b010, 0b111, 1, 0, 1>;
3012 def M2_cmacsc_s1 : T_XTYPE_mpy64_acc < "cmpy", "+", 0b110, 0b110, 1, 1, 1>;
3013 def M2_cnacsc_s1 : T_XTYPE_mpy64_acc < "cmpy", "-", 0b110, 0b111, 1, 1, 1>;
3015 // Vector multiply halfwords
3016 // Rdd=vmpyh(Rs,Rt)[:<<]:sat
3017 //let Defs = [USR_OVF] in {
3018 def M2_vmpy2s_s1 : T_XTYPE_mpy64 < "vmpyh", 0b100, 0b101, 1, 1, 0>;
3019 def M2_vmpy2s_s0 : T_XTYPE_mpy64 < "vmpyh", 0b000, 0b101, 1, 0, 0>;
3022 // Rxx+=vmpyh(Rs,Rt)[:<<1][:sat]
3023 def M2_vmac2 : T_XTYPE_mpy64_acc < "vmpyh", "+", 0b001, 0b001, 0, 0, 0>;
3024 def M2_vmac2s_s1 : T_XTYPE_mpy64_acc < "vmpyh", "+", 0b100, 0b101, 1, 1, 0>;
3025 def M2_vmac2s_s0 : T_XTYPE_mpy64_acc < "vmpyh", "+", 0b000, 0b101, 1, 0, 0>;
3027 def: Pat<(i64 (mul (i64 (anyext (i32 IntRegs:$src1))),
3028 (i64 (anyext (i32 IntRegs:$src2))))),
3029 (M2_dpmpyuu_s0 IntRegs:$src1, IntRegs:$src2)>;
3031 def: Pat<(i64 (mul (i64 (sext (i32 IntRegs:$src1))),
3032 (i64 (sext (i32 IntRegs:$src2))))),
3033 (M2_dpmpyss_s0 IntRegs:$src1, IntRegs:$src2)>;
3035 def: Pat<(i64 (mul (is_sext_i32:$src1),
3036 (is_sext_i32:$src2))),
3037 (M2_dpmpyss_s0 (LoReg DoubleRegs:$src1), (LoReg DoubleRegs:$src2))>;
3039 // Multiply and accumulate, use full result.
3040 // Rxx[+-]=mpy(Rs,Rt)
3042 def: Pat<(i64 (add (i64 DoubleRegs:$src1),
3043 (mul (i64 (sext (i32 IntRegs:$src2))),
3044 (i64 (sext (i32 IntRegs:$src3)))))),
3045 (M2_dpmpyss_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
3047 def: Pat<(i64 (sub (i64 DoubleRegs:$src1),
3048 (mul (i64 (sext (i32 IntRegs:$src2))),
3049 (i64 (sext (i32 IntRegs:$src3)))))),
3050 (M2_dpmpyss_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
3052 def: Pat<(i64 (add (i64 DoubleRegs:$src1),
3053 (mul (i64 (anyext (i32 IntRegs:$src2))),
3054 (i64 (anyext (i32 IntRegs:$src3)))))),
3055 (M2_dpmpyuu_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
3057 def: Pat<(i64 (add (i64 DoubleRegs:$src1),
3058 (mul (i64 (zext (i32 IntRegs:$src2))),
3059 (i64 (zext (i32 IntRegs:$src3)))))),
3060 (M2_dpmpyuu_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
3062 def: Pat<(i64 (sub (i64 DoubleRegs:$src1),
3063 (mul (i64 (anyext (i32 IntRegs:$src2))),
3064 (i64 (anyext (i32 IntRegs:$src3)))))),
3065 (M2_dpmpyuu_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
3067 def: Pat<(i64 (sub (i64 DoubleRegs:$src1),
3068 (mul (i64 (zext (i32 IntRegs:$src2))),
3069 (i64 (zext (i32 IntRegs:$src3)))))),
3070 (M2_dpmpyuu_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
3072 //===----------------------------------------------------------------------===//
3074 //===----------------------------------------------------------------------===//
3076 //===----------------------------------------------------------------------===//
3078 //===----------------------------------------------------------------------===//
3079 //===----------------------------------------------------------------------===//
3081 //===----------------------------------------------------------------------===//
3083 //===----------------------------------------------------------------------===//
3085 //===----------------------------------------------------------------------===//
3086 //===----------------------------------------------------------------------===//
3088 //===----------------------------------------------------------------------===//
3090 //===----------------------------------------------------------------------===//
3092 //===----------------------------------------------------------------------===//
3093 //===----------------------------------------------------------------------===//
3095 //===----------------------------------------------------------------------===//
3097 //===----------------------------------------------------------------------===//
3099 //===----------------------------------------------------------------------===//
3101 // Store doubleword.
3102 //===----------------------------------------------------------------------===//
3103 // Template class for non-predicated post increment stores with immediate offset
3104 //===----------------------------------------------------------------------===//
3105 let isPredicable = 1, hasSideEffects = 0, addrMode = PostInc in
3106 class T_store_pi <string mnemonic, RegisterClass RC, Operand ImmOp,
3107 bits<4> MajOp, bit isHalf >
3108 : STInst <(outs IntRegs:$_dst_),
3109 (ins IntRegs:$src1, ImmOp:$offset, RC:$src2),
3110 mnemonic#"($src1++#$offset) = $src2"#!if(isHalf, ".h", ""),
3111 [], "$src1 = $_dst_" >,
3118 string ImmOpStr = !cast<string>(ImmOp);
3119 let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3},
3120 !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
3121 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
3122 /* s4_0Imm */ offset{3-0})));
3123 let isNVStorable = !if (!eq(ImmOpStr, "s4_3Imm"), 0, 1);
3125 let IClass = 0b1010;
3127 let Inst{27-25} = 0b101;
3128 let Inst{24-21} = MajOp;
3129 let Inst{20-16} = src1;
3131 let Inst{12-8} = src2;
3133 let Inst{6-3} = offsetBits;
3137 //===----------------------------------------------------------------------===//
3138 // Template class for predicated post increment stores with immediate offset
3139 //===----------------------------------------------------------------------===//
3140 let isPredicated = 1, hasSideEffects = 0, addrMode = PostInc in
3141 class T_pstore_pi <string mnemonic, RegisterClass RC, Operand ImmOp,
3142 bits<4> MajOp, bit isHalf, bit isPredNot, bit isPredNew >
3143 : STInst <(outs IntRegs:$_dst_),
3144 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset, RC:$src3),
3145 !if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
3146 ") ")#mnemonic#"($src2++#$offset) = $src3"#!if(isHalf, ".h", ""),
3147 [], "$src2 = $_dst_" >,
3155 string ImmOpStr = !cast<string>(ImmOp);
3156 let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3},
3157 !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
3158 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
3159 /* s4_0Imm */ offset{3-0})));
3161 let isNVStorable = !if (!eq(ImmOpStr, "s4_3Imm"), 0, 1);
3162 let isPredicatedNew = isPredNew;
3163 let isPredicatedFalse = isPredNot;
3165 let IClass = 0b1010;
3167 let Inst{27-25} = 0b101;
3168 let Inst{24-21} = MajOp;
3169 let Inst{20-16} = src2;
3171 let Inst{12-8} = src3;
3172 let Inst{7} = isPredNew;
3173 let Inst{6-3} = offsetBits;
3174 let Inst{2} = isPredNot;
3175 let Inst{1-0} = src1;
3178 multiclass ST_PostInc<string mnemonic, string BaseOp, RegisterClass RC,
3179 Operand ImmOp, bits<4> MajOp, bit isHalf = 0 > {
3181 let BaseOpcode = "POST_"#BaseOp in {
3182 def S2_#NAME#_pi : T_store_pi <mnemonic, RC, ImmOp, MajOp, isHalf>;
3185 def S2_p#NAME#t_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp, isHalf, 0, 0>;
3186 def S2_p#NAME#f_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp, isHalf, 1, 0>;
3189 def S2_p#NAME#tnew_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp,
3191 def S2_p#NAME#fnew_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp,
3196 let accessSize = ByteAccess in
3197 defm storerb: ST_PostInc <"memb", "STrib", IntRegs, s4_0Imm, 0b1000>;
3199 let accessSize = HalfWordAccess in
3200 defm storerh: ST_PostInc <"memh", "STrih", IntRegs, s4_1Imm, 0b1010>;
3202 let accessSize = WordAccess in
3203 defm storeri: ST_PostInc <"memw", "STriw", IntRegs, s4_2Imm, 0b1100>;
3205 let accessSize = DoubleWordAccess in
3206 defm storerd: ST_PostInc <"memd", "STrid", DoubleRegs, s4_3Imm, 0b1110>;
3208 let accessSize = HalfWordAccess, isNVStorable = 0 in
3209 defm storerf: ST_PostInc <"memh", "STrih_H", IntRegs, s4_1Imm, 0b1011, 1>;
3211 // Patterns for generating stores, where the address takes different forms:
3214 // - simple (base address without offset).
3215 // These would usually be used together (via Storex_pat defined below), but
3216 // in some cases one may want to apply different properties (such as
3217 // AddedComplexity) to the individual patterns.
3218 class Storex_fi_pat<PatFrag Store, PatFrag Value, InstHexagon MI>
3219 : Pat<(Store Value:$Rs, AddrFI:$fi), (MI AddrFI:$fi, 0, Value:$Rs)>;
3220 class Storex_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred,
3222 : Pat<(Store Value:$Rt, (add (i32 IntRegs:$Rs), ImmPred:$Off)),
3223 (MI IntRegs:$Rs, imm:$Off, Value:$Rt)>;
3225 multiclass Storex_pat<PatFrag Store, PatFrag Value, PatLeaf ImmPred,
3227 def: Storex_fi_pat <Store, Value, MI>;
3228 def: Storex_add_pat <Store, Value, ImmPred, MI>;
3231 def : Pat<(post_truncsti8 (i32 IntRegs:$src1), IntRegs:$src2,
3232 s4_3ImmPred:$offset),
3233 (S2_storerb_pi IntRegs:$src2, s4_0ImmPred:$offset, IntRegs:$src1)>;
3235 def : Pat<(post_truncsti16 (i32 IntRegs:$src1), IntRegs:$src2,
3236 s4_3ImmPred:$offset),
3237 (S2_storerh_pi IntRegs:$src2, s4_1ImmPred:$offset, IntRegs:$src1)>;
3239 def : Pat<(post_store (i32 IntRegs:$src1), IntRegs:$src2, s4_2ImmPred:$offset),
3240 (S2_storeri_pi IntRegs:$src2, s4_1ImmPred:$offset, IntRegs:$src1)>;
3242 def : Pat<(post_store (i64 DoubleRegs:$src1), IntRegs:$src2,
3243 s4_3ImmPred:$offset),
3244 (S2_storerd_pi IntRegs:$src2, s4_3ImmPred:$offset, DoubleRegs:$src1)>;
3246 //===----------------------------------------------------------------------===//
3247 // Template class for post increment stores with register offset.
3248 //===----------------------------------------------------------------------===//
3249 let isNVStorable = 1 in
3250 class T_store_pr <string mnemonic, RegisterClass RC, bits<3> MajOp,
3251 MemAccessSize AccessSz, bit isHalf = 0>
3252 : STInst <(outs IntRegs:$_dst_),
3253 (ins IntRegs:$src1, ModRegs:$src2, RC:$src3),
3254 mnemonic#"($src1++$src2) = $src3"#!if(isHalf, ".h", ""),
3255 [], "$src1 = $_dst_" > {
3259 let accessSize = AccessSz;
3261 let IClass = 0b1010;
3263 let Inst{27-24} = 0b1101;
3264 let Inst{23-21} = MajOp;
3265 let Inst{20-16} = src1;
3266 let Inst{13} = src2;
3267 let Inst{12-8} = src3;
3271 def S2_storerb_pr : T_store_pr<"memb", IntRegs, 0b000, ByteAccess>;
3272 def S2_storerh_pr : T_store_pr<"memh", IntRegs, 0b010, HalfWordAccess>;
3273 def S2_storeri_pr : T_store_pr<"memw", IntRegs, 0b100, WordAccess>;
3274 def S2_storerd_pr : T_store_pr<"memd", DoubleRegs, 0b110, DoubleWordAccess>;
3276 def S2_storerf_pr : T_store_pr<"memh", IntRegs, 0b011, HalfWordAccess, 1>;
3278 let opExtendable = 1, isExtentSigned = 1, isPredicable = 1 in
3279 class T_store_io <string mnemonic, RegisterClass RC, Operand ImmOp,
3280 bits<3>MajOp, bit isH = 0>
3282 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
3283 mnemonic#"($src1+#$src2) = $src3"#!if(isH,".h","")>,
3284 AddrModeRel, ImmRegRel {
3286 bits<14> src2; // Actual address offset
3288 bits<11> offsetBits; // Represents offset encoding
3290 string ImmOpStr = !cast<string>(ImmOp);
3292 let opExtentBits = !if (!eq(ImmOpStr, "s11_3Ext"), 14,
3293 !if (!eq(ImmOpStr, "s11_2Ext"), 13,
3294 !if (!eq(ImmOpStr, "s11_1Ext"), 12,
3295 /* s11_0Ext */ 11)));
3296 let offsetBits = !if (!eq(ImmOpStr, "s11_3Ext"), src2{13-3},
3297 !if (!eq(ImmOpStr, "s11_2Ext"), src2{12-2},
3298 !if (!eq(ImmOpStr, "s11_1Ext"), src2{11-1},
3299 /* s11_0Ext */ src2{10-0})));
3300 let IClass = 0b1010;
3303 let Inst{26-25} = offsetBits{10-9};
3305 let Inst{23-21} = MajOp;
3306 let Inst{20-16} = src1;
3307 let Inst{13} = offsetBits{8};
3308 let Inst{12-8} = src3;
3309 let Inst{7-0} = offsetBits{7-0};
3312 let opExtendable = 2, isPredicated = 1 in
3313 class T_pstore_io <string mnemonic, RegisterClass RC, Operand ImmOp,
3314 bits<3>MajOp, bit PredNot, bit isPredNew, bit isH = 0>
3316 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4),
3317 !if(PredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
3318 ") ")#mnemonic#"($src2+#$src3) = $src4"#!if(isH,".h",""),
3319 [],"",V2LDST_tc_st_SLOT01 >,
3320 AddrModeRel, ImmRegRel {
3323 bits<9> src3; // Actual address offset
3325 bits<6> offsetBits; // Represents offset encoding
3327 let isPredicatedNew = isPredNew;
3328 let isPredicatedFalse = PredNot;
3330 string ImmOpStr = !cast<string>(ImmOp);
3331 let opExtentBits = !if (!eq(ImmOpStr, "u6_3Ext"), 9,
3332 !if (!eq(ImmOpStr, "u6_2Ext"), 8,
3333 !if (!eq(ImmOpStr, "u6_1Ext"), 7,
3335 let offsetBits = !if (!eq(ImmOpStr, "u6_3Ext"), src3{8-3},
3336 !if (!eq(ImmOpStr, "u6_2Ext"), src3{7-2},
3337 !if (!eq(ImmOpStr, "u6_1Ext"), src3{6-1},
3338 /* u6_0Ext */ src3{5-0})));
3339 let IClass = 0b0100;
3342 let Inst{26} = PredNot;
3343 let Inst{25} = isPredNew;
3345 let Inst{23-21} = MajOp;
3346 let Inst{20-16} = src2;
3347 let Inst{13} = offsetBits{5};
3348 let Inst{12-8} = src4;
3349 let Inst{7-3} = offsetBits{4-0};
3350 let Inst{1-0} = src1;
3353 let isExtendable = 1, isNVStorable = 1, hasSideEffects = 0 in
3354 multiclass ST_Idxd<string mnemonic, string CextOp, RegisterClass RC,
3355 Operand ImmOp, Operand predImmOp, bits<3> MajOp, bit isH = 0> {
3356 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
3357 def S2_#NAME#_io : T_store_io <mnemonic, RC, ImmOp, MajOp, isH>;
3360 def S2_p#NAME#t_io : T_pstore_io<mnemonic, RC, predImmOp, MajOp, 0, 0, isH>;
3361 def S2_p#NAME#f_io : T_pstore_io<mnemonic, RC, predImmOp, MajOp, 1, 0, isH>;
3364 def S4_p#NAME#tnew_io : T_pstore_io <mnemonic, RC, predImmOp,
3366 def S4_p#NAME#fnew_io : T_pstore_io <mnemonic, RC, predImmOp,
3371 let addrMode = BaseImmOffset, InputType = "imm" in {
3372 let accessSize = ByteAccess in
3373 defm storerb: ST_Idxd < "memb", "STrib", IntRegs, s11_0Ext, u6_0Ext, 0b000>;
3375 let accessSize = HalfWordAccess, opExtentAlign = 1 in
3376 defm storerh: ST_Idxd < "memh", "STrih", IntRegs, s11_1Ext, u6_1Ext, 0b010>;
3378 let accessSize = WordAccess, opExtentAlign = 2 in
3379 defm storeri: ST_Idxd < "memw", "STriw", IntRegs, s11_2Ext, u6_2Ext, 0b100>;
3381 let accessSize = DoubleWordAccess, isNVStorable = 0, opExtentAlign = 3 in
3382 defm storerd: ST_Idxd < "memd", "STrid", DoubleRegs, s11_3Ext,
3385 let accessSize = HalfWordAccess, opExtentAlign = 1 in
3386 defm storerf: ST_Idxd < "memh", "STrif", IntRegs, s11_1Ext,
3390 class Storex_simple_pat<PatFrag Store, PatFrag Value, InstHexagon MI>
3391 : Pat<(Store Value:$Rt, (i32 IntRegs:$Rs)),
3392 (MI IntRegs:$Rs, 0, Value:$Rt)>;
3394 // Regular stores in the DAG have two operands: value and address.
3395 // Atomic stores also have two, but they are reversed: address, value.
3396 // To use atomic stores with the patterns, they need to have their operands
3397 // swapped. This relies on the knowledge that the F.Fragment uses names
3399 class SwapSt<PatFrag F>
3400 : PatFrag<(ops node:$val, node:$ptr), F.Fragment>;
3402 def: Storex_simple_pat<SwapSt<atomic_store_8>, I32, S2_storerb_io>;
3403 def: Storex_simple_pat<SwapSt<atomic_store_16>, I32, S2_storerh_io>;
3404 def: Storex_simple_pat<SwapSt<atomic_store_32>, I32, S2_storeri_io>;
3405 def: Storex_simple_pat<SwapSt<atomic_store_64>, I64, S2_storerd_io>;
3407 def : Pat<(truncstorei8 (i32 IntRegs:$src1), ADDRriS11_0:$addr),
3408 (S2_storerb_io AddrFI:$addr, 0, (i32 IntRegs:$src1))>;
3410 def : Pat<(truncstorei16 (i32 IntRegs:$src1), ADDRriS11_1:$addr),
3411 (S2_storerh_io AddrFI:$addr, 0, (i32 IntRegs:$src1))>;
3413 def : Pat<(store (i32 IntRegs:$src1), ADDRriS11_2:$addr),
3414 (S2_storeri_io AddrFI:$addr, 0, (i32 IntRegs:$src1))>;
3416 def : Pat<(store (i64 DoubleRegs:$src1), ADDRriS11_3:$addr),
3417 (S2_storerd_io AddrFI:$addr, 0, (i64 DoubleRegs:$src1))>;
3420 let AddedComplexity = 10 in {
3421 def : Pat<(truncstorei8 (i32 IntRegs:$src1), (add IntRegs:$src2,
3422 s11_0ExtPred:$offset)),
3423 (S2_storerb_io IntRegs:$src2, s11_0ImmPred:$offset,
3424 (i32 IntRegs:$src1))>;
3426 def : Pat<(truncstorei16 (i32 IntRegs:$src1), (add IntRegs:$src2,
3427 s11_1ExtPred:$offset)),
3428 (S2_storerh_io IntRegs:$src2, s11_1ImmPred:$offset,
3429 (i32 IntRegs:$src1))>;
3431 def : Pat<(store (i32 IntRegs:$src1), (add IntRegs:$src2,
3432 s11_2ExtPred:$offset)),
3433 (S2_storeri_io IntRegs:$src2, s11_2ImmPred:$offset,
3434 (i32 IntRegs:$src1))>;
3436 def : Pat<(store (i64 DoubleRegs:$src1), (add IntRegs:$src2,
3437 s11_3ExtPred:$offset)),
3438 (S2_storerd_io IntRegs:$src2, s11_3ImmPred:$offset,
3439 (i64 DoubleRegs:$src1))>;
3442 // memh(Rx++#s4:1)=Rt.H
3445 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 13,
3446 isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in
3447 def STriw_pred : STInst<(outs),
3448 (ins IntRegs:$addr, s11_2Ext:$off, PredRegs:$src1),
3449 ".error \"should not emit\"", []>;
3451 // S2_allocframe: Allocate stack frame.
3452 let Defs = [R29, R30], Uses = [R29, R31, R30],
3453 hasSideEffects = 0, accessSize = DoubleWordAccess in
3454 def S2_allocframe: ST0Inst <
3455 (outs), (ins u11_3Imm:$u11_3),
3456 "allocframe(#$u11_3)" > {
3459 let IClass = 0b1010;
3460 let Inst{27-16} = 0b000010011101;
3461 let Inst{13-11} = 0b000;
3462 let Inst{10-0} = u11_3{13-3};
3465 // S2_storer[bhwdf]_pci: Store byte/half/word/double.
3466 // S2_storer[bhwdf]_pci -> S2_storerbnew_pci
3467 let Uses = [CS], isNVStorable = 1 in
3468 class T_store_pci <string mnemonic, RegisterClass RC,
3469 Operand Imm, bits<4>MajOp,
3470 MemAccessSize AlignSize, string RegSrc = "Rt">
3471 : STInst <(outs IntRegs:$_dst_),
3472 (ins IntRegs:$Rz, Imm:$offset, ModRegs:$Mu, RC:$Rt),
3473 #mnemonic#"($Rz ++ #$offset:circ($Mu)) = $"#RegSrc#"",
3480 let accessSize = AlignSize;
3482 let IClass = 0b1010;
3483 let Inst{27-25} = 0b100;
3484 let Inst{24-21} = MajOp;
3485 let Inst{20-16} = Rz;
3487 let Inst{12-8} = Rt;
3490 !if (!eq(!cast<string>(AlignSize), "DoubleWordAccess"), offset{6-3},
3491 !if (!eq(!cast<string>(AlignSize), "WordAccess"), offset{5-2},
3492 !if (!eq(!cast<string>(AlignSize), "HalfWordAccess"), offset{4-1},
3493 /* ByteAccess */ offset{3-0})));
3497 def S2_storerb_pci : T_store_pci<"memb", IntRegs, s4_0Imm, 0b1000,
3499 def S2_storerh_pci : T_store_pci<"memh", IntRegs, s4_1Imm, 0b1010,
3501 def S2_storerf_pci : T_store_pci<"memh", IntRegs, s4_1Imm, 0b1011,
3502 HalfWordAccess, "Rt.h">;
3503 def S2_storeri_pci : T_store_pci<"memw", IntRegs, s4_2Imm, 0b1100,
3505 def S2_storerd_pci : T_store_pci<"memd", DoubleRegs, s4_3Imm, 0b1110,
3508 let Uses = [CS], isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 4 in
3509 class T_storenew_pci <string mnemonic, Operand Imm,
3510 bits<2>MajOp, MemAccessSize AlignSize>
3511 : NVInst < (outs IntRegs:$_dst_),
3512 (ins IntRegs:$Rz, Imm:$offset, ModRegs:$Mu, IntRegs:$Nt),
3513 #mnemonic#"($Rz ++ #$offset:circ($Mu)) = $Nt.new",
3521 let accessSize = AlignSize;
3523 let IClass = 0b1010;
3524 let Inst{27-21} = 0b1001101;
3525 let Inst{20-16} = Rz;
3527 let Inst{12-11} = MajOp;
3528 let Inst{10-8} = Nt;
3531 !if (!eq(!cast<string>(AlignSize), "WordAccess"), offset{5-2},
3532 !if (!eq(!cast<string>(AlignSize), "HalfWordAccess"), offset{4-1},
3533 /* ByteAccess */ offset{3-0}));
3537 def S2_storerbnew_pci : T_storenew_pci <"memb", s4_0Imm, 0b00, ByteAccess>;
3538 def S2_storerhnew_pci : T_storenew_pci <"memh", s4_1Imm, 0b01, HalfWordAccess>;
3539 def S2_storerinew_pci : T_storenew_pci <"memw", s4_2Imm, 0b10, WordAccess>;
3541 //===----------------------------------------------------------------------===//
3542 // Circular stores with auto-increment register
3543 //===----------------------------------------------------------------------===//
3544 let Uses = [CS], isNVStorable = 1 in
3545 class T_store_pcr <string mnemonic, RegisterClass RC, bits<4>MajOp,
3546 MemAccessSize AlignSize, string RegSrc = "Rt">
3547 : STInst <(outs IntRegs:$_dst_),
3548 (ins IntRegs:$Rz, ModRegs:$Mu, RC:$Rt),
3549 #mnemonic#"($Rz ++ I:circ($Mu)) = $"#RegSrc#"",
3556 let accessSize = AlignSize;
3558 let IClass = 0b1010;
3559 let Inst{27-25} = 0b100;
3560 let Inst{24-21} = MajOp;
3561 let Inst{20-16} = Rz;
3563 let Inst{12-8} = Rt;
3568 def S2_storerb_pcr : T_store_pcr<"memb", IntRegs, 0b1000, ByteAccess>;
3569 def S2_storerh_pcr : T_store_pcr<"memh", IntRegs, 0b1010, HalfWordAccess>;
3570 def S2_storeri_pcr : T_store_pcr<"memw", IntRegs, 0b1100, WordAccess>;
3571 def S2_storerd_pcr : T_store_pcr<"memd", DoubleRegs, 0b1110, DoubleWordAccess>;
3572 def S2_storerf_pcr : T_store_pcr<"memh", IntRegs, 0b1011,
3573 HalfWordAccess, "Rt.h">;
3575 //===----------------------------------------------------------------------===//
3576 // Circular .new stores with auto-increment register
3577 //===----------------------------------------------------------------------===//
3578 let Uses = [CS], isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 3 in
3579 class T_storenew_pcr <string mnemonic, bits<2>MajOp,
3580 MemAccessSize AlignSize>
3581 : NVInst <(outs IntRegs:$_dst_),
3582 (ins IntRegs:$Rz, ModRegs:$Mu, IntRegs:$Nt),
3583 #mnemonic#"($Rz ++ I:circ($Mu)) = $Nt.new" ,
3590 let accessSize = AlignSize;
3592 let IClass = 0b1010;
3593 let Inst{27-21} = 0b1001101;
3594 let Inst{20-16} = Rz;
3596 let Inst{12-11} = MajOp;
3597 let Inst{10-8} = Nt;
3602 def S2_storerbnew_pcr : T_storenew_pcr <"memb", 0b00, ByteAccess>;
3603 def S2_storerhnew_pcr : T_storenew_pcr <"memh", 0b01, HalfWordAccess>;
3604 def S2_storerinew_pcr : T_storenew_pcr <"memw", 0b10, WordAccess>;
3606 //===----------------------------------------------------------------------===//
3607 // Bit-reversed stores with auto-increment register
3608 //===----------------------------------------------------------------------===//
3609 let hasSideEffects = 0 in
3610 class T_store_pbr<string mnemonic, RegisterClass RC,
3611 MemAccessSize addrSize, bits<3> majOp,
3614 <(outs IntRegs:$_dst_),
3615 (ins IntRegs:$Rz, ModRegs:$Mu, RC:$src),
3616 #mnemonic#"($Rz ++ $Mu:brev) = $src"#!if (!eq(isHalf, 1), ".h", ""),
3617 [], "$Rz = $_dst_" > {
3619 let accessSize = addrSize;
3625 let IClass = 0b1010;
3627 let Inst{27-24} = 0b1111;
3628 let Inst{23-21} = majOp;
3630 let Inst{20-16} = Rz;
3632 let Inst{12-8} = src;
3635 let isNVStorable = 1 in {
3636 let BaseOpcode = "S2_storerb_pbr" in
3637 def S2_storerb_pbr : T_store_pbr<"memb", IntRegs, ByteAccess,
3638 0b000>, NewValueRel;
3639 let BaseOpcode = "S2_storerh_pbr" in
3640 def S2_storerh_pbr : T_store_pbr<"memh", IntRegs, HalfWordAccess,
3641 0b010>, NewValueRel;
3642 let BaseOpcode = "S2_storeri_pbr" in
3643 def S2_storeri_pbr : T_store_pbr<"memw", IntRegs, WordAccess,
3644 0b100>, NewValueRel;
3647 def S2_storerf_pbr : T_store_pbr<"memh", IntRegs, HalfWordAccess, 0b011, 1>;
3648 def S2_storerd_pbr : T_store_pbr<"memd", DoubleRegs, DoubleWordAccess, 0b110>;
3650 //===----------------------------------------------------------------------===//
3651 // Bit-reversed .new stores with auto-increment register
3652 //===----------------------------------------------------------------------===//
3653 let isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 3,
3654 hasSideEffects = 0 in
3655 class T_storenew_pbr<string mnemonic, MemAccessSize addrSize, bits<2> majOp>
3656 : NVInst <(outs IntRegs:$_dst_),
3657 (ins IntRegs:$Rz, ModRegs:$Mu, IntRegs:$Nt),
3658 #mnemonic#"($Rz ++ $Mu:brev) = $Nt.new", [],
3659 "$Rz = $_dst_">, NewValueRel {
3660 let accessSize = addrSize;
3665 let IClass = 0b1010;
3667 let Inst{27-21} = 0b1111101;
3668 let Inst{12-11} = majOp;
3670 let Inst{20-16} = Rz;
3672 let Inst{10-8} = Nt;
3675 let BaseOpcode = "S2_storerb_pbr" in
3676 def S2_storerbnew_pbr : T_storenew_pbr<"memb", ByteAccess, 0b00>;
3678 let BaseOpcode = "S2_storerh_pbr" in
3679 def S2_storerhnew_pbr : T_storenew_pbr<"memh", HalfWordAccess, 0b01>;
3681 let BaseOpcode = "S2_storeri_pbr" in
3682 def S2_storerinew_pbr : T_storenew_pbr<"memw", WordAccess, 0b10>;
3684 //===----------------------------------------------------------------------===//
3686 //===----------------------------------------------------------------------===//
3688 let hasSideEffects = 0 in
3689 class T_S2op_1 <string mnemonic, bits<4> RegTyBits, RegisterClass RCOut,
3690 RegisterClass RCIn, bits<2> MajOp, bits<3> MinOp, bit isSat>
3691 : SInst <(outs RCOut:$dst), (ins RCIn:$src),
3692 "$dst = "#mnemonic#"($src)"#!if(isSat, ":sat", ""),
3693 [], "", S_2op_tc_1_SLOT23 > {
3697 let IClass = 0b1000;
3699 let Inst{27-24} = RegTyBits;
3700 let Inst{23-22} = MajOp;
3702 let Inst{20-16} = src;
3703 let Inst{7-5} = MinOp;
3704 let Inst{4-0} = dst;
3707 class T_S2op_1_di <string mnemonic, bits<2> MajOp, bits<3> MinOp>
3708 : T_S2op_1 <mnemonic, 0b0100, DoubleRegs, IntRegs, MajOp, MinOp, 0>;
3710 let hasNewValue = 1 in
3711 class T_S2op_1_id <string mnemonic, bits<2> MajOp, bits<3> MinOp, bit isSat = 0>
3712 : T_S2op_1 <mnemonic, 0b1000, IntRegs, DoubleRegs, MajOp, MinOp, isSat>;
3714 let hasNewValue = 1 in
3715 class T_S2op_1_ii <string mnemonic, bits<2> MajOp, bits<3> MinOp, bit isSat = 0>
3716 : T_S2op_1 <mnemonic, 0b1100, IntRegs, IntRegs, MajOp, MinOp, isSat>;
3718 // Vector sign/zero extend
3719 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
3720 def S2_vsxtbh : T_S2op_1_di <"vsxtbh", 0b00, 0b000>;
3721 def S2_vsxthw : T_S2op_1_di <"vsxthw", 0b00, 0b100>;
3722 def S2_vzxtbh : T_S2op_1_di <"vzxtbh", 0b00, 0b010>;
3723 def S2_vzxthw : T_S2op_1_di <"vzxthw", 0b00, 0b110>;
3726 // Vector splat bytes/halfwords
3727 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
3728 def S2_vsplatrb : T_S2op_1_ii <"vsplatb", 0b01, 0b111>;
3729 def S2_vsplatrh : T_S2op_1_di <"vsplath", 0b01, 0b010>;
3732 // Sign extend word to doubleword
3733 def A2_sxtw : T_S2op_1_di <"sxtw", 0b01, 0b000>;
3735 def: Pat <(i64 (sext I32:$src)), (A2_sxtw I32:$src)>;
3737 // Vector saturate and pack
3738 let Defs = [USR_OVF] in {
3739 def S2_svsathb : T_S2op_1_ii <"vsathb", 0b10, 0b000>;
3740 def S2_svsathub : T_S2op_1_ii <"vsathub", 0b10, 0b010>;
3741 def S2_vsathb : T_S2op_1_id <"vsathb", 0b00, 0b110>;
3742 def S2_vsathub : T_S2op_1_id <"vsathub", 0b00, 0b000>;
3743 def S2_vsatwh : T_S2op_1_id <"vsatwh", 0b00, 0b010>;
3744 def S2_vsatwuh : T_S2op_1_id <"vsatwuh", 0b00, 0b100>;
3748 def S2_vtrunohb : T_S2op_1_id <"vtrunohb", 0b10, 0b000>;
3749 def S2_vtrunehb : T_S2op_1_id <"vtrunehb", 0b10, 0b010>;
3751 // Swizzle the bytes of a word
3752 def A2_swiz : T_S2op_1_ii <"swiz", 0b10, 0b111>;
3755 let Defs = [USR_OVF] in {
3756 def A2_sat : T_S2op_1_id <"sat", 0b11, 0b000>;
3757 def A2_satb : T_S2op_1_ii <"satb", 0b11, 0b111>;
3758 def A2_satub : T_S2op_1_ii <"satub", 0b11, 0b110>;
3759 def A2_sath : T_S2op_1_ii <"sath", 0b11, 0b100>;
3760 def A2_satuh : T_S2op_1_ii <"satuh", 0b11, 0b101>;
3761 def A2_roundsat : T_S2op_1_id <"round", 0b11, 0b001, 0b1>;
3764 let Itinerary = S_2op_tc_2_SLOT23 in {
3765 // Vector round and pack
3766 def S2_vrndpackwh : T_S2op_1_id <"vrndwh", 0b10, 0b100>;
3768 let Defs = [USR_OVF] in
3769 def S2_vrndpackwhs : T_S2op_1_id <"vrndwh", 0b10, 0b110, 1>;
3772 def S2_brev : T_S2op_1_ii <"brev", 0b01, 0b110>;
3774 // Absolute value word
3775 def A2_abs : T_S2op_1_ii <"abs", 0b10, 0b100>;
3777 let Defs = [USR_OVF] in
3778 def A2_abssat : T_S2op_1_ii <"abs", 0b10, 0b101, 1>;
3780 // Negate with saturation
3781 let Defs = [USR_OVF] in
3782 def A2_negsat : T_S2op_1_ii <"neg", 0b10, 0b110, 1>;
3785 def: Pat<(i32 (select (i1 (setlt (i32 IntRegs:$src), 0)),
3786 (i32 (sub 0, (i32 IntRegs:$src))),
3787 (i32 IntRegs:$src))),
3788 (A2_abs IntRegs:$src)>;
3790 let AddedComplexity = 50 in
3791 def: Pat<(i32 (xor (add (sra (i32 IntRegs:$src), (i32 31)),
3792 (i32 IntRegs:$src)),
3793 (sra (i32 IntRegs:$src), (i32 31)))),
3794 (A2_abs IntRegs:$src)>;
3796 class T_S2op_2 <string mnemonic, bits<4> RegTyBits, RegisterClass RCOut,
3797 RegisterClass RCIn, bits<3> MajOp, bits<3> MinOp,
3798 bit isSat, bit isRnd, list<dag> pattern = []>
3799 : SInst <(outs RCOut:$dst),
3800 (ins RCIn:$src, u5Imm:$u5),
3801 "$dst = "#mnemonic#"($src, #$u5)"#!if(isSat, ":sat", "")
3802 #!if(isRnd, ":rnd", ""),
3803 pattern, "", S_2op_tc_2_SLOT23> {
3808 let IClass = 0b1000;
3810 let Inst{27-24} = RegTyBits;
3811 let Inst{23-21} = MajOp;
3812 let Inst{20-16} = src;
3814 let Inst{12-8} = u5;
3815 let Inst{7-5} = MinOp;
3816 let Inst{4-0} = dst;
3819 class T_S2op_2_di <string mnemonic, bits<3> MajOp, bits<3> MinOp>
3820 : T_S2op_2 <mnemonic, 0b1000, DoubleRegs, IntRegs, MajOp, MinOp, 0, 0>;
3822 let hasNewValue = 1 in
3823 class T_S2op_2_id <string mnemonic, bits<3> MajOp, bits<3> MinOp>
3824 : T_S2op_2 <mnemonic, 0b1000, IntRegs, DoubleRegs, MajOp, MinOp, 0, 0>;
3826 let hasNewValue = 1 in
3827 class T_S2op_2_ii <string mnemonic, bits<3> MajOp, bits<3> MinOp,
3828 bit isSat = 0, bit isRnd = 0, list<dag> pattern = []>
3829 : T_S2op_2 <mnemonic, 0b1100, IntRegs, IntRegs, MajOp, MinOp,
3830 isSat, isRnd, pattern>;
3832 class T_S2op_shift <string mnemonic, bits<3> MajOp, bits<3> MinOp, SDNode OpNd>
3833 : T_S2op_2_ii <mnemonic, MajOp, MinOp, 0, 0,
3834 [(set (i32 IntRegs:$dst), (OpNd (i32 IntRegs:$src),
3835 (u5ImmPred:$u5)))]>;
3837 // Vector arithmetic shift right by immediate with truncate and pack
3838 def S2_asr_i_svw_trun : T_S2op_2_id <"vasrw", 0b110, 0b010>;
3840 // Arithmetic/logical shift right/left by immediate
3841 let Itinerary = S_2op_tc_1_SLOT23 in {
3842 def S2_asr_i_r : T_S2op_shift <"asr", 0b000, 0b000, sra>;
3843 def S2_lsr_i_r : T_S2op_shift <"lsr", 0b000, 0b001, srl>;
3844 def S2_asl_i_r : T_S2op_shift <"asl", 0b000, 0b010, shl>;
3847 // Shift left by immediate with saturation
3848 let Defs = [USR_OVF] in
3849 def S2_asl_i_r_sat : T_S2op_2_ii <"asl", 0b010, 0b010, 1>;
3851 // Shift right with round
3852 def S2_asr_i_r_rnd : T_S2op_2_ii <"asr", 0b010, 0b000, 0, 1>;
3854 let isAsmParserOnly = 1 in
3855 def S2_asr_i_r_rnd_goodsyntax
3856 : SInst <(outs IntRegs:$dst), (ins IntRegs:$src, u5Imm:$u5),
3857 "$dst = asrrnd($src, #$u5)",
3858 [], "", S_2op_tc_1_SLOT23>;
3860 def: Pat<(i32 (sra (i32 (add (i32 (sra I32:$src1, u5ImmPred:$src2)),
3863 (S2_asr_i_r_rnd IntRegs:$src1, u5ImmPred:$src2)>;
3865 class T_S2op_3<string opc, bits<2>MajOp, bits<3>minOp, bits<1> sat = 0>
3866 : SInst<(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss),
3867 "$Rdd = "#opc#"($Rss)"#!if(!eq(sat, 1),":sat","")> {
3870 let IClass = 0b1000;
3871 let Inst{27-24} = 0;
3872 let Inst{23-22} = MajOp;
3873 let Inst{20-16} = Rss;
3874 let Inst{7-5} = minOp;
3875 let Inst{4-0} = Rdd;
3878 def A2_absp : T_S2op_3 <"abs", 0b10, 0b110>;
3879 def A2_negp : T_S2op_3 <"neg", 0b10, 0b101>;
3880 def A2_notp : T_S2op_3 <"not", 0b10, 0b100>;
3882 // Innterleave/deinterleave
3883 def S2_interleave : T_S2op_3 <"interleave", 0b11, 0b101>;
3884 def S2_deinterleave : T_S2op_3 <"deinterleave", 0b11, 0b100>;
3886 // Vector Complex conjugate
3887 def A2_vconj : T_S2op_3 <"vconj", 0b10, 0b111, 1>;
3889 // Vector saturate without pack
3890 def S2_vsathb_nopack : T_S2op_3 <"vsathb", 0b00, 0b111>;
3891 def S2_vsathub_nopack : T_S2op_3 <"vsathub", 0b00, 0b100>;
3892 def S2_vsatwh_nopack : T_S2op_3 <"vsatwh", 0b00, 0b110>;
3893 def S2_vsatwuh_nopack : T_S2op_3 <"vsatwuh", 0b00, 0b101>;
3895 // Vector absolute value halfwords with and without saturation
3896 // Rdd64=vabsh(Rss64)[:sat]
3897 def A2_vabsh : T_S2op_3 <"vabsh", 0b01, 0b100>;
3898 def A2_vabshsat : T_S2op_3 <"vabsh", 0b01, 0b101, 1>;
3900 // Vector absolute value words with and without saturation
3901 def A2_vabsw : T_S2op_3 <"vabsw", 0b01, 0b110>;
3902 def A2_vabswsat : T_S2op_3 <"vabsw", 0b01, 0b111, 1>;
3904 //===----------------------------------------------------------------------===//
3906 //===----------------------------------------------------------------------===//
3909 let hasSideEffects = 0, hasNewValue = 1 in
3910 class T_COUNT_LEADING<string MnOp, bits<3> MajOp, bits<3> MinOp, bit Is32,
3912 : SInst<Out, Inp, "$Rd = "#MnOp#"($Rs)", [], "", S_2op_tc_1_SLOT23> {
3915 let IClass = 0b1000;
3917 let Inst{26} = Is32;
3918 let Inst{25-24} = 0b00;
3919 let Inst{23-21} = MajOp;
3920 let Inst{20-16} = Rs;
3921 let Inst{7-5} = MinOp;
3925 class T_COUNT_LEADING_32<string MnOp, bits<3> MajOp, bits<3> MinOp>
3926 : T_COUNT_LEADING<MnOp, MajOp, MinOp, 0b1,
3927 (outs IntRegs:$Rd), (ins IntRegs:$Rs)>;
3929 class T_COUNT_LEADING_64<string MnOp, bits<3> MajOp, bits<3> MinOp>
3930 : T_COUNT_LEADING<MnOp, MajOp, MinOp, 0b0,
3931 (outs IntRegs:$Rd), (ins DoubleRegs:$Rs)>;
3933 def S2_cl0 : T_COUNT_LEADING_32<"cl0", 0b000, 0b101>;
3934 def S2_cl1 : T_COUNT_LEADING_32<"cl1", 0b000, 0b110>;
3935 def S2_ct0 : T_COUNT_LEADING_32<"ct0", 0b010, 0b100>;
3936 def S2_ct1 : T_COUNT_LEADING_32<"ct1", 0b010, 0b101>;
3937 def S2_cl0p : T_COUNT_LEADING_64<"cl0", 0b010, 0b010>;
3938 def S2_cl1p : T_COUNT_LEADING_64<"cl1", 0b010, 0b100>;
3939 def S2_clb : T_COUNT_LEADING_32<"clb", 0b000, 0b100>;
3940 def S2_clbp : T_COUNT_LEADING_64<"clb", 0b010, 0b000>;
3941 def S2_clbnorm : T_COUNT_LEADING_32<"normamt", 0b000, 0b111>;
3943 def: Pat<(i32 (ctlz I32:$Rs)), (S2_cl0 I32:$Rs)>;
3944 def: Pat<(i32 (ctlz (not I32:$Rs))), (S2_cl1 I32:$Rs)>;
3945 def: Pat<(i32 (cttz I32:$Rs)), (S2_ct0 I32:$Rs)>;
3946 def: Pat<(i32 (cttz (not I32:$Rs))), (S2_ct1 I32:$Rs)>;
3947 def: Pat<(i32 (trunc (ctlz I64:$Rss))), (S2_cl0p I64:$Rss)>;
3948 def: Pat<(i32 (trunc (ctlz (not I64:$Rss)))), (S2_cl1p I64:$Rss)>;
3950 // Bit set/clear/toggle
3952 let hasSideEffects = 0, hasNewValue = 1 in
3953 class T_SCT_BIT_IMM<string MnOp, bits<3> MinOp>
3954 : SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, u5Imm:$u5),
3955 "$Rd = "#MnOp#"($Rs, #$u5)", [], "", S_2op_tc_1_SLOT23> {
3959 let IClass = 0b1000;
3960 let Inst{27-21} = 0b1100110;
3961 let Inst{20-16} = Rs;
3963 let Inst{12-8} = u5;
3964 let Inst{7-5} = MinOp;
3968 let hasSideEffects = 0, hasNewValue = 1 in
3969 class T_SCT_BIT_REG<string MnOp, bits<2> MinOp>
3970 : SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
3971 "$Rd = "#MnOp#"($Rs, $Rt)", [], "", S_3op_tc_1_SLOT23> {
3975 let IClass = 0b1100;
3976 let Inst{27-22} = 0b011010;
3977 let Inst{20-16} = Rs;
3978 let Inst{12-8} = Rt;
3979 let Inst{7-6} = MinOp;
3983 def S2_clrbit_i : T_SCT_BIT_IMM<"clrbit", 0b001>;
3984 def S2_setbit_i : T_SCT_BIT_IMM<"setbit", 0b000>;
3985 def S2_togglebit_i : T_SCT_BIT_IMM<"togglebit", 0b010>;
3986 def S2_clrbit_r : T_SCT_BIT_REG<"clrbit", 0b01>;
3987 def S2_setbit_r : T_SCT_BIT_REG<"setbit", 0b00>;
3988 def S2_togglebit_r : T_SCT_BIT_REG<"togglebit", 0b10>;
3990 def: Pat<(i32 (and (i32 IntRegs:$Rs), (not (shl 1, u5ImmPred:$u5)))),
3991 (S2_clrbit_i IntRegs:$Rs, u5ImmPred:$u5)>;
3992 def: Pat<(i32 (or (i32 IntRegs:$Rs), (shl 1, u5ImmPred:$u5))),
3993 (S2_setbit_i IntRegs:$Rs, u5ImmPred:$u5)>;
3994 def: Pat<(i32 (xor (i32 IntRegs:$Rs), (shl 1, u5ImmPred:$u5))),
3995 (S2_togglebit_i IntRegs:$Rs, u5ImmPred:$u5)>;
3996 def: Pat<(i32 (and (i32 IntRegs:$Rs), (not (shl 1, (i32 IntRegs:$Rt))))),
3997 (S2_clrbit_r IntRegs:$Rs, IntRegs:$Rt)>;
3998 def: Pat<(i32 (or (i32 IntRegs:$Rs), (shl 1, (i32 IntRegs:$Rt)))),
3999 (S2_setbit_r IntRegs:$Rs, IntRegs:$Rt)>;
4000 def: Pat<(i32 (xor (i32 IntRegs:$Rs), (shl 1, (i32 IntRegs:$Rt)))),
4001 (S2_togglebit_r IntRegs:$Rs, IntRegs:$Rt)>;
4005 let hasSideEffects = 0 in
4006 class T_TEST_BIT_IMM<string MnOp, bits<3> MajOp>
4007 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, u5Imm:$u5),
4008 "$Pd = "#MnOp#"($Rs, #$u5)",
4009 [], "", S_2op_tc_2early_SLOT23> {
4013 let IClass = 0b1000;
4014 let Inst{27-24} = 0b0101;
4015 let Inst{23-21} = MajOp;
4016 let Inst{20-16} = Rs;
4018 let Inst{12-8} = u5;
4022 let hasSideEffects = 0 in
4023 class T_TEST_BIT_REG<string MnOp, bit IsNeg>
4024 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
4025 "$Pd = "#MnOp#"($Rs, $Rt)",
4026 [], "", S_3op_tc_2early_SLOT23> {
4030 let IClass = 0b1100;
4031 let Inst{27-22} = 0b011100;
4032 let Inst{21} = IsNeg;
4033 let Inst{20-16} = Rs;
4034 let Inst{12-8} = Rt;
4038 def S2_tstbit_i : T_TEST_BIT_IMM<"tstbit", 0b000>;
4039 def S2_tstbit_r : T_TEST_BIT_REG<"tstbit", 0>;
4041 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm.
4042 def: Pat<(i1 (setne (and (shl 1, u5ImmPred:$u5), (i32 IntRegs:$Rs)), 0)),
4043 (S2_tstbit_i IntRegs:$Rs, u5ImmPred:$u5)>;
4044 def: Pat<(i1 (setne (and (shl 1, (i32 IntRegs:$Rt)), (i32 IntRegs:$Rs)), 0)),
4045 (S2_tstbit_r IntRegs:$Rs, IntRegs:$Rt)>;
4046 def: Pat<(i1 (trunc (i32 IntRegs:$Rs))),
4047 (S2_tstbit_i IntRegs:$Rs, 0)>;
4048 def: Pat<(i1 (trunc (i64 DoubleRegs:$Rs))),
4049 (S2_tstbit_i (LoReg DoubleRegs:$Rs), 0)>;
4051 let hasSideEffects = 0 in
4052 class T_TEST_BITS_IMM<string MnOp, bits<2> MajOp, bit IsNeg>
4053 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, u6Imm:$u6),
4054 "$Pd = "#MnOp#"($Rs, #$u6)",
4055 [], "", S_2op_tc_2early_SLOT23> {
4059 let IClass = 0b1000;
4060 let Inst{27-24} = 0b0101;
4061 let Inst{23-22} = MajOp;
4062 let Inst{21} = IsNeg;
4063 let Inst{20-16} = Rs;
4064 let Inst{13-8} = u6;
4068 let hasSideEffects = 0 in
4069 class T_TEST_BITS_REG<string MnOp, bits<2> MajOp, bit IsNeg>
4070 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
4071 "$Pd = "#MnOp#"($Rs, $Rt)",
4072 [], "", S_3op_tc_2early_SLOT23> {
4076 let IClass = 0b1100;
4077 let Inst{27-24} = 0b0111;
4078 let Inst{23-22} = MajOp;
4079 let Inst{21} = IsNeg;
4080 let Inst{20-16} = Rs;
4081 let Inst{12-8} = Rt;
4085 def C2_bitsclri : T_TEST_BITS_IMM<"bitsclr", 0b10, 0>;
4086 def C2_bitsclr : T_TEST_BITS_REG<"bitsclr", 0b10, 0>;
4087 def C2_bitsset : T_TEST_BITS_REG<"bitsset", 0b01, 0>;
4089 let AddedComplexity = 20 in { // Complexity greater than compare reg-imm.
4090 def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), u6ImmPred:$u6), 0)),
4091 (C2_bitsclri IntRegs:$Rs, u6ImmPred:$u6)>;
4092 def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)), 0)),
4093 (C2_bitsclr IntRegs:$Rs, IntRegs:$Rt)>;
4096 let AddedComplexity = 10 in // Complexity greater than compare reg-reg.
4097 def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)), IntRegs:$Rt)),
4098 (C2_bitsset IntRegs:$Rs, IntRegs:$Rt)>;
4100 //===----------------------------------------------------------------------===//
4102 //===----------------------------------------------------------------------===//
4104 //===----------------------------------------------------------------------===//
4106 //===----------------------------------------------------------------------===//
4107 //===----------------------------------------------------------------------===//
4109 //===----------------------------------------------------------------------===//
4111 //===----------------------------------------------------------------------===//
4113 //===----------------------------------------------------------------------===//
4115 //===----------------------------------------------------------------------===//
4117 //===----------------------------------------------------------------------===//
4119 //===----------------------------------------------------------------------===//
4121 //===----------------------------------------------------------------------===//
4123 // Predicate transfer.
4124 let hasSideEffects = 0, hasNewValue = 1 in
4125 def C2_tfrpr : SInst<(outs IntRegs:$Rd), (ins PredRegs:$Ps),
4126 "$Rd = $Ps", [], "", S_2op_tc_1_SLOT23> {
4130 let IClass = 0b1000;
4131 let Inst{27-24} = 0b1001;
4133 let Inst{17-16} = Ps;
4137 // Transfer general register to predicate.
4138 let hasSideEffects = 0 in
4139 def C2_tfrrp: SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs),
4140 "$Pd = $Rs", [], "", S_2op_tc_2early_SLOT23> {
4144 let IClass = 0b1000;
4145 let Inst{27-21} = 0b0101010;
4146 let Inst{20-16} = Rs;
4151 //===----------------------------------------------------------------------===//
4153 //===----------------------------------------------------------------------===//
4155 //===----------------------------------------------------------------------===//
4157 //===----------------------------------------------------------------------===//
4158 class S_2OpInstImm<string Mnemonic, bits<3>MajOp, bits<3>MinOp,
4159 Operand Imm, list<dag> pattern = [], bit isRnd = 0>
4160 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, Imm:$src2),
4161 "$dst = "#Mnemonic#"($src1, #$src2)"#!if(isRnd, ":rnd", ""),
4165 let IClass = 0b1000;
4166 let Inst{27-24} = 0;
4167 let Inst{23-21} = MajOp;
4168 let Inst{20-16} = src1;
4169 let Inst{7-5} = MinOp;
4170 let Inst{4-0} = dst;
4173 class S_2OpInstImmI6<string Mnemonic, SDNode OpNode, bits<3>MinOp>
4174 : S_2OpInstImm<Mnemonic, 0b000, MinOp, u6Imm,
4175 [(set (i64 DoubleRegs:$dst), (OpNode (i64 DoubleRegs:$src1),
4176 u6ImmPred:$src2))]> {
4178 let Inst{13-8} = src2;
4181 // Shift by immediate.
4182 def S2_asr_i_p : S_2OpInstImmI6<"asr", sra, 0b000>;
4183 def S2_asl_i_p : S_2OpInstImmI6<"asl", shl, 0b010>;
4184 def S2_lsr_i_p : S_2OpInstImmI6<"lsr", srl, 0b001>;
4186 // Shift left by small amount and add.
4187 let AddedComplexity = 100, hasNewValue = 1, hasSideEffects = 0 in
4188 def S2_addasl_rrri: SInst <(outs IntRegs:$Rd),
4189 (ins IntRegs:$Rt, IntRegs:$Rs, u3Imm:$u3),
4190 "$Rd = addasl($Rt, $Rs, #$u3)" ,
4191 [(set (i32 IntRegs:$Rd), (add (i32 IntRegs:$Rt),
4192 (shl (i32 IntRegs:$Rs), u3ImmPred:$u3)))],
4193 "", S_3op_tc_2_SLOT23> {
4199 let IClass = 0b1100;
4201 let Inst{27-21} = 0b0100000;
4202 let Inst{20-16} = Rs;
4204 let Inst{12-8} = Rt;
4209 //===----------------------------------------------------------------------===//
4211 //===----------------------------------------------------------------------===//
4213 //===----------------------------------------------------------------------===//
4215 //===----------------------------------------------------------------------===//
4216 //===----------------------------------------------------------------------===//
4218 //===----------------------------------------------------------------------===//
4220 //===----------------------------------------------------------------------===//
4222 //===----------------------------------------------------------------------===//
4223 //===----------------------------------------------------------------------===//
4225 //===----------------------------------------------------------------------===//
4227 //===----------------------------------------------------------------------===//
4229 //===----------------------------------------------------------------------===//
4231 //===----------------------------------------------------------------------===//
4233 //===----------------------------------------------------------------------===//
4234 def HexagonBARRIER: SDNode<"HexagonISD::BARRIER", SDTNone, [SDNPHasChain]>;
4236 let hasSideEffects = 1, isSoloAX = 1 in
4237 def BARRIER : SYSInst<(outs), (ins),
4239 [(HexagonBARRIER)],"",ST_tc_st_SLOT0> {
4240 let Inst{31-28} = 0b1010;
4241 let Inst{27-21} = 0b1000000;
4244 //===----------------------------------------------------------------------===//
4246 //===----------------------------------------------------------------------===//
4247 //===----------------------------------------------------------------------===//
4249 //===----------------------------------------------------------------------===//
4251 let isExtendable = 1, isExtentSigned = 1, opExtentBits = 9, opExtentAlign = 2,
4252 opExtendable = 0, hasSideEffects = 0 in
4253 class LOOP_iBase<string mnemonic, Operand brOp, bit mustExtend = 0>
4254 : CRInst<(outs), (ins brOp:$offset, u10Imm:$src2),
4255 #mnemonic#"($offset, #$src2)",
4256 [], "" , CR_tc_3x_SLOT3> {
4260 let IClass = 0b0110;
4262 let Inst{27-22} = 0b100100;
4263 let Inst{21} = !if (!eq(mnemonic, "loop0"), 0b0, 0b1);
4264 let Inst{20-16} = src2{9-5};
4265 let Inst{12-8} = offset{8-4};
4266 let Inst{7-5} = src2{4-2};
4267 let Inst{4-3} = offset{3-2};
4268 let Inst{1-0} = src2{1-0};
4271 let isExtendable = 1, isExtentSigned = 1, opExtentBits = 9, opExtentAlign = 2,
4272 opExtendable = 0, hasSideEffects = 0 in
4273 class LOOP_rBase<string mnemonic, Operand brOp, bit mustExtend = 0>
4274 : CRInst<(outs), (ins brOp:$offset, IntRegs:$src2),
4275 #mnemonic#"($offset, $src2)",
4276 [], "" ,CR_tc_3x_SLOT3> {
4280 let IClass = 0b0110;
4282 let Inst{27-22} = 0b000000;
4283 let Inst{21} = !if (!eq(mnemonic, "loop0"), 0b0, 0b1);
4284 let Inst{20-16} = src2;
4285 let Inst{12-8} = offset{8-4};
4286 let Inst{4-3} = offset{3-2};
4289 multiclass LOOP_ri<string mnemonic> {
4290 def i : LOOP_iBase<mnemonic, brtarget>;
4291 def r : LOOP_rBase<mnemonic, brtarget>;
4295 let Defs = [SA0, LC0, USR] in
4296 defm J2_loop0 : LOOP_ri<"loop0">;
4298 // Interestingly only loop0's appear to set usr.lpcfg
4299 let Defs = [SA1, LC1] in
4300 defm J2_loop1 : LOOP_ri<"loop1">;
4302 let isBranch = 1, isTerminator = 1, hasSideEffects = 0,
4303 Defs = [PC, LC0], Uses = [SA0, LC0] in {
4304 def ENDLOOP0 : Endloop<(outs), (ins brtarget:$offset),
4309 let isBranch = 1, isTerminator = 1, hasSideEffects = 0,
4310 Defs = [PC, LC1], Uses = [SA1, LC1] in {
4311 def ENDLOOP1 : Endloop<(outs), (ins brtarget:$offset),
4316 // Pipelined loop instructions, sp[123]loop0
4317 let Defs = [LC0, SA0, P3, USR], hasSideEffects = 0,
4318 isExtentSigned = 1, isExtendable = 1, opExtentBits = 9, opExtentAlign = 2,
4319 opExtendable = 0, isPredicateLate = 1 in
4320 class SPLOOP_iBase<string SP, bits<2> op>
4321 : CRInst <(outs), (ins brtarget:$r7_2, u10Imm:$U10),
4322 "p3 = sp"#SP#"loop0($r7_2, #$U10)" > {
4326 let IClass = 0b0110;
4328 let Inst{22-21} = op;
4329 let Inst{27-23} = 0b10011;
4330 let Inst{20-16} = U10{9-5};
4331 let Inst{12-8} = r7_2{8-4};
4332 let Inst{7-5} = U10{4-2};
4333 let Inst{4-3} = r7_2{3-2};
4334 let Inst{1-0} = U10{1-0};
4337 let Defs = [LC0, SA0, P3, USR], hasSideEffects = 0,
4338 isExtentSigned = 1, isExtendable = 1, opExtentBits = 9, opExtentAlign = 2,
4339 opExtendable = 0, isPredicateLate = 1 in
4340 class SPLOOP_rBase<string SP, bits<2> op>
4341 : CRInst <(outs), (ins brtarget:$r7_2, IntRegs:$Rs),
4342 "p3 = sp"#SP#"loop0($r7_2, $Rs)" > {
4346 let IClass = 0b0110;
4348 let Inst{22-21} = op;
4349 let Inst{27-23} = 0b00001;
4350 let Inst{20-16} = Rs;
4351 let Inst{12-8} = r7_2{8-4};
4352 let Inst{4-3} = r7_2{3-2};
4355 multiclass SPLOOP_ri<string mnemonic, bits<2> op> {
4356 def i : SPLOOP_iBase<mnemonic, op>;
4357 def r : SPLOOP_rBase<mnemonic, op>;
4360 defm J2_ploop1s : SPLOOP_ri<"1", 0b01>;
4361 defm J2_ploop2s : SPLOOP_ri<"2", 0b10>;
4362 defm J2_ploop3s : SPLOOP_ri<"3", 0b11>;
4364 // if (Rs[!>=<]=#0) jump:[t/nt]
4365 let Defs = [PC], isPredicated = 1, isBranch = 1, hasSideEffects = 0,
4366 hasSideEffects = 0 in
4367 class J2_jump_0_Base<string compare, bit isTak, bits<2> op>
4368 : CRInst <(outs), (ins IntRegs:$Rs, brtarget:$r13_2),
4369 "if ($Rs"#compare#"#0) jump"#!if(isTak, ":t", ":nt")#" $r13_2" > {
4373 let IClass = 0b0110;
4375 let Inst{27-24} = 0b0001;
4376 let Inst{23-22} = op;
4377 let Inst{12} = isTak;
4378 let Inst{21} = r13_2{14};
4379 let Inst{20-16} = Rs;
4380 let Inst{11-1} = r13_2{12-2};
4381 let Inst{13} = r13_2{13};
4384 multiclass J2_jump_compare_0<string compare, bits<2> op> {
4385 def NAME : J2_jump_0_Base<compare, 0, op>;
4386 def NAME#pt : J2_jump_0_Base<compare, 1, op>;
4389 defm J2_jumprz : J2_jump_compare_0<"!=", 0b00>;
4390 defm J2_jumprgtez : J2_jump_compare_0<">=", 0b01>;
4391 defm J2_jumprnz : J2_jump_compare_0<"==", 0b10>;
4392 defm J2_jumprltez : J2_jump_compare_0<"<=", 0b11>;
4394 // Transfer to/from Control/GPR Guest/GPR
4395 let hasSideEffects = 0 in
4396 class TFR_CR_RS_base<RegisterClass CTRC, RegisterClass RC, bit isDouble>
4397 : CRInst <(outs CTRC:$dst), (ins RC:$src),
4398 "$dst = $src", [], "", CR_tc_3x_SLOT3> {
4402 let IClass = 0b0110;
4404 let Inst{27-25} = 0b001;
4405 let Inst{24} = isDouble;
4406 let Inst{23-21} = 0b001;
4407 let Inst{20-16} = src;
4408 let Inst{4-0} = dst;
4411 def A2_tfrrcr : TFR_CR_RS_base<CtrRegs, IntRegs, 0b0>;
4412 def : InstAlias<"m0 = $Rs", (A2_tfrrcr C6, IntRegs:$Rs)>;
4413 def : InstAlias<"m1 = $Rs", (A2_tfrrcr C7, IntRegs:$Rs)>;
4415 let hasSideEffects = 0 in
4416 class TFR_RD_CR_base<RegisterClass RC, RegisterClass CTRC, bit isSingle>
4417 : CRInst <(outs RC:$dst), (ins CTRC:$src),
4418 "$dst = $src", [], "", CR_tc_3x_SLOT3> {
4422 let IClass = 0b0110;
4424 let Inst{27-26} = 0b10;
4425 let Inst{25} = isSingle;
4426 let Inst{24-21} = 0b0000;
4427 let Inst{20-16} = src;
4428 let Inst{4-0} = dst;
4431 let hasNewValue = 1, opNewValue = 0 in
4432 def A2_tfrcrr : TFR_RD_CR_base<IntRegs, CtrRegs, 1>;
4433 def : InstAlias<"$Rd = m0", (A2_tfrcrr IntRegs:$Rd, C6)>;
4434 def : InstAlias<"$Rd = m1", (A2_tfrcrr IntRegs:$Rd, C7)>;
4436 // Y4_trace: Send value to etm trace.
4437 let isSoloAX = 1, hasSideEffects = 0 in
4438 def Y4_trace: CRInst <(outs), (ins IntRegs:$Rs),
4442 let IClass = 0b0110;
4443 let Inst{27-21} = 0b0010010;
4444 let Inst{20-16} = Rs;
4447 let AddedComplexity = 100, isPredicated = 1, isCodeGenOnly = 1 in
4448 def TFR_condset_ri : ALU32_rr<(outs IntRegs:$dst),
4449 (ins PredRegs:$src1, IntRegs:$src2, s12Imm:$src3),
4450 "Error; should not emit",
4451 [(set (i32 IntRegs:$dst),
4452 (i32 (select (i1 PredRegs:$src1), (i32 IntRegs:$src2),
4453 s12ImmPred:$src3)))]>;
4455 let AddedComplexity = 100, isPredicated = 1, isCodeGenOnly = 1 in
4456 def TFR_condset_ir : ALU32_rr<(outs IntRegs:$dst),
4457 (ins PredRegs:$src1, s12Imm:$src2, IntRegs:$src3),
4458 "Error; should not emit",
4459 [(set (i32 IntRegs:$dst),
4460 (i32 (select (i1 PredRegs:$src1), s12ImmPred:$src2,
4461 (i32 IntRegs:$src3))))]>;
4463 let AddedComplexity = 100, isPredicated = 1, isCodeGenOnly = 1 in
4464 def TFR_condset_ii : ALU32_rr<(outs IntRegs:$dst),
4465 (ins PredRegs:$src1, s12Imm:$src2, s12Imm:$src3),
4466 "Error; should not emit",
4467 [(set (i32 IntRegs:$dst),
4468 (i32 (select (i1 PredRegs:$src1), s12ImmPred:$src2,
4469 s12ImmPred:$src3)))]>;
4471 // Generate frameindex addresses.
4472 let isReMaterializable = 1, isCodeGenOnly = 1 in
4473 def TFR_FI : ALU32_ri<(outs IntRegs:$dst), (ins FrameIndex:$src1),
4474 "$dst = add($src1)",
4475 [(set (i32 IntRegs:$dst), ADDRri:$src1)]>;
4477 // Support for generating global address.
4478 // Taken from X86InstrInfo.td.
4479 def SDTHexagonCONST32 : SDTypeProfile<1, 1, [SDTCisVT<0, i32>,
4482 def HexagonCONST32 : SDNode<"HexagonISD::CONST32", SDTHexagonCONST32>;
4483 def HexagonCONST32_GP : SDNode<"HexagonISD::CONST32_GP", SDTHexagonCONST32>;
4485 // HI/LO Instructions
4486 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0,
4487 isAsmParserOnly = 1 in
4488 def LO : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
4489 "$dst.l = #LO($global)",
4492 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0,
4493 isAsmParserOnly = 1 in
4494 def HI : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
4495 "$dst.h = #HI($global)",
4498 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0,
4499 isAsmParserOnly = 1 in
4500 def LOi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value),
4501 "$dst.l = #LO($imm_value)",
4505 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0,
4506 isAsmParserOnly = 1 in
4507 def HIi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value),
4508 "$dst.h = #HI($imm_value)",
4511 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0,
4512 isAsmParserOnly = 1 in
4513 def LO_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt),
4514 "$dst.l = #LO($jt)",
4517 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0,
4518 isAsmParserOnly = 1 in
4519 def HI_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt),
4520 "$dst.h = #HI($jt)",
4524 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0,
4525 isAsmParserOnly = 1 in
4526 def LO_label : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
4527 "$dst.l = #LO($label)",
4530 let isReMaterializable = 1, isMoveImm = 1 , hasSideEffects = 0,
4531 isAsmParserOnly = 1 in
4532 def HI_label : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
4533 "$dst.h = #HI($label)",
4536 // This pattern is incorrect. When we add small data, we should change
4537 // this pattern to use memw(#foo).
4538 // This is for sdata.
4539 let isMoveImm = 1, isAsmParserOnly = 1 in
4540 def CONST32 : LDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
4541 "$dst = CONST32(#$global)",
4542 [(set (i32 IntRegs:$dst),
4543 (load (HexagonCONST32 tglobaltlsaddr:$global)))]>;
4545 // This is for non-sdata.
4546 let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in
4547 def CONST32_set : LDInst2<(outs IntRegs:$dst), (ins globaladdress:$global),
4548 "$dst = CONST32(#$global)",
4549 [(set (i32 IntRegs:$dst),
4550 (HexagonCONST32 tglobaladdr:$global))]>;
4552 let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in
4553 def CONST32_set_jt : LDInst2<(outs IntRegs:$dst), (ins jumptablebase:$jt),
4554 "$dst = CONST32(#$jt)",
4555 [(set (i32 IntRegs:$dst),
4556 (HexagonCONST32 tjumptable:$jt))]>;
4558 let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in
4559 def CONST32GP_set : LDInst2<(outs IntRegs:$dst), (ins globaladdress:$global),
4560 "$dst = CONST32(#$global)",
4561 [(set (i32 IntRegs:$dst),
4562 (HexagonCONST32_GP tglobaladdr:$global))]>;
4564 let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in
4565 def CONST32_Int_Real : LDInst2<(outs IntRegs:$dst), (ins i32imm:$global),
4566 "$dst = CONST32(#$global)",
4567 [(set (i32 IntRegs:$dst), imm:$global) ]>;
4569 // Map BlockAddress lowering to CONST32_Int_Real
4570 def : Pat<(HexagonCONST32_GP tblockaddress:$addr),
4571 (CONST32_Int_Real tblockaddress:$addr)>;
4573 let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in
4574 def CONST32_Label : LDInst2<(outs IntRegs:$dst), (ins bblabel:$label),
4575 "$dst = CONST32($label)",
4576 [(set (i32 IntRegs:$dst), (HexagonCONST32 bbl:$label))]>;
4578 let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in
4579 def CONST64_Int_Real : LDInst2<(outs DoubleRegs:$dst), (ins i64imm:$global),
4580 "$dst = CONST64(#$global)",
4581 [(set (i64 DoubleRegs:$dst), imm:$global) ]>;
4583 let isCodeGenOnly = 1 in
4584 def TFR_PdFalse : SInst<(outs PredRegs:$dst), (ins),
4585 "$dst = xor($dst, $dst)",
4586 [(set (i1 PredRegs:$dst), 0)]>;
4588 // Pseudo instructions.
4589 def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
4590 def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
4591 SDTCisVT<1, i32> ]>;
4593 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
4594 [SDNPHasChain, SDNPOutGlue]>;
4595 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,
4596 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
4598 def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
4600 // For tailcalls a HexagonTCRet SDNode has 3 SDNode Properties - a chain,
4601 // Optional Flag and Variable Arguments.
4602 // Its 1 Operand has pointer type.
4603 def HexagonTCRet : SDNode<"HexagonISD::TC_RETURN", SDT_SPCall,
4604 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
4606 let Defs = [R29, R30], Uses = [R31, R30, R29] in {
4607 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
4608 "Should never be emitted",
4609 [(callseq_start timm:$amt)]>;
4612 let Defs = [R29, R30, R31], Uses = [R29] in {
4613 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
4614 "Should never be emitted",
4615 [(callseq_end timm:$amt1, timm:$amt2)]>;
4618 let isCall = 1, hasSideEffects = 0, isAsmParserOnly = 1,
4619 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
4620 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
4621 def CALL : JInst<(outs), (ins calltarget:$dst),
4625 // Call subroutine indirectly.
4626 let Defs = VolatileV3.Regs in
4627 def J2_callr : JUMPR_MISC_CALLR<0, 1>;
4629 // Indirect tail-call.
4630 let isCodeGenOnly = 1, isCall = 1, isReturn = 1 in
4631 def TCRETURNR : T_JMPr;
4633 // Direct tail-calls.
4634 let isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0,
4635 isTerminator = 1, isCodeGenOnly = 1 in {
4636 def TCRETURNtg : JInst<(outs), (ins calltarget:$dst), "jump $dst",
4637 [], "", J_tc_2early_SLOT23>;
4638 def TCRETURNtext : JInst<(outs), (ins calltarget:$dst), "jump $dst",
4639 [], "", J_tc_2early_SLOT23>;
4643 def : Pat<(HexagonTCRet tglobaladdr:$dst),
4644 (TCRETURNtg tglobaladdr:$dst)>;
4645 def : Pat<(HexagonTCRet texternalsym:$dst),
4646 (TCRETURNtext texternalsym:$dst)>;
4647 def : Pat<(HexagonTCRet (i32 IntRegs:$dst)),
4648 (TCRETURNR (i32 IntRegs:$dst))>;
4650 // Map from r0 = and(r1, 65535) to r0 = zxth(r1)
4651 def : Pat <(and (i32 IntRegs:$src1), 65535),
4652 (A2_zxth (i32 IntRegs:$src1))>;
4654 // Map from r0 = and(r1, 255) to r0 = zxtb(r1).
4655 def : Pat <(and (i32 IntRegs:$src1), 255),
4656 (A2_zxtb (i32 IntRegs:$src1))>;
4658 // Map Add(p1, true) to p1 = not(p1).
4659 // Add(p1, false) should never be produced,
4660 // if it does, it got to be mapped to NOOP.
4661 def : Pat <(add (i1 PredRegs:$src1), -1),
4662 (C2_not (i1 PredRegs:$src1))>;
4664 // Map from p0 = pnot(p0); r0 = mux(p0, #i, #j) => r0 = mux(p0, #j, #i).
4665 def : Pat <(select (not (i1 PredRegs:$src1)), s8ImmPred:$src2, s8ImmPred:$src3),
4666 (i32 (TFR_condset_ii (i1 PredRegs:$src1), s8ImmPred:$src3,
4669 // Map from p0 = pnot(p0); r0 = select(p0, #i, r1)
4670 // => r0 = TFR_condset_ri(p0, r1, #i)
4671 def : Pat <(select (not (i1 PredRegs:$src1)), s12ImmPred:$src2,
4672 (i32 IntRegs:$src3)),
4673 (i32 (TFR_condset_ri (i1 PredRegs:$src1), (i32 IntRegs:$src3),
4674 s12ImmPred:$src2))>;
4676 // Map from p0 = pnot(p0); r0 = mux(p0, r1, #i)
4677 // => r0 = TFR_condset_ir(p0, #i, r1)
4678 def : Pat <(select (not (i1 PredRegs:$src1)), IntRegs:$src2, s12ImmPred:$src3),
4679 (i32 (TFR_condset_ir (i1 PredRegs:$src1), s12ImmPred:$src3,
4680 (i32 IntRegs:$src2)))>;
4682 // Map from p0 = pnot(p0); if (p0) jump => if (!p0) jump.
4683 def : Pat <(brcond (not (i1 PredRegs:$src1)), bb:$offset),
4684 (J2_jumpf (i1 PredRegs:$src1), bb:$offset)>;
4686 // Map from p2 = pnot(p2); p1 = and(p0, p2) => p1 = and(p0, !p2).
4687 def : Pat <(and (i1 PredRegs:$src1), (not (i1 PredRegs:$src2))),
4688 (i1 (C2_andn (i1 PredRegs:$src1), (i1 PredRegs:$src2)))>;
4691 let AddedComplexity = 100 in
4692 def : Pat <(i64 (zextloadi1 (HexagonCONST32 tglobaladdr:$global))),
4693 (i64 (A2_combinew (A2_tfrsi 0),
4694 (L2_loadrub_io (CONST32_set tglobaladdr:$global), 0)))>,
4697 // Map from i1 loads to 32 bits. This assumes that the i1* is byte aligned.
4698 let AddedComplexity = 10 in
4699 def : Pat <(i32 (zextloadi1 ADDRriS11_0:$addr)),
4700 (i32 (A2_and (i32 (L2_loadrb_io AddrFI:$addr, 0)), (A2_tfrsi 0x1)))>;
4702 // Map from Rdd = sign_extend_inreg(Rss, i32) -> Rdd = A2_sxtw(Rss.lo).
4703 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i32)),
4704 (i64 (A2_sxtw (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg))))>;
4706 // Map from Rdd = sign_extend_inreg(Rss, i16) -> Rdd = A2_sxtw(SXTH(Rss.lo)).
4707 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i16)),
4708 (i64 (A2_sxtw (i32 (A2_sxth (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
4709 subreg_loreg))))))>;
4711 // Map from Rdd = sign_extend_inreg(Rss, i8) -> Rdd = A2_sxtw(SXTB(Rss.lo)).
4712 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i8)),
4713 (i64 (A2_sxtw (i32 (A2_sxtb (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
4714 subreg_loreg))))))>;
4716 // We want to prevent emitting pnot's as much as possible.
4717 // Map brcond with an unsupported setcc to a J2_jumpf.
4718 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4720 (J2_jumpf (C2_cmpeq (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
4723 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), s10ImmPred:$src2)),
4725 (J2_jumpf (C2_cmpeqi (i32 IntRegs:$src1), s10ImmPred:$src2), bb:$offset)>;
4727 def : Pat <(brcond (i1 (setne (i1 PredRegs:$src1), (i1 -1))), bb:$offset),
4728 (J2_jumpf (i1 PredRegs:$src1), bb:$offset)>;
4730 def : Pat <(brcond (i1 (setne (i1 PredRegs:$src1), (i1 0))), bb:$offset),
4731 (J2_jumpt (i1 PredRegs:$src1), bb:$offset)>;
4733 // cmp.lt(Rs, Imm) -> !cmp.ge(Rs, Imm) -> !cmp.gt(Rs, Imm-1)
4734 def : Pat <(brcond (i1 (setlt (i32 IntRegs:$src1), s8ImmPred:$src2)),
4736 (J2_jumpf (C2_cmpgti (i32 IntRegs:$src1),
4737 (DEC_CONST_SIGNED s8ImmPred:$src2)), bb:$offset)>;
4739 // cmp.lt(r0, r1) -> cmp.gt(r1, r0)
4740 def : Pat <(brcond (i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4742 (J2_jumpt (C2_cmpgt (i32 IntRegs:$src2), (i32 IntRegs:$src1)), bb:$offset)>;
4744 def : Pat <(brcond (i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
4746 (J2_jumpf (C2_cmpgtup (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)),
4749 def : Pat <(brcond (i1 (setule (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4751 (J2_jumpf (C2_cmpgtu (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
4754 def : Pat <(brcond (i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
4756 (J2_jumpf (C2_cmpgtup (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
4759 // Map from a 64-bit select to an emulated 64-bit mux.
4760 // Hexagon does not support 64-bit MUXes; so emulate with combines.
4761 def : Pat <(select (i1 PredRegs:$src1), (i64 DoubleRegs:$src2),
4762 (i64 DoubleRegs:$src3)),
4763 (i64 (A2_combinew (i32 (C2_mux (i1 PredRegs:$src1),
4764 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
4766 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src3),
4768 (i32 (C2_mux (i1 PredRegs:$src1),
4769 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
4771 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src3),
4772 subreg_loreg))))))>;
4774 // Map from a 1-bit select to logical ops.
4775 // From LegalizeDAG.cpp: (B1 ? B2 : B3) <=> (B1 & B2)|(!B1&B3).
4776 def : Pat <(select (i1 PredRegs:$src1), (i1 PredRegs:$src2),
4777 (i1 PredRegs:$src3)),
4778 (C2_or (C2_and (i1 PredRegs:$src1), (i1 PredRegs:$src2)),
4779 (C2_and (C2_not (i1 PredRegs:$src1)), (i1 PredRegs:$src3)))>;
4781 // Map Pd = load(addr) -> Rs = load(addr); Pd = Rs.
4782 def : Pat<(i1 (load ADDRriS11_2:$addr)),
4783 (i1 (C2_tfrrp (i32 (L2_loadrb_io AddrFI:$addr, 0))))>;
4785 // Map for truncating from 64 immediates to 32 bit immediates.
4786 def : Pat<(i32 (trunc (i64 DoubleRegs:$src))),
4787 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src), subreg_loreg))>;
4789 // Map for truncating from i64 immediates to i1 bit immediates.
4790 def : Pat<(i1 (trunc (i64 DoubleRegs:$src))),
4791 (i1 (C2_tfrrp (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
4794 // Map memb(Rs) = Rdd -> memb(Rs) = Rt.
4795 def : Pat<(truncstorei8 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
4796 (S2_storerb_io AddrFI:$addr, 0, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
4799 // Map memh(Rs) = Rdd -> memh(Rs) = Rt.
4800 def : Pat<(truncstorei16 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
4801 (S2_storerh_io AddrFI:$addr, 0, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
4803 // Map memw(Rs) = Rdd -> memw(Rs) = Rt
4804 def : Pat<(truncstorei32 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
4805 (S2_storeri_io AddrFI:$addr, 0, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
4808 // Map memw(Rs) = Rdd -> memw(Rs) = Rt.
4809 def : Pat<(truncstorei32 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
4810 (S2_storeri_io AddrFI:$addr, 0, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
4813 // Map from i1 = constant<-1>; memw(addr) = i1 -> r0 = 1; memw(addr) = r0.
4814 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
4815 (S2_storerb_io AddrFI:$addr, 0, (A2_tfrsi 1))>;
4818 // Map from i1 = constant<-1>; store i1 -> r0 = 1; store r0.
4819 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
4820 (S2_storerb_io AddrFI:$addr, 0, (A2_tfrsi 1))>;
4822 // Map from memb(Rs) = Pd -> Rt = mux(Pd, #0, #1); store Rt.
4823 def : Pat<(store (i1 PredRegs:$src1), ADDRriS11_2:$addr),
4824 (S2_storerb_io AddrFI:$addr, 0, (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0)) )>;
4826 // Map Rdd = anyext(Rs) -> Rdd = A2_sxtw(Rs).
4827 // Hexagon_TODO: We can probably use combine but that will cost 2 instructions.
4828 // Better way to do this?
4829 def : Pat<(i64 (anyext (i32 IntRegs:$src1))),
4830 (i64 (A2_sxtw (i32 IntRegs:$src1)))>;
4832 // Map cmple -> cmpgt.
4833 // rs <= rt -> !(rs > rt).
4834 def : Pat<(i1 (setle (i32 IntRegs:$src1), s10ExtPred:$src2)),
4835 (i1 (C2_not (C2_cmpgti (i32 IntRegs:$src1), s10ExtPred:$src2)))>;
4837 // rs <= rt -> !(rs > rt).
4838 def : Pat<(i1 (setle (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4839 (i1 (C2_not (C2_cmpgt (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
4841 // Rss <= Rtt -> !(Rss > Rtt).
4842 def : Pat<(i1 (setle (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
4843 (i1 (C2_not (C2_cmpgtp (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))))>;
4845 // Map cmpne -> cmpeq.
4846 // Hexagon_TODO: We should improve on this.
4847 // rs != rt -> !(rs == rt).
4848 def : Pat <(i1 (setne (i32 IntRegs:$src1), s10ExtPred:$src2)),
4849 (i1 (C2_not(i1 (C2_cmpeqi (i32 IntRegs:$src1), s10ExtPred:$src2))))>;
4851 // Map cmpne(Rs) -> !cmpeqe(Rs).
4852 // rs != rt -> !(rs == rt).
4853 def : Pat <(i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4854 (i1 (C2_not (i1 (C2_cmpeq (i32 IntRegs:$src1), (i32 IntRegs:$src2)))))>;
4856 // Convert setne back to xor for hexagon since we compute w/ pred registers.
4857 def : Pat <(i1 (setne (i1 PredRegs:$src1), (i1 PredRegs:$src2))),
4858 (i1 (C2_xor (i1 PredRegs:$src1), (i1 PredRegs:$src2)))>;
4860 // Map cmpne(Rss) -> !cmpew(Rss).
4861 // rs != rt -> !(rs == rt).
4862 def : Pat <(i1 (setne (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
4863 (i1 (C2_not (i1 (C2_cmpeqp (i64 DoubleRegs:$src1),
4864 (i64 DoubleRegs:$src2)))))>;
4866 // Map cmpge(Rs, Rt) -> !(cmpgt(Rs, Rt).
4867 // rs >= rt -> !(rt > rs).
4868 def : Pat <(i1 (setge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4869 (i1 (C2_not (i1 (C2_cmpgt (i32 IntRegs:$src2), (i32 IntRegs:$src1)))))>;
4871 // cmpge(Rs, Imm) -> cmpgt(Rs, Imm-1)
4872 def : Pat <(i1 (setge (i32 IntRegs:$src1), s8ExtPred:$src2)),
4873 (i1 (C2_cmpgti (i32 IntRegs:$src1), (DEC_CONST_SIGNED s8ExtPred:$src2)))>;
4875 // Map cmpge(Rss, Rtt) -> !cmpgt(Rtt, Rss).
4876 // rss >= rtt -> !(rtt > rss).
4877 def : Pat <(i1 (setge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
4878 (i1 (C2_not (i1 (C2_cmpgtp (i64 DoubleRegs:$src2),
4879 (i64 DoubleRegs:$src1)))))>;
4881 // Map cmplt(Rs, Imm) -> !cmpge(Rs, Imm).
4882 // !cmpge(Rs, Imm) -> !cmpgt(Rs, Imm-1).
4883 // rs < rt -> !(rs >= rt).
4884 def : Pat <(i1 (setlt (i32 IntRegs:$src1), s8ExtPred:$src2)),
4885 (i1 (C2_not (C2_cmpgti (i32 IntRegs:$src1), (DEC_CONST_SIGNED s8ExtPred:$src2))))>;
4887 // Map cmplt(Rs, Rt) -> cmpgt(Rt, Rs).
4888 // rs < rt -> rt > rs.
4889 // We can let assembler map it, or we can do in the compiler itself.
4890 def : Pat <(i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4891 (i1 (C2_cmpgt (i32 IntRegs:$src2), (i32 IntRegs:$src1)))>;
4893 // Map cmplt(Rss, Rtt) -> cmpgt(Rtt, Rss).
4894 // rss < rtt -> (rtt > rss).
4895 def : Pat <(i1 (setlt (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
4896 (i1 (C2_cmpgtp (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)))>;
4898 // Map from cmpltu(Rs, Rd) -> cmpgtu(Rd, Rs)
4899 // rs < rt -> rt > rs.
4900 // We can let assembler map it, or we can do in the compiler itself.
4901 def : Pat <(i1 (setult (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4902 (i1 (C2_cmpgtu (i32 IntRegs:$src2), (i32 IntRegs:$src1)))>;
4904 // Map from cmpltu(Rss, Rdd) -> cmpgtu(Rdd, Rss).
4905 // rs < rt -> rt > rs.
4906 def : Pat <(i1 (setult (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
4907 (i1 (C2_cmpgtup (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)))>;
4909 // Generate cmpgeu(Rs, #0) -> cmpeq(Rs, Rs)
4910 def : Pat <(i1 (setuge (i32 IntRegs:$src1), 0)),
4911 (i1 (C2_cmpeq (i32 IntRegs:$src1), (i32 IntRegs:$src1)))>;
4913 // Generate cmpgeu(Rs, #u8) -> cmpgtu(Rs, #u8 -1)
4914 def : Pat <(i1 (setuge (i32 IntRegs:$src1), u8ExtPred:$src2)),
4915 (i1 (C2_cmpgtui (i32 IntRegs:$src1), (DEC_CONST_UNSIGNED u8ExtPred:$src2)))>;
4917 // Generate cmpgtu(Rs, #u9)
4918 def : Pat <(i1 (setugt (i32 IntRegs:$src1), u9ExtPred:$src2)),
4919 (i1 (C2_cmpgtui (i32 IntRegs:$src1), u9ExtPred:$src2))>;
4921 // Map from Rs >= Rt -> !(Rt > Rs).
4922 // rs >= rt -> !(rt > rs).
4923 def : Pat <(i1 (setuge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4924 (i1 (C2_not (C2_cmpgtu (i32 IntRegs:$src2), (i32 IntRegs:$src1))))>;
4926 // Map from Rs >= Rt -> !(Rt > Rs).
4927 // rs >= rt -> !(rt > rs).
4928 def : Pat <(i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
4929 (i1 (C2_not (C2_cmpgtup (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1))))>;
4931 // Map from cmpleu(Rs, Rt) -> !cmpgtu(Rs, Rt).
4932 // Map from (Rs <= Rt) -> !(Rs > Rt).
4933 def : Pat <(i1 (setule (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4934 (i1 (C2_not (C2_cmpgtu (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
4936 // Map from cmpleu(Rss, Rtt) -> !cmpgtu(Rss, Rtt-1).
4937 // Map from (Rs <= Rt) -> !(Rs > Rt).
4938 def : Pat <(i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
4939 (i1 (C2_not (C2_cmpgtup (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))))>;
4943 def : Pat <(i32 (sext (i1 PredRegs:$src1))),
4944 (i32 (C2_muxii (i1 PredRegs:$src1), -1, 0))>;
4947 def : Pat <(i64 (sext (i1 PredRegs:$src1))),
4948 (i64 (A2_combinew (A2_tfrsi -1), (C2_muxii (i1 PredRegs:$src1), -1, 0)))>;
4950 // Convert sign-extended load back to load and sign extend.
4952 def: Pat <(i64 (sextloadi8 ADDRriS11_0:$src1)),
4953 (i64 (A2_sxtw (L2_loadrb_io AddrFI:$src1, 0)))>;
4955 // Convert any-extended load back to load and sign extend.
4957 def: Pat <(i64 (extloadi8 ADDRriS11_0:$src1)),
4958 (i64 (A2_sxtw (L2_loadrb_io AddrFI:$src1, 0)))>;
4960 // Convert sign-extended load back to load and sign extend.
4962 def: Pat <(i64 (sextloadi16 ADDRriS11_1:$src1)),
4963 (i64 (A2_sxtw (L2_loadrh_io AddrFI:$src1, 0)))>;
4965 // Convert sign-extended load back to load and sign extend.
4967 def: Pat <(i64 (sextloadi32 ADDRriS11_2:$src1)),
4968 (i64 (A2_sxtw (L2_loadri_io AddrFI:$src1, 0)))>;
4973 def : Pat <(i32 (zext (i1 PredRegs:$src1))),
4974 (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0))>;
4977 def : Pat <(i64 (zext (i1 PredRegs:$src1))),
4978 (i64 (A2_combinew (A2_tfrsi 0), (C2_muxii (i1 PredRegs:$src1), 1, 0)))>,
4982 def : Pat <(i64 (zext (i32 IntRegs:$src1))),
4983 (i64 (A2_combinew (A2_tfrsi 0), (i32 IntRegs:$src1)))>,
4987 def: Pat <(i64 (zextloadi8 ADDRriS11_0:$src1)),
4988 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadrub_io AddrFI:$src1, 0)))>,
4991 let AddedComplexity = 20 in
4992 def: Pat <(i64 (zextloadi8 (add (i32 IntRegs:$src1),
4993 s11_0ExtPred:$offset))),
4994 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadrub_io IntRegs:$src1,
4995 s11_0ExtPred:$offset)))>,
4999 def: Pat <(i64 (zextloadi1 ADDRriS11_0:$src1)),
5000 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadrub_io AddrFI:$src1, 0)))>,
5003 let AddedComplexity = 20 in
5004 def: Pat <(i64 (zextloadi1 (add (i32 IntRegs:$src1),
5005 s11_0ExtPred:$offset))),
5006 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadrub_io IntRegs:$src1,
5007 s11_0ExtPred:$offset)))>,
5011 def: Pat <(i64 (zextloadi16 ADDRriS11_1:$src1)),
5012 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadruh_io AddrFI:$src1, 0)))>,
5015 let AddedComplexity = 20 in
5016 def: Pat <(i64 (zextloadi16 (add (i32 IntRegs:$src1),
5017 s11_1ExtPred:$offset))),
5018 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadruh_io IntRegs:$src1,
5019 s11_1ExtPred:$offset)))>,
5023 def: Pat <(i64 (zextloadi32 ADDRriS11_2:$src1)),
5024 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadri_io AddrFI:$src1, 0)))>,
5027 let AddedComplexity = 100 in
5028 def: Pat <(i64 (zextloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
5029 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadri_io IntRegs:$src1,
5030 s11_2ExtPred:$offset)))>,
5033 let AddedComplexity = 10 in
5034 def: Pat <(i32 (zextloadi1 ADDRriS11_0:$src1)),
5035 (i32 (L2_loadri_io AddrFI:$src1, 0))>;
5037 // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
5038 def : Pat <(i32 (zext (i1 PredRegs:$src1))),
5039 (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0))>;
5041 // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
5042 def : Pat <(i32 (anyext (i1 PredRegs:$src1))),
5043 (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0))>;
5045 // Map from Rss = Pd to Rdd = A2_sxtw (mux(Pd, #1, #0))
5046 def : Pat <(i64 (anyext (i1 PredRegs:$src1))),
5047 (i64 (A2_sxtw (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0))))>;
5050 let AddedComplexity = 100 in
5051 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
5053 (i64 (zextloadi32 (i32 (add IntRegs:$src2,
5054 s11_2ExtPred:$offset2)))))),
5055 (i64 (A2_combinew (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
5056 (L2_loadri_io IntRegs:$src2,
5057 s11_2ExtPred:$offset2)))>;
5059 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
5061 (i64 (zextloadi32 ADDRriS11_2:$srcLow)))),
5062 (i64 (A2_combinew (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
5063 (L2_loadri_io AddrFI:$srcLow, 0)))>;
5065 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
5067 (i64 (zext (i32 IntRegs:$srcLow))))),
5068 (i64 (A2_combinew (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
5071 let AddedComplexity = 100 in
5072 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
5074 (i64 (zextloadi32 (i32 (add IntRegs:$src2,
5075 s11_2ExtPred:$offset2)))))),
5076 (i64 (A2_combinew (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
5077 (L2_loadri_io IntRegs:$src2,
5078 s11_2ExtPred:$offset2)))>;
5080 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
5082 (i64 (zextloadi32 ADDRriS11_2:$srcLow)))),
5083 (i64 (A2_combinew (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
5084 (L2_loadri_io AddrFI:$srcLow, 0)))>;
5086 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
5088 (i64 (zext (i32 IntRegs:$srcLow))))),
5089 (i64 (A2_combinew (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
5092 // Any extended 64-bit load.
5093 // anyext i32 -> i64
5094 def: Pat <(i64 (extloadi32 ADDRriS11_2:$src1)),
5095 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadri_io AddrFI:$src1, 0)))>,
5098 // When there is an offset we should prefer the pattern below over the pattern above.
5099 // The complexity of the above is 13 (gleaned from HexagonGenDAGIsel.inc)
5100 // So this complexity below is comfortably higher to allow for choosing the below.
5101 // If this is not done then we generate addresses such as
5102 // ********************************************
5103 // r1 = add (r0, #4)
5104 // r1 = memw(r1 + #0)
5106 // r1 = memw(r0 + #4)
5107 // ********************************************
5108 let AddedComplexity = 100 in
5109 def: Pat <(i64 (extloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
5110 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadri_io IntRegs:$src1,
5111 s11_2ExtPred:$offset)))>,
5114 // anyext i16 -> i64.
5115 def: Pat <(i64 (extloadi16 ADDRriS11_2:$src1)),
5116 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadrh_io AddrFI:$src1, 0)))>,
5119 let AddedComplexity = 20 in
5120 def: Pat <(i64 (extloadi16 (add (i32 IntRegs:$src1),
5121 s11_1ExtPred:$offset))),
5122 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadrh_io IntRegs:$src1,
5123 s11_1ExtPred:$offset)))>,
5126 // Map from Rdd = zxtw(Rs) -> Rdd = combine(0, Rs).
5127 def : Pat<(i64 (zext (i32 IntRegs:$src1))),
5128 (i64 (A2_combinew (A2_tfrsi 0), (i32 IntRegs:$src1)))>,
5131 // Multiply 64-bit unsigned and use upper result.
5132 def : Pat <(mulhu (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
5147 (A2_combinew (A2_tfrsi 0),
5154 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
5156 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
5157 subreg_loreg)))), 32)),
5159 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
5160 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)))),
5161 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
5162 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg)))),
5163 32)), subreg_loreg)))),
5164 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
5165 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg))))>;
5167 // Multiply 64-bit signed and use upper result.
5168 def : Pat <(mulhs (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
5172 (A2_combinew (A2_tfrsi 0),
5182 (A2_combinew (A2_tfrsi 0),
5189 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
5191 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
5192 subreg_loreg)))), 32)),
5194 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
5195 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)))),
5196 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
5197 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg)))),
5198 32)), subreg_loreg)))),
5199 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
5200 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg))))>;
5202 // Hexagon specific ISD nodes.
5203 def SDTHexagonADJDYNALLOC : SDTypeProfile<1, 2,
5204 [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
5205 def Hexagon_ADJDYNALLOC : SDNode<"HexagonISD::ADJDYNALLOC",
5206 SDTHexagonADJDYNALLOC>;
5207 // Needed to tag these instructions for stack layout.
5208 let usesCustomInserter = 1, isAsmParserOnly = 1 in
5209 def ADJDYNALLOC : ALU32_ri<(outs IntRegs:$dst), (ins IntRegs:$src1,
5211 "$dst = add($src1, #$src2)",
5212 [(set (i32 IntRegs:$dst),
5213 (Hexagon_ADJDYNALLOC (i32 IntRegs:$src1),
5214 s16ImmPred:$src2))]>;
5216 def SDTHexagonARGEXTEND : SDTypeProfile<1, 1, [SDTCisVT<0, i32>]>;
5217 def Hexagon_ARGEXTEND : SDNode<"HexagonISD::ARGEXTEND", SDTHexagonARGEXTEND>;
5218 let isCodeGenOnly = 1 in
5219 def ARGEXTEND : ALU32_rr <(outs IntRegs:$dst), (ins IntRegs:$src1),
5221 [(set (i32 IntRegs:$dst),
5222 (Hexagon_ARGEXTEND (i32 IntRegs:$src1)))]>;
5224 let AddedComplexity = 100 in
5225 def : Pat<(i32 (sext_inreg (Hexagon_ARGEXTEND (i32 IntRegs:$src1)), i16)),
5226 (COPY (i32 IntRegs:$src1))>;
5228 def HexagonWrapperJT: SDNode<"HexagonISD::WrapperJT", SDTIntUnaryOp>;
5230 def : Pat<(HexagonWrapperJT tjumptable:$dst),
5231 (i32 (CONST32_set_jt tjumptable:$dst))>;
5235 //===----------------------------------------------------------------------===//
5237 // Shift by immediate/register and accumulate/logical
5238 //===----------------------------------------------------------------------===//
5240 // Rx[+-&|]=asr(Rs,#u5)
5241 // Rx[+-&|^]=lsr(Rs,#u5)
5242 // Rx[+-&|^]=asl(Rs,#u5)
5244 let hasNewValue = 1, opNewValue = 0 in
5245 class T_shift_imm_acc_r <string opc1, string opc2, SDNode OpNode1,
5246 SDNode OpNode2, bits<3> majOp, bits<2> minOp>
5247 : SInst_acc<(outs IntRegs:$Rx),
5248 (ins IntRegs:$src1, IntRegs:$Rs, u5Imm:$u5),
5249 "$Rx "#opc2#opc1#"($Rs, #$u5)",
5250 [(set (i32 IntRegs:$Rx),
5251 (OpNode2 (i32 IntRegs:$src1),
5252 (OpNode1 (i32 IntRegs:$Rs), u5ImmPred:$u5)))],
5253 "$src1 = $Rx", S_2op_tc_2_SLOT23> {
5258 let IClass = 0b1000;
5260 let Inst{27-24} = 0b1110;
5261 let Inst{23-22} = majOp{2-1};
5263 let Inst{7} = majOp{0};
5264 let Inst{6-5} = minOp;
5266 let Inst{20-16} = Rs;
5267 let Inst{12-8} = u5;
5270 // Rx[+-&|]=asr(Rs,Rt)
5271 // Rx[+-&|^]=lsr(Rs,Rt)
5272 // Rx[+-&|^]=asl(Rs,Rt)
5274 let hasNewValue = 1, opNewValue = 0 in
5275 class T_shift_reg_acc_r <string opc1, string opc2, SDNode OpNode1,
5276 SDNode OpNode2, bits<2> majOp, bits<2> minOp>
5277 : SInst_acc<(outs IntRegs:$Rx),
5278 (ins IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt),
5279 "$Rx "#opc2#opc1#"($Rs, $Rt)",
5280 [(set (i32 IntRegs:$Rx),
5281 (OpNode2 (i32 IntRegs:$src1),
5282 (OpNode1 (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))],
5283 "$src1 = $Rx", S_3op_tc_2_SLOT23 > {
5288 let IClass = 0b1100;
5290 let Inst{27-24} = 0b1100;
5291 let Inst{23-22} = majOp;
5292 let Inst{7-6} = minOp;
5294 let Inst{20-16} = Rs;
5295 let Inst{12-8} = Rt;
5298 // Rxx[+-&|]=asr(Rss,#u6)
5299 // Rxx[+-&|^]=lsr(Rss,#u6)
5300 // Rxx[+-&|^]=asl(Rss,#u6)
5302 class T_shift_imm_acc_p <string opc1, string opc2, SDNode OpNode1,
5303 SDNode OpNode2, bits<3> majOp, bits<2> minOp>
5304 : SInst_acc<(outs DoubleRegs:$Rxx),
5305 (ins DoubleRegs:$src1, DoubleRegs:$Rss, u6Imm:$u6),
5306 "$Rxx "#opc2#opc1#"($Rss, #$u6)",
5307 [(set (i64 DoubleRegs:$Rxx),
5308 (OpNode2 (i64 DoubleRegs:$src1),
5309 (OpNode1 (i64 DoubleRegs:$Rss), u6ImmPred:$u6)))],
5310 "$src1 = $Rxx", S_2op_tc_2_SLOT23> {
5315 let IClass = 0b1000;
5317 let Inst{27-24} = 0b0010;
5318 let Inst{23-22} = majOp{2-1};
5319 let Inst{7} = majOp{0};
5320 let Inst{6-5} = minOp;
5321 let Inst{4-0} = Rxx;
5322 let Inst{20-16} = Rss;
5323 let Inst{13-8} = u6;
5327 // Rxx[+-&|]=asr(Rss,Rt)
5328 // Rxx[+-&|^]=lsr(Rss,Rt)
5329 // Rxx[+-&|^]=asl(Rss,Rt)
5330 // Rxx[+-&|^]=lsl(Rss,Rt)
5332 class T_shift_reg_acc_p <string opc1, string opc2, SDNode OpNode1,
5333 SDNode OpNode2, bits<3> majOp, bits<2> minOp>
5334 : SInst_acc<(outs DoubleRegs:$Rxx),
5335 (ins DoubleRegs:$src1, DoubleRegs:$Rss, IntRegs:$Rt),
5336 "$Rxx "#opc2#opc1#"($Rss, $Rt)",
5337 [(set (i64 DoubleRegs:$Rxx),
5338 (OpNode2 (i64 DoubleRegs:$src1),
5339 (OpNode1 (i64 DoubleRegs:$Rss), (i32 IntRegs:$Rt))))],
5340 "$src1 = $Rxx", S_3op_tc_2_SLOT23> {
5345 let IClass = 0b1100;
5347 let Inst{27-24} = 0b1011;
5348 let Inst{23-21} = majOp;
5349 let Inst{20-16} = Rss;
5350 let Inst{12-8} = Rt;
5351 let Inst{7-6} = minOp;
5352 let Inst{4-0} = Rxx;
5355 //===----------------------------------------------------------------------===//
5356 // Multi-class for the shift instructions with logical/arithmetic operators.
5357 //===----------------------------------------------------------------------===//
5359 multiclass xtype_imm_base<string OpcStr1, string OpcStr2, SDNode OpNode1,
5360 SDNode OpNode2, bits<3> majOp, bits<2> minOp > {
5361 def _i_r#NAME : T_shift_imm_acc_r< OpcStr1, OpcStr2, OpNode1,
5362 OpNode2, majOp, minOp >;
5363 def _i_p#NAME : T_shift_imm_acc_p< OpcStr1, OpcStr2, OpNode1,
5364 OpNode2, majOp, minOp >;
5367 multiclass xtype_imm_acc<string opc1, SDNode OpNode, bits<2>minOp> {
5368 let AddedComplexity = 100 in
5369 defm _acc : xtype_imm_base< opc1, "+= ", OpNode, add, 0b001, minOp>;
5371 defm _nac : xtype_imm_base< opc1, "-= ", OpNode, sub, 0b000, minOp>;
5372 defm _and : xtype_imm_base< opc1, "&= ", OpNode, and, 0b010, minOp>;
5373 defm _or : xtype_imm_base< opc1, "|= ", OpNode, or, 0b011, minOp>;
5376 multiclass xtype_xor_imm_acc<string opc1, SDNode OpNode, bits<2>minOp> {
5377 let AddedComplexity = 100 in
5378 defm _xacc : xtype_imm_base< opc1, "^= ", OpNode, xor, 0b100, minOp>;
5381 defm S2_asr : xtype_imm_acc<"asr", sra, 0b00>;
5383 defm S2_lsr : xtype_imm_acc<"lsr", srl, 0b01>,
5384 xtype_xor_imm_acc<"lsr", srl, 0b01>;
5386 defm S2_asl : xtype_imm_acc<"asl", shl, 0b10>,
5387 xtype_xor_imm_acc<"asl", shl, 0b10>;
5389 multiclass xtype_reg_acc_r<string opc1, SDNode OpNode, bits<2>minOp> {
5390 let AddedComplexity = 100 in
5391 def _acc : T_shift_reg_acc_r <opc1, "+= ", OpNode, add, 0b11, minOp>;
5393 def _nac : T_shift_reg_acc_r <opc1, "-= ", OpNode, sub, 0b10, minOp>;
5394 def _and : T_shift_reg_acc_r <opc1, "&= ", OpNode, and, 0b01, minOp>;
5395 def _or : T_shift_reg_acc_r <opc1, "|= ", OpNode, or, 0b00, minOp>;
5398 multiclass xtype_reg_acc_p<string opc1, SDNode OpNode, bits<2>minOp> {
5399 let AddedComplexity = 100 in
5400 def _acc : T_shift_reg_acc_p <opc1, "+= ", OpNode, add, 0b110, minOp>;
5402 def _nac : T_shift_reg_acc_p <opc1, "-= ", OpNode, sub, 0b100, minOp>;
5403 def _and : T_shift_reg_acc_p <opc1, "&= ", OpNode, and, 0b010, minOp>;
5404 def _or : T_shift_reg_acc_p <opc1, "|= ", OpNode, or, 0b000, minOp>;
5405 def _xor : T_shift_reg_acc_p <opc1, "^= ", OpNode, xor, 0b011, minOp>;
5408 multiclass xtype_reg_acc<string OpcStr, SDNode OpNode, bits<2> minOp > {
5409 defm _r_r : xtype_reg_acc_r <OpcStr, OpNode, minOp>;
5410 defm _r_p : xtype_reg_acc_p <OpcStr, OpNode, minOp>;
5413 defm S2_asl : xtype_reg_acc<"asl", shl, 0b10>;
5414 defm S2_asr : xtype_reg_acc<"asr", sra, 0b00>;
5415 defm S2_lsr : xtype_reg_acc<"lsr", srl, 0b01>;
5416 defm S2_lsl : xtype_reg_acc<"lsl", shl, 0b11>;
5418 //===----------------------------------------------------------------------===//
5419 let hasSideEffects = 0 in
5420 class T_S3op_1 <string mnemonic, RegisterClass RC, bits<2> MajOp, bits<3> MinOp,
5421 bit SwapOps, bit isSat = 0, bit isRnd = 0, bit hasShift = 0>
5422 : SInst <(outs RC:$dst),
5423 (ins DoubleRegs:$src1, DoubleRegs:$src2),
5424 "$dst = "#mnemonic#"($src1, $src2)"#!if(isRnd, ":rnd", "")
5425 #!if(hasShift,":>>1","")
5426 #!if(isSat, ":sat", ""),
5427 [], "", S_3op_tc_2_SLOT23 > {
5432 let IClass = 0b1100;
5434 let Inst{27-24} = 0b0001;
5435 let Inst{23-22} = MajOp;
5436 let Inst{20-16} = !if (SwapOps, src2, src1);
5437 let Inst{12-8} = !if (SwapOps, src1, src2);
5438 let Inst{7-5} = MinOp;
5439 let Inst{4-0} = dst;
5442 class T_S3op_64 <string mnemonic, bits<2> MajOp, bits<3> MinOp, bit SwapOps,
5443 bit isSat = 0, bit isRnd = 0, bit hasShift = 0 >
5444 : T_S3op_1 <mnemonic, DoubleRegs, MajOp, MinOp, SwapOps,
5445 isSat, isRnd, hasShift>;
5447 let Itinerary = S_3op_tc_1_SLOT23 in {
5448 def S2_shuffeb : T_S3op_64 < "shuffeb", 0b00, 0b010, 0>;
5449 def S2_shuffeh : T_S3op_64 < "shuffeh", 0b00, 0b110, 0>;
5450 def S2_shuffob : T_S3op_64 < "shuffob", 0b00, 0b100, 1>;
5451 def S2_shuffoh : T_S3op_64 < "shuffoh", 0b10, 0b000, 1>;
5453 def S2_vtrunewh : T_S3op_64 < "vtrunewh", 0b10, 0b010, 0>;
5454 def S2_vtrunowh : T_S3op_64 < "vtrunowh", 0b10, 0b100, 0>;
5457 def S2_lfsp : T_S3op_64 < "lfs", 0b10, 0b110, 0>;
5459 let hasSideEffects = 0 in
5460 class T_S3op_2 <string mnemonic, bits<3> MajOp, bit SwapOps>
5461 : SInst < (outs DoubleRegs:$Rdd),
5462 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt, PredRegs:$Pu),
5463 "$Rdd = "#mnemonic#"($Rss, $Rtt, $Pu)",
5464 [], "", S_3op_tc_1_SLOT23 > {
5470 let IClass = 0b1100;
5472 let Inst{27-24} = 0b0010;
5473 let Inst{23-21} = MajOp;
5474 let Inst{20-16} = !if (SwapOps, Rtt, Rss);
5475 let Inst{12-8} = !if (SwapOps, Rss, Rtt);
5477 let Inst{4-0} = Rdd;
5480 def S2_valignrb : T_S3op_2 < "valignb", 0b000, 1>;
5481 def S2_vsplicerb : T_S3op_2 < "vspliceb", 0b100, 0>;
5483 //===----------------------------------------------------------------------===//
5484 // Template class used by vector shift, vector rotate, vector neg,
5485 // 32-bit shift, 64-bit shifts, etc.
5486 //===----------------------------------------------------------------------===//
5488 let hasSideEffects = 0 in
5489 class T_S3op_3 <string mnemonic, RegisterClass RC, bits<2> MajOp,
5490 bits<2> MinOp, bit isSat = 0, list<dag> pattern = [] >
5491 : SInst <(outs RC:$dst),
5492 (ins RC:$src1, IntRegs:$src2),
5493 "$dst = "#mnemonic#"($src1, $src2)"#!if(isSat, ":sat", ""),
5494 pattern, "", S_3op_tc_1_SLOT23> {
5499 let IClass = 0b1100;
5501 let Inst{27-24} = !if(!eq(!cast<string>(RC), "IntRegs"), 0b0110, 0b0011);
5502 let Inst{23-22} = MajOp;
5503 let Inst{20-16} = src1;
5504 let Inst{12-8} = src2;
5505 let Inst{7-6} = MinOp;
5506 let Inst{4-0} = dst;
5509 let hasNewValue = 1 in
5510 class T_S3op_shift32 <string mnemonic, SDNode OpNode, bits<2> MinOp>
5511 : T_S3op_3 <mnemonic, IntRegs, 0b01, MinOp, 0,
5512 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$src1),
5513 (i32 IntRegs:$src2)))]>;
5515 let hasNewValue = 1, Itinerary = S_3op_tc_2_SLOT23 in
5516 class T_S3op_shift32_Sat <string mnemonic, bits<2> MinOp>
5517 : T_S3op_3 <mnemonic, IntRegs, 0b00, MinOp, 1, []>;
5520 class T_S3op_shift64 <string mnemonic, SDNode OpNode, bits<2> MinOp>
5521 : T_S3op_3 <mnemonic, DoubleRegs, 0b10, MinOp, 0,
5522 [(set (i64 DoubleRegs:$dst), (OpNode (i64 DoubleRegs:$src1),
5523 (i32 IntRegs:$src2)))]>;
5526 class T_S3op_shiftVect <string mnemonic, bits<2> MajOp, bits<2> MinOp>
5527 : T_S3op_3 <mnemonic, DoubleRegs, MajOp, MinOp, 0, []>;
5530 // Shift by register
5531 // Rdd=[asr|lsr|asl|lsl](Rss,Rt)
5533 def S2_asr_r_p : T_S3op_shift64 < "asr", sra, 0b00>;
5534 def S2_lsr_r_p : T_S3op_shift64 < "lsr", srl, 0b01>;
5535 def S2_asl_r_p : T_S3op_shift64 < "asl", shl, 0b10>;
5536 def S2_lsl_r_p : T_S3op_shift64 < "lsl", shl, 0b11>;
5538 // Rd=[asr|lsr|asl|lsl](Rs,Rt)
5540 def S2_asr_r_r : T_S3op_shift32<"asr", sra, 0b00>;
5541 def S2_lsr_r_r : T_S3op_shift32<"lsr", srl, 0b01>;
5542 def S2_asl_r_r : T_S3op_shift32<"asl", shl, 0b10>;
5543 def S2_lsl_r_r : T_S3op_shift32<"lsl", shl, 0b11>;
5545 // Shift by register with saturation
5546 // Rd=asr(Rs,Rt):sat
5547 // Rd=asl(Rs,Rt):sat
5549 let Defs = [USR_OVF] in {
5550 def S2_asr_r_r_sat : T_S3op_shift32_Sat<"asr", 0b00>;
5551 def S2_asl_r_r_sat : T_S3op_shift32_Sat<"asl", 0b10>;
5554 let hasNewValue = 1, hasSideEffects = 0 in
5555 class T_S3op_8 <string opc, bits<3> MinOp, bit isSat, bit isRnd, bit hasShift, bit hasSplat = 0>
5556 : SInst < (outs IntRegs:$Rd),
5557 (ins DoubleRegs:$Rss, IntRegs:$Rt),
5558 "$Rd = "#opc#"($Rss, $Rt"#!if(hasSplat, "*", "")#")"
5559 #!if(hasShift, ":<<1", "")
5560 #!if(isRnd, ":rnd", "")
5561 #!if(isSat, ":sat", ""),
5562 [], "", S_3op_tc_1_SLOT23 > {
5567 let IClass = 0b1100;
5569 let Inst{27-24} = 0b0101;
5570 let Inst{20-16} = Rss;
5571 let Inst{12-8} = Rt;
5572 let Inst{7-5} = MinOp;
5576 def S2_asr_r_svw_trun : T_S3op_8<"vasrw", 0b010, 0, 0, 0>;
5578 let Defs = [USR_OVF], Itinerary = S_3op_tc_2_SLOT23 in
5579 def S2_vcrotate : T_S3op_shiftVect < "vcrotate", 0b11, 0b00>;
5581 let hasSideEffects = 0 in
5582 class T_S3op_7 <string mnemonic, bit MajOp >
5583 : SInst <(outs DoubleRegs:$Rdd),
5584 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt, u3Imm:$u3),
5585 "$Rdd = "#mnemonic#"($Rss, $Rtt, #$u3)" ,
5586 [], "", S_3op_tc_1_SLOT23 > {
5592 let IClass = 0b1100;
5594 let Inst{27-24} = 0b0000;
5595 let Inst{23} = MajOp;
5596 let Inst{20-16} = !if(MajOp, Rss, Rtt);
5597 let Inst{12-8} = !if(MajOp, Rtt, Rss);
5599 let Inst{4-0} = Rdd;
5602 def S2_valignib : T_S3op_7 < "valignb", 0>;
5603 def S2_vspliceib : T_S3op_7 < "vspliceb", 1>;
5605 //===----------------------------------------------------------------------===//
5606 // Template class for 'insert bitfield' instructions
5607 //===----------------------------------------------------------------------===//
5608 let hasSideEffects = 0 in
5609 class T_S3op_insert <string mnemonic, RegisterClass RC>
5610 : SInst <(outs RC:$dst),
5611 (ins RC:$src1, RC:$src2, DoubleRegs:$src3),
5612 "$dst = "#mnemonic#"($src2, $src3)" ,
5613 [], "$src1 = $dst", S_3op_tc_1_SLOT23 > {
5618 let IClass = 0b1100;
5620 let Inst{27-26} = 0b10;
5621 let Inst{25-24} = !if(!eq(!cast<string>(RC), "IntRegs"), 0b00, 0b10);
5623 let Inst{20-16} = src2;
5624 let Inst{12-8} = src3;
5625 let Inst{4-0} = dst;
5628 let hasSideEffects = 0 in
5629 class T_S2op_insert <bits<4> RegTyBits, RegisterClass RC, Operand ImmOp>
5630 : SInst <(outs RC:$dst), (ins RC:$dst2, RC:$src1, ImmOp:$src2, ImmOp:$src3),
5631 "$dst = insert($src1, #$src2, #$src3)",
5632 [], "$dst2 = $dst", S_2op_tc_2_SLOT23> {
5639 string ImmOpStr = !cast<string>(ImmOp);
5641 let bit23 = !if (!eq(ImmOpStr, "u6Imm"), src3{5}, 0);
5642 let bit13 = !if (!eq(ImmOpStr, "u6Imm"), src2{5}, 0);
5644 let IClass = 0b1000;
5646 let Inst{27-24} = RegTyBits;
5647 let Inst{23} = bit23;
5648 let Inst{22-21} = src3{4-3};
5649 let Inst{20-16} = src1;
5650 let Inst{13} = bit13;
5651 let Inst{12-8} = src2{4-0};
5652 let Inst{7-5} = src3{2-0};
5653 let Inst{4-0} = dst;
5656 // Rx=insert(Rs,Rtt)
5657 // Rx=insert(Rs,#u5,#U5)
5658 let hasNewValue = 1 in {
5659 def S2_insert_rp : T_S3op_insert <"insert", IntRegs>;
5660 def S2_insert : T_S2op_insert <0b1111, IntRegs, u5Imm>;
5663 // Rxx=insert(Rss,Rtt)
5664 // Rxx=insert(Rss,#u6,#U6)
5665 def S2_insertp_rp : T_S3op_insert<"insert", DoubleRegs>;
5666 def S2_insertp : T_S2op_insert <0b0011, DoubleRegs, u6Imm>;
5668 //===----------------------------------------------------------------------===//
5669 // Template class for 'extract bitfield' instructions
5670 //===----------------------------------------------------------------------===//
5671 let hasNewValue = 1, hasSideEffects = 0 in
5672 class T_S3op_extract <string mnemonic, bits<2> MinOp>
5673 : SInst <(outs IntRegs:$Rd), (ins IntRegs:$Rs, DoubleRegs:$Rtt),
5674 "$Rd = "#mnemonic#"($Rs, $Rtt)",
5675 [], "", S_3op_tc_2_SLOT23 > {
5680 let IClass = 0b1100;
5682 let Inst{27-22} = 0b100100;
5683 let Inst{20-16} = Rs;
5684 let Inst{12-8} = Rtt;
5685 let Inst{7-6} = MinOp;
5689 let hasSideEffects = 0 in
5690 class T_S2op_extract <string mnemonic, bits<4> RegTyBits,
5691 RegisterClass RC, Operand ImmOp>
5692 : SInst <(outs RC:$dst), (ins RC:$src1, ImmOp:$src2, ImmOp:$src3),
5693 "$dst = "#mnemonic#"($src1, #$src2, #$src3)",
5694 [], "", S_2op_tc_2_SLOT23> {
5701 string ImmOpStr = !cast<string>(ImmOp);
5703 let bit23 = !if (!eq(ImmOpStr, "u6Imm"), src3{5},
5704 !if (!eq(mnemonic, "extractu"), 0, 1));
5706 let bit13 = !if (!eq(ImmOpStr, "u6Imm"), src2{5}, 0);
5708 let IClass = 0b1000;
5710 let Inst{27-24} = RegTyBits;
5711 let Inst{23} = bit23;
5712 let Inst{22-21} = src3{4-3};
5713 let Inst{20-16} = src1;
5714 let Inst{13} = bit13;
5715 let Inst{12-8} = src2{4-0};
5716 let Inst{7-5} = src3{2-0};
5717 let Inst{4-0} = dst;
5722 // Rdd=extractu(Rss,Rtt)
5723 // Rdd=extractu(Rss,#u6,#U6)
5724 def S2_extractup_rp : T_S3op_64 < "extractu", 0b00, 0b000, 0>;
5725 def S2_extractup : T_S2op_extract <"extractu", 0b0001, DoubleRegs, u6Imm>;
5727 // Rd=extractu(Rs,Rtt)
5728 // Rd=extractu(Rs,#u5,#U5)
5729 let hasNewValue = 1 in {
5730 def S2_extractu_rp : T_S3op_extract<"extractu", 0b00>;
5731 def S2_extractu : T_S2op_extract <"extractu", 0b1101, IntRegs, u5Imm>;
5734 //===----------------------------------------------------------------------===//
5735 // :raw for of tableindx[bdhw] insns
5736 //===----------------------------------------------------------------------===//
5738 let hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
5739 class tableidxRaw<string OpStr, bits<2>MinOp>
5740 : SInst <(outs IntRegs:$Rx),
5741 (ins IntRegs:$_dst_, IntRegs:$Rs, u4Imm:$u4, s6Imm:$S6),
5742 "$Rx = "#OpStr#"($Rs, #$u4, #$S6):raw",
5743 [], "$Rx = $_dst_" > {
5749 let IClass = 0b1000;
5751 let Inst{27-24} = 0b0111;
5752 let Inst{23-22} = MinOp;
5753 let Inst{21} = u4{3};
5754 let Inst{20-16} = Rs;
5755 let Inst{13-8} = S6;
5756 let Inst{7-5} = u4{2-0};
5760 def S2_tableidxb : tableidxRaw<"tableidxb", 0b00>;
5761 def S2_tableidxh : tableidxRaw<"tableidxh", 0b01>;
5762 def S2_tableidxw : tableidxRaw<"tableidxw", 0b10>;
5763 def S2_tableidxd : tableidxRaw<"tableidxd", 0b11>;
5765 // Change the sign of the immediate for Rd=-mpyi(Rs,#u8)
5766 def : Pat <(mul (i32 IntRegs:$src1), (ineg n8ImmPred:$src2)),
5767 (i32 (M2_mpysin (i32 IntRegs:$src1), u8ImmPred:$src2))>;
5769 //===----------------------------------------------------------------------===//
5770 // V3 Instructions +
5771 //===----------------------------------------------------------------------===//
5773 include "HexagonInstrInfoV3.td"
5775 //===----------------------------------------------------------------------===//
5776 // V3 Instructions -
5777 //===----------------------------------------------------------------------===//
5779 //===----------------------------------------------------------------------===//
5780 // V4 Instructions +
5781 //===----------------------------------------------------------------------===//
5783 include "HexagonInstrInfoV4.td"
5785 //===----------------------------------------------------------------------===//
5786 // V4 Instructions -
5787 //===----------------------------------------------------------------------===//
5789 //===----------------------------------------------------------------------===//
5790 // V5 Instructions +
5791 //===----------------------------------------------------------------------===//
5793 include "HexagonInstrInfoV5.td"
5795 //===----------------------------------------------------------------------===//
5796 // V5 Instructions -
5797 //===----------------------------------------------------------------------===//
5799 //===----------------------------------------------------------------------===//
5800 // ALU32/64/Vector +
5801 //===----------------------------------------------------------------------===///
5803 include "HexagonInstrInfoVector.td"