1 //===- HexagonInstrInfo.h - Hexagon Instruction Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Hexagon implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef HexagonINSTRUCTIONINFO_H
15 #define HexagonINSTRUCTIONINFO_H
17 #include "HexagonRegisterInfo.h"
18 #include "MCTargetDesc/HexagonBaseInfo.h"
19 #include "llvm/Target/TargetInstrInfo.h"
20 #include "llvm/Target/TargetFrameLowering.h"
21 #include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
23 #define GET_INSTRINFO_HEADER
24 #include "HexagonGenInstrInfo.inc"
28 class HexagonInstrInfo : public HexagonGenInstrInfo {
29 const HexagonRegisterInfo RI;
30 const HexagonSubtarget &Subtarget;
31 typedef unsigned Opcode_t;
33 virtual void anchor();
36 explicit HexagonInstrInfo(HexagonSubtarget &ST);
38 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
39 /// such, whenever a client has an instance of instruction info, it should
40 /// always be able to get register info as well (through this method).
42 virtual const HexagonRegisterInfo &getRegisterInfo() const { return RI; }
44 /// isLoadFromStackSlot - If the specified machine instruction is a direct
45 /// load from a stack slot, return the virtual or physical register number of
46 /// the destination along with the FrameIndex of the loaded stack slot. If
47 /// not, return 0. This predicate must return 0 if the instruction has
48 /// any side effects other than loading from the stack slot.
49 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
50 int &FrameIndex) const;
52 /// isStoreToStackSlot - If the specified machine instruction is a direct
53 /// store to a stack slot, return the virtual or physical register number of
54 /// the source reg along with the FrameIndex of the loaded stack slot. If
55 /// not, return 0. This predicate must return 0 if the instruction has
56 /// any side effects other than storing to the stack slot.
57 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
58 int &FrameIndex) const;
61 virtual bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
62 MachineBasicBlock *&FBB,
63 SmallVectorImpl<MachineOperand> &Cond,
64 bool AllowModify) const;
66 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
68 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
69 MachineBasicBlock *FBB,
70 const SmallVectorImpl<MachineOperand> &Cond,
73 virtual bool analyzeCompare(const MachineInstr *MI,
74 unsigned &SrcReg, unsigned &SrcReg2,
75 int &Mask, int &Value) const;
77 virtual void copyPhysReg(MachineBasicBlock &MBB,
78 MachineBasicBlock::iterator I, DebugLoc DL,
79 unsigned DestReg, unsigned SrcReg,
82 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
83 MachineBasicBlock::iterator MBBI,
84 unsigned SrcReg, bool isKill, int FrameIndex,
85 const TargetRegisterClass *RC,
86 const TargetRegisterInfo *TRI) const;
88 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
89 SmallVectorImpl<MachineOperand> &Addr,
90 const TargetRegisterClass *RC,
91 SmallVectorImpl<MachineInstr*> &NewMIs) const;
93 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
94 MachineBasicBlock::iterator MBBI,
95 unsigned DestReg, int FrameIndex,
96 const TargetRegisterClass *RC,
97 const TargetRegisterInfo *TRI) const;
99 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
100 SmallVectorImpl<MachineOperand> &Addr,
101 const TargetRegisterClass *RC,
102 SmallVectorImpl<MachineInstr*> &NewMIs) const;
104 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
106 const SmallVectorImpl<unsigned> &Ops,
107 int FrameIndex) const;
109 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
111 const SmallVectorImpl<unsigned> &Ops,
112 MachineInstr* LoadMI) const {
116 unsigned createVR(MachineFunction* MF, MVT VT) const;
118 virtual bool isBranch(const MachineInstr *MI) const;
119 virtual bool isPredicable(MachineInstr *MI) const;
121 PredicateInstruction(MachineInstr *MI,
122 const SmallVectorImpl<MachineOperand> &Cond) const;
124 virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
125 unsigned ExtraPredCycles,
126 const BranchProbability &Probability) const;
128 virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
129 unsigned NumTCycles, unsigned ExtraTCycles,
130 MachineBasicBlock &FMBB,
131 unsigned NumFCycles, unsigned ExtraFCycles,
132 const BranchProbability &Probability) const;
134 virtual bool isPredicated(const MachineInstr *MI) const;
135 virtual bool isPredicated(unsigned Opcode) const;
136 virtual bool isPredicatedTrue(const MachineInstr *MI) const;
137 virtual bool isPredicatedTrue(unsigned Opcode) const;
138 virtual bool isPredicatedNew(const MachineInstr *MI) const;
139 virtual bool isPredicatedNew(unsigned Opcode) const;
140 virtual bool DefinesPredicate(MachineInstr *MI,
141 std::vector<MachineOperand> &Pred) const;
143 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
144 const SmallVectorImpl<MachineOperand> &Pred2) const;
147 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
150 isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumCycles,
151 const BranchProbability &Probability) const;
153 virtual DFAPacketizer*
154 CreateTargetScheduleState(const TargetMachine *TM,
155 const ScheduleDAG *DAG) const;
157 virtual bool isSchedulingBoundary(const MachineInstr *MI,
158 const MachineBasicBlock *MBB,
159 const MachineFunction &MF) const;
160 bool isValidOffset(const int Opcode, const int Offset) const;
161 bool isValidAutoIncImm(const EVT VT, const int Offset) const;
162 bool isMemOp(const MachineInstr *MI) const;
163 bool isSpillPredRegOp(const MachineInstr *MI) const;
164 bool isU6_3Immediate(const int value) const;
165 bool isU6_2Immediate(const int value) const;
166 bool isU6_1Immediate(const int value) const;
167 bool isU6_0Immediate(const int value) const;
168 bool isS4_3Immediate(const int value) const;
169 bool isS4_2Immediate(const int value) const;
170 bool isS4_1Immediate(const int value) const;
171 bool isS4_0Immediate(const int value) const;
172 bool isS12_Immediate(const int value) const;
173 bool isU6_Immediate(const int value) const;
174 bool isS8_Immediate(const int value) const;
175 bool isS6_Immediate(const int value) const;
177 bool isSaveCalleeSavedRegsCall(const MachineInstr* MI) const;
178 bool isConditionalTransfer(const MachineInstr* MI) const;
179 bool isConditionalALU32 (const MachineInstr* MI) const;
180 bool isConditionalLoad (const MachineInstr* MI) const;
181 bool isConditionalStore(const MachineInstr* MI) const;
182 bool isNewValueInst(const MachineInstr* MI) const;
183 bool isNewValue(const MachineInstr* MI) const;
184 bool isDotNewInst(const MachineInstr* MI) const;
185 int GetDotOldOp(const int opc) const;
186 int GetDotNewOp(const MachineInstr* MI) const;
187 int GetDotNewPredOp(MachineInstr *MI,
188 const MachineBranchProbabilityInfo
190 bool mayBeNewStore(const MachineInstr* MI) const;
191 bool isDeallocRet(const MachineInstr *MI) const;
192 unsigned getInvertedPredicatedOpcode(const int Opc) const;
193 bool isExtendable(const MachineInstr* MI) const;
194 bool isExtended(const MachineInstr* MI) const;
195 bool isPostIncrement(const MachineInstr* MI) const;
196 bool isNewValueStore(const MachineInstr* MI) const;
197 bool isNewValueStore(unsigned Opcode) const;
198 bool isNewValueJump(const MachineInstr* MI) const;
199 bool isNewValueJumpCandidate(const MachineInstr *MI) const;
202 void immediateExtend(MachineInstr *MI) const;
203 bool isConstExtended(MachineInstr *MI) const;
204 int getDotNewPredJumpOp(MachineInstr *MI,
205 const MachineBranchProbabilityInfo *MBPI) const;
206 unsigned getAddrMode(const MachineInstr* MI) const;
207 bool isOperandExtended(const MachineInstr *MI,
208 unsigned short OperandNum) const;
209 unsigned short getCExtOpNum(const MachineInstr *MI) const;
210 int getMinValue(const MachineInstr *MI) const;
211 int getMaxValue(const MachineInstr *MI) const;
212 bool NonExtEquivalentExists (const MachineInstr *MI) const;
213 short getNonExtOpcode(const MachineInstr *MI) const;
214 bool PredOpcodeHasJMP_c(Opcode_t Opcode) const;
215 bool PredOpcodeHasNot(Opcode_t Opcode) const;
218 int getMatchingCondBranchOpcode(int Opc, bool sense) const;