1 //===-- HexagonInstrInfo.cpp - Hexagon Instruction Information ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Hexagon implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "HexagonInstrInfo.h"
15 #include "HexagonRegisterInfo.h"
16 #include "HexagonSubtarget.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/CodeGen/DFAPacketizer.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineMemOperand.h"
25 #include "llvm/CodeGen/PseudoSourceValue.h"
26 #include "llvm/Support/MathExtras.h"
27 #define GET_INSTRINFO_CTOR
28 #include "HexagonGenInstrInfo.inc"
29 #include "HexagonGenDFAPacketizer.inc"
34 /// Constants for Hexagon instructions.
36 const int Hexagon_MEMW_OFFSET_MAX = 4095;
37 const int Hexagon_MEMW_OFFSET_MIN = -4096;
38 const int Hexagon_MEMD_OFFSET_MAX = 8191;
39 const int Hexagon_MEMD_OFFSET_MIN = -8192;
40 const int Hexagon_MEMH_OFFSET_MAX = 2047;
41 const int Hexagon_MEMH_OFFSET_MIN = -2048;
42 const int Hexagon_MEMB_OFFSET_MAX = 1023;
43 const int Hexagon_MEMB_OFFSET_MIN = -1024;
44 const int Hexagon_ADDI_OFFSET_MAX = 32767;
45 const int Hexagon_ADDI_OFFSET_MIN = -32768;
46 const int Hexagon_MEMD_AUTOINC_MAX = 56;
47 const int Hexagon_MEMD_AUTOINC_MIN = -64;
48 const int Hexagon_MEMW_AUTOINC_MAX = 28;
49 const int Hexagon_MEMW_AUTOINC_MIN = -32;
50 const int Hexagon_MEMH_AUTOINC_MAX = 14;
51 const int Hexagon_MEMH_AUTOINC_MIN = -16;
52 const int Hexagon_MEMB_AUTOINC_MAX = 7;
53 const int Hexagon_MEMB_AUTOINC_MIN = -8;
57 HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST)
58 : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
59 RI(ST, *this), Subtarget(ST) {
63 /// isLoadFromStackSlot - If the specified machine instruction is a direct
64 /// load from a stack slot, return the virtual or physical register number of
65 /// the destination along with the FrameIndex of the loaded stack slot. If
66 /// not, return 0. This predicate must return 0 if the instruction has
67 /// any side effects other than loading from the stack slot.
68 unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
69 int &FrameIndex) const {
72 switch (MI->getOpcode()) {
79 if (MI->getOperand(2).isFI() &&
80 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
81 FrameIndex = MI->getOperand(2).getIndex();
82 return MI->getOperand(0).getReg();
90 /// isStoreToStackSlot - If the specified machine instruction is a direct
91 /// store to a stack slot, return the virtual or physical register number of
92 /// the source reg along with the FrameIndex of the loaded stack slot. If
93 /// not, return 0. This predicate must return 0 if the instruction has
94 /// any side effects other than storing to the stack slot.
95 unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
96 int &FrameIndex) const {
97 switch (MI->getOpcode()) {
103 if (MI->getOperand(2).isFI() &&
104 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
105 FrameIndex = MI->getOperand(2).getIndex();
106 return MI->getOperand(0).getReg();
115 HexagonInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
116 MachineBasicBlock *FBB,
117 const SmallVectorImpl<MachineOperand> &Cond,
120 int BOpc = Hexagon::JMP;
121 int BccOpc = Hexagon::JMP_c;
123 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
126 // Check if ReverseBranchCondition has asked to reverse this branch
127 // If we want to reverse the branch an odd number of times, we want
129 if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) {
130 BccOpc = Hexagon::JMP_cNot;
136 // Due to a bug in TailMerging/CFG Optimization, we need to add a
137 // special case handling of a predicated jump followed by an
138 // unconditional jump. If not, Tail Merging and CFG Optimization go
139 // into an infinite loop.
140 MachineBasicBlock *NewTBB, *NewFBB;
141 SmallVector<MachineOperand, 4> Cond;
142 MachineInstr *Term = MBB.getFirstTerminator();
143 if (isPredicated(Term) && !AnalyzeBranch(MBB, NewTBB, NewFBB, Cond,
145 MachineBasicBlock *NextBB =
146 llvm::next(MachineFunction::iterator(&MBB));
147 if (NewTBB == NextBB) {
148 ReverseBranchCondition(Cond);
150 return InsertBranch(MBB, TBB, 0, Cond, DL);
153 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
156 get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
161 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
162 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
168 bool HexagonInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
169 MachineBasicBlock *&TBB,
170 MachineBasicBlock *&FBB,
171 SmallVectorImpl<MachineOperand> &Cond,
172 bool AllowModify) const {
175 // If the block has no terminators, it just falls into the block after it.
176 MachineBasicBlock::iterator I = MBB.end();
177 if (I == MBB.begin())
180 // A basic block may looks like this:
190 // It has two succs but does not have a terminator
191 // Don't know how to handle it.
196 } while (I != MBB.begin());
201 while (I->isDebugValue()) {
202 if (I == MBB.begin())
206 if (!isUnpredicatedTerminator(I))
209 // Get the last instruction in the block.
210 MachineInstr *LastInst = I;
212 // If there is only one terminator instruction, process it.
213 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
214 if (LastInst->getOpcode() == Hexagon::JMP) {
215 TBB = LastInst->getOperand(0).getMBB();
218 if (LastInst->getOpcode() == Hexagon::JMP_c) {
219 // Block ends with fall-through true condbranch.
220 TBB = LastInst->getOperand(1).getMBB();
221 Cond.push_back(LastInst->getOperand(0));
224 if (LastInst->getOpcode() == Hexagon::JMP_cNot) {
225 // Block ends with fall-through false condbranch.
226 TBB = LastInst->getOperand(1).getMBB();
227 Cond.push_back(MachineOperand::CreateImm(0));
228 Cond.push_back(LastInst->getOperand(0));
231 // Otherwise, don't know what this is.
235 // Get the instruction before it if it's a terminator.
236 MachineInstr *SecondLastInst = I;
238 // If there are three terminators, we don't know what sort of block this is.
239 if (SecondLastInst && I != MBB.begin() &&
240 isUnpredicatedTerminator(--I))
243 // If the block ends with Hexagon::BRCOND and Hexagon:JMP, handle it.
244 if (((SecondLastInst->getOpcode() == Hexagon::BRCOND) ||
245 (SecondLastInst->getOpcode() == Hexagon::JMP_c)) &&
246 LastInst->getOpcode() == Hexagon::JMP) {
247 TBB = SecondLastInst->getOperand(1).getMBB();
248 Cond.push_back(SecondLastInst->getOperand(0));
249 FBB = LastInst->getOperand(0).getMBB();
253 // If the block ends with Hexagon::JMP_cNot and Hexagon:JMP, handle it.
254 if ((SecondLastInst->getOpcode() == Hexagon::JMP_cNot) &&
255 LastInst->getOpcode() == Hexagon::JMP) {
256 TBB = SecondLastInst->getOperand(1).getMBB();
257 Cond.push_back(MachineOperand::CreateImm(0));
258 Cond.push_back(SecondLastInst->getOperand(0));
259 FBB = LastInst->getOperand(0).getMBB();
263 // If the block ends with two Hexagon:JMPs, handle it. The second one is not
264 // executed, so remove it.
265 if (SecondLastInst->getOpcode() == Hexagon::JMP &&
266 LastInst->getOpcode() == Hexagon::JMP) {
267 TBB = SecondLastInst->getOperand(0).getMBB();
270 I->eraseFromParent();
274 // Otherwise, can't handle this.
279 unsigned HexagonInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
280 int BOpc = Hexagon::JMP;
281 int BccOpc = Hexagon::JMP_c;
282 int BccOpcNot = Hexagon::JMP_cNot;
284 MachineBasicBlock::iterator I = MBB.end();
285 if (I == MBB.begin()) return 0;
287 if (I->getOpcode() != BOpc && I->getOpcode() != BccOpc &&
288 I->getOpcode() != BccOpcNot)
291 // Remove the branch.
292 I->eraseFromParent();
296 if (I == MBB.begin()) return 1;
298 if (I->getOpcode() != BccOpc && I->getOpcode() != BccOpcNot)
301 // Remove the branch.
302 I->eraseFromParent();
307 void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
308 MachineBasicBlock::iterator I, DebugLoc DL,
309 unsigned DestReg, unsigned SrcReg,
310 bool KillSrc) const {
311 if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
312 BuildMI(MBB, I, DL, get(Hexagon::TFR), DestReg).addReg(SrcReg);
315 if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
316 BuildMI(MBB, I, DL, get(Hexagon::TFR_64), DestReg).addReg(SrcReg);
319 if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
320 // Map Pd = Ps to Pd = or(Ps, Ps).
321 BuildMI(MBB, I, DL, get(Hexagon::OR_pp),
322 DestReg).addReg(SrcReg).addReg(SrcReg);
325 if (Hexagon::DoubleRegsRegClass.contains(DestReg, SrcReg)) {
326 // We can have an overlap between single and double reg: r1:0 = r0.
327 if(SrcReg == RI.getSubReg(DestReg, Hexagon::subreg_loreg)) {
329 BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg,
330 Hexagon::subreg_hireg))).addImm(0);
332 // r1:0 = r1 or no overlap.
333 BuildMI(MBB, I, DL, get(Hexagon::TFR), (RI.getSubReg(DestReg,
334 Hexagon::subreg_loreg))).addReg(SrcReg);
335 BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg,
336 Hexagon::subreg_hireg))).addImm(0);
340 if (Hexagon::CRRegsRegClass.contains(DestReg, SrcReg)) {
341 BuildMI(MBB, I, DL, get(Hexagon::TFCR), DestReg).addReg(SrcReg);
345 llvm_unreachable("Unimplemented");
349 void HexagonInstrInfo::
350 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
351 unsigned SrcReg, bool isKill, int FI,
352 const TargetRegisterClass *RC,
353 const TargetRegisterInfo *TRI) const {
355 DebugLoc DL = MBB.findDebugLoc(I);
356 MachineFunction &MF = *MBB.getParent();
357 MachineFrameInfo &MFI = *MF.getFrameInfo();
358 unsigned Align = MFI.getObjectAlignment(FI);
360 MachineMemOperand *MMO =
361 MF.getMachineMemOperand(
362 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
363 MachineMemOperand::MOStore,
364 MFI.getObjectSize(FI),
367 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
368 BuildMI(MBB, I, DL, get(Hexagon::STriw))
369 .addFrameIndex(FI).addImm(0)
370 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
371 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
372 BuildMI(MBB, I, DL, get(Hexagon::STrid))
373 .addFrameIndex(FI).addImm(0)
374 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
375 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
376 BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
377 .addFrameIndex(FI).addImm(0)
378 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
380 llvm_unreachable("Unimplemented");
385 void HexagonInstrInfo::storeRegToAddr(
386 MachineFunction &MF, unsigned SrcReg,
388 SmallVectorImpl<MachineOperand> &Addr,
389 const TargetRegisterClass *RC,
390 SmallVectorImpl<MachineInstr*> &NewMIs) const
392 llvm_unreachable("Unimplemented");
396 void HexagonInstrInfo::
397 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
398 unsigned DestReg, int FI,
399 const TargetRegisterClass *RC,
400 const TargetRegisterInfo *TRI) const {
401 DebugLoc DL = MBB.findDebugLoc(I);
402 MachineFunction &MF = *MBB.getParent();
403 MachineFrameInfo &MFI = *MF.getFrameInfo();
404 unsigned Align = MFI.getObjectAlignment(FI);
406 MachineMemOperand *MMO =
407 MF.getMachineMemOperand(
408 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
409 MachineMemOperand::MOLoad,
410 MFI.getObjectSize(FI),
412 if (RC == &Hexagon::IntRegsRegClass) {
413 BuildMI(MBB, I, DL, get(Hexagon::LDriw), DestReg)
414 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
415 } else if (RC == &Hexagon::DoubleRegsRegClass) {
416 BuildMI(MBB, I, DL, get(Hexagon::LDrid), DestReg)
417 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
418 } else if (RC == &Hexagon::PredRegsRegClass) {
419 BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
420 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
422 llvm_unreachable("Can't store this register to stack slot");
427 void HexagonInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
428 SmallVectorImpl<MachineOperand> &Addr,
429 const TargetRegisterClass *RC,
430 SmallVectorImpl<MachineInstr*> &NewMIs) const {
431 llvm_unreachable("Unimplemented");
435 MachineInstr *HexagonInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
437 const SmallVectorImpl<unsigned> &Ops,
439 // Hexagon_TODO: Implement.
444 unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const {
446 MachineRegisterInfo &RegInfo = MF->getRegInfo();
447 const TargetRegisterClass *TRC;
449 TRC = &Hexagon::PredRegsRegClass;
450 } else if (VT == MVT::i32 || VT == MVT::f32) {
451 TRC = &Hexagon::IntRegsRegClass;
452 } else if (VT == MVT::i64 || VT == MVT::f64) {
453 TRC = &Hexagon::DoubleRegsRegClass;
455 llvm_unreachable("Cannot handle this register class");
458 unsigned NewReg = RegInfo.createVirtualRegister(TRC);
462 bool HexagonInstrInfo::isExtendable(const MachineInstr *MI) const {
463 switch(MI->getOpcode()) {
464 default: return false;
466 case Hexagon::JMP_EQriPt_nv_V4:
467 case Hexagon::JMP_EQriPnt_nv_V4:
468 case Hexagon::JMP_EQriNotPt_nv_V4:
469 case Hexagon::JMP_EQriNotPnt_nv_V4:
471 // JMP_EQri - with -1
472 case Hexagon::JMP_EQriPtneg_nv_V4:
473 case Hexagon::JMP_EQriPntneg_nv_V4:
474 case Hexagon::JMP_EQriNotPtneg_nv_V4:
475 case Hexagon::JMP_EQriNotPntneg_nv_V4:
478 case Hexagon::JMP_EQrrPt_nv_V4:
479 case Hexagon::JMP_EQrrPnt_nv_V4:
480 case Hexagon::JMP_EQrrNotPt_nv_V4:
481 case Hexagon::JMP_EQrrNotPnt_nv_V4:
484 case Hexagon::JMP_GTriPt_nv_V4:
485 case Hexagon::JMP_GTriPnt_nv_V4:
486 case Hexagon::JMP_GTriNotPt_nv_V4:
487 case Hexagon::JMP_GTriNotPnt_nv_V4:
489 // JMP_GTri - with -1
490 case Hexagon::JMP_GTriPtneg_nv_V4:
491 case Hexagon::JMP_GTriPntneg_nv_V4:
492 case Hexagon::JMP_GTriNotPtneg_nv_V4:
493 case Hexagon::JMP_GTriNotPntneg_nv_V4:
496 case Hexagon::JMP_GTrrPt_nv_V4:
497 case Hexagon::JMP_GTrrPnt_nv_V4:
498 case Hexagon::JMP_GTrrNotPt_nv_V4:
499 case Hexagon::JMP_GTrrNotPnt_nv_V4:
502 case Hexagon::JMP_GTrrdnPt_nv_V4:
503 case Hexagon::JMP_GTrrdnPnt_nv_V4:
504 case Hexagon::JMP_GTrrdnNotPt_nv_V4:
505 case Hexagon::JMP_GTrrdnNotPnt_nv_V4:
508 case Hexagon::JMP_GTUriPt_nv_V4:
509 case Hexagon::JMP_GTUriPnt_nv_V4:
510 case Hexagon::JMP_GTUriNotPt_nv_V4:
511 case Hexagon::JMP_GTUriNotPnt_nv_V4:
514 case Hexagon::JMP_GTUrrPt_nv_V4:
515 case Hexagon::JMP_GTUrrPnt_nv_V4:
516 case Hexagon::JMP_GTUrrNotPt_nv_V4:
517 case Hexagon::JMP_GTUrrNotPnt_nv_V4:
520 case Hexagon::JMP_GTUrrdnPt_nv_V4:
521 case Hexagon::JMP_GTUrrdnPnt_nv_V4:
522 case Hexagon::JMP_GTUrrdnNotPt_nv_V4:
523 case Hexagon::JMP_GTUrrdnNotPnt_nv_V4:
526 case Hexagon::TFR_FI:
531 bool HexagonInstrInfo::isExtended(const MachineInstr *MI) const {
532 switch(MI->getOpcode()) {
533 default: return false;
535 case Hexagon::JMP_EQriPt_ie_nv_V4:
536 case Hexagon::JMP_EQriPnt_ie_nv_V4:
537 case Hexagon::JMP_EQriNotPt_ie_nv_V4:
538 case Hexagon::JMP_EQriNotPnt_ie_nv_V4:
540 // JMP_EQri - with -1
541 case Hexagon::JMP_EQriPtneg_ie_nv_V4:
542 case Hexagon::JMP_EQriPntneg_ie_nv_V4:
543 case Hexagon::JMP_EQriNotPtneg_ie_nv_V4:
544 case Hexagon::JMP_EQriNotPntneg_ie_nv_V4:
547 case Hexagon::JMP_EQrrPt_ie_nv_V4:
548 case Hexagon::JMP_EQrrPnt_ie_nv_V4:
549 case Hexagon::JMP_EQrrNotPt_ie_nv_V4:
550 case Hexagon::JMP_EQrrNotPnt_ie_nv_V4:
553 case Hexagon::JMP_GTriPt_ie_nv_V4:
554 case Hexagon::JMP_GTriPnt_ie_nv_V4:
555 case Hexagon::JMP_GTriNotPt_ie_nv_V4:
556 case Hexagon::JMP_GTriNotPnt_ie_nv_V4:
558 // JMP_GTri - with -1
559 case Hexagon::JMP_GTriPtneg_ie_nv_V4:
560 case Hexagon::JMP_GTriPntneg_ie_nv_V4:
561 case Hexagon::JMP_GTriNotPtneg_ie_nv_V4:
562 case Hexagon::JMP_GTriNotPntneg_ie_nv_V4:
565 case Hexagon::JMP_GTrrPt_ie_nv_V4:
566 case Hexagon::JMP_GTrrPnt_ie_nv_V4:
567 case Hexagon::JMP_GTrrNotPt_ie_nv_V4:
568 case Hexagon::JMP_GTrrNotPnt_ie_nv_V4:
571 case Hexagon::JMP_GTrrdnPt_ie_nv_V4:
572 case Hexagon::JMP_GTrrdnPnt_ie_nv_V4:
573 case Hexagon::JMP_GTrrdnNotPt_ie_nv_V4:
574 case Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4:
577 case Hexagon::JMP_GTUriPt_ie_nv_V4:
578 case Hexagon::JMP_GTUriPnt_ie_nv_V4:
579 case Hexagon::JMP_GTUriNotPt_ie_nv_V4:
580 case Hexagon::JMP_GTUriNotPnt_ie_nv_V4:
583 case Hexagon::JMP_GTUrrPt_ie_nv_V4:
584 case Hexagon::JMP_GTUrrPnt_ie_nv_V4:
585 case Hexagon::JMP_GTUrrNotPt_ie_nv_V4:
586 case Hexagon::JMP_GTUrrNotPnt_ie_nv_V4:
589 case Hexagon::JMP_GTUrrdnPt_ie_nv_V4:
590 case Hexagon::JMP_GTUrrdnPnt_ie_nv_V4:
591 case Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4:
592 case Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4:
594 // V4 absolute set addressing.
595 case Hexagon::LDrid_abs_setimm_V4:
596 case Hexagon::LDriw_abs_setimm_V4:
597 case Hexagon::LDrih_abs_setimm_V4:
598 case Hexagon::LDrib_abs_setimm_V4:
599 case Hexagon::LDriuh_abs_setimm_V4:
600 case Hexagon::LDriub_abs_setimm_V4:
602 case Hexagon::STrid_abs_setimm_V4:
603 case Hexagon::STrib_abs_setimm_V4:
604 case Hexagon::STrih_abs_setimm_V4:
605 case Hexagon::STriw_abs_setimm_V4:
607 // V4 global address load.
608 case Hexagon::LDrid_GP_cPt_V4 :
609 case Hexagon::LDrid_GP_cNotPt_V4 :
610 case Hexagon::LDrid_GP_cdnPt_V4 :
611 case Hexagon::LDrid_GP_cdnNotPt_V4 :
612 case Hexagon::LDrib_GP_cPt_V4 :
613 case Hexagon::LDrib_GP_cNotPt_V4 :
614 case Hexagon::LDrib_GP_cdnPt_V4 :
615 case Hexagon::LDrib_GP_cdnNotPt_V4 :
616 case Hexagon::LDriub_GP_cPt_V4 :
617 case Hexagon::LDriub_GP_cNotPt_V4 :
618 case Hexagon::LDriub_GP_cdnPt_V4 :
619 case Hexagon::LDriub_GP_cdnNotPt_V4 :
620 case Hexagon::LDrih_GP_cPt_V4 :
621 case Hexagon::LDrih_GP_cNotPt_V4 :
622 case Hexagon::LDrih_GP_cdnPt_V4 :
623 case Hexagon::LDrih_GP_cdnNotPt_V4 :
624 case Hexagon::LDriuh_GP_cPt_V4 :
625 case Hexagon::LDriuh_GP_cNotPt_V4 :
626 case Hexagon::LDriuh_GP_cdnPt_V4 :
627 case Hexagon::LDriuh_GP_cdnNotPt_V4 :
628 case Hexagon::LDriw_GP_cPt_V4 :
629 case Hexagon::LDriw_GP_cNotPt_V4 :
630 case Hexagon::LDriw_GP_cdnPt_V4 :
631 case Hexagon::LDriw_GP_cdnNotPt_V4 :
632 case Hexagon::LDd_GP_cPt_V4 :
633 case Hexagon::LDd_GP_cNotPt_V4 :
634 case Hexagon::LDd_GP_cdnPt_V4 :
635 case Hexagon::LDd_GP_cdnNotPt_V4 :
636 case Hexagon::LDb_GP_cPt_V4 :
637 case Hexagon::LDb_GP_cNotPt_V4 :
638 case Hexagon::LDb_GP_cdnPt_V4 :
639 case Hexagon::LDb_GP_cdnNotPt_V4 :
640 case Hexagon::LDub_GP_cPt_V4 :
641 case Hexagon::LDub_GP_cNotPt_V4 :
642 case Hexagon::LDub_GP_cdnPt_V4 :
643 case Hexagon::LDub_GP_cdnNotPt_V4 :
644 case Hexagon::LDh_GP_cPt_V4 :
645 case Hexagon::LDh_GP_cNotPt_V4 :
646 case Hexagon::LDh_GP_cdnPt_V4 :
647 case Hexagon::LDh_GP_cdnNotPt_V4 :
648 case Hexagon::LDuh_GP_cPt_V4 :
649 case Hexagon::LDuh_GP_cNotPt_V4 :
650 case Hexagon::LDuh_GP_cdnPt_V4 :
651 case Hexagon::LDuh_GP_cdnNotPt_V4 :
652 case Hexagon::LDw_GP_cPt_V4 :
653 case Hexagon::LDw_GP_cNotPt_V4 :
654 case Hexagon::LDw_GP_cdnPt_V4 :
655 case Hexagon::LDw_GP_cdnNotPt_V4 :
657 // V4 global address store.
658 case Hexagon::STrid_GP_cPt_V4 :
659 case Hexagon::STrid_GP_cNotPt_V4 :
660 case Hexagon::STrid_GP_cdnPt_V4 :
661 case Hexagon::STrid_GP_cdnNotPt_V4 :
662 case Hexagon::STrib_GP_cPt_V4 :
663 case Hexagon::STrib_GP_cNotPt_V4 :
664 case Hexagon::STrib_GP_cdnPt_V4 :
665 case Hexagon::STrib_GP_cdnNotPt_V4 :
666 case Hexagon::STrih_GP_cPt_V4 :
667 case Hexagon::STrih_GP_cNotPt_V4 :
668 case Hexagon::STrih_GP_cdnPt_V4 :
669 case Hexagon::STrih_GP_cdnNotPt_V4 :
670 case Hexagon::STriw_GP_cPt_V4 :
671 case Hexagon::STriw_GP_cNotPt_V4 :
672 case Hexagon::STriw_GP_cdnPt_V4 :
673 case Hexagon::STriw_GP_cdnNotPt_V4 :
674 case Hexagon::STd_GP_cPt_V4 :
675 case Hexagon::STd_GP_cNotPt_V4 :
676 case Hexagon::STd_GP_cdnPt_V4 :
677 case Hexagon::STd_GP_cdnNotPt_V4 :
678 case Hexagon::STb_GP_cPt_V4 :
679 case Hexagon::STb_GP_cNotPt_V4 :
680 case Hexagon::STb_GP_cdnPt_V4 :
681 case Hexagon::STb_GP_cdnNotPt_V4 :
682 case Hexagon::STh_GP_cPt_V4 :
683 case Hexagon::STh_GP_cNotPt_V4 :
684 case Hexagon::STh_GP_cdnPt_V4 :
685 case Hexagon::STh_GP_cdnNotPt_V4 :
686 case Hexagon::STw_GP_cPt_V4 :
687 case Hexagon::STw_GP_cNotPt_V4 :
688 case Hexagon::STw_GP_cdnPt_V4 :
689 case Hexagon::STw_GP_cdnNotPt_V4 :
691 // V4 predicated global address new value store.
692 case Hexagon::STrib_GP_cPt_nv_V4 :
693 case Hexagon::STrib_GP_cNotPt_nv_V4 :
694 case Hexagon::STrib_GP_cdnPt_nv_V4 :
695 case Hexagon::STrib_GP_cdnNotPt_nv_V4 :
696 case Hexagon::STrih_GP_cPt_nv_V4 :
697 case Hexagon::STrih_GP_cNotPt_nv_V4 :
698 case Hexagon::STrih_GP_cdnPt_nv_V4 :
699 case Hexagon::STrih_GP_cdnNotPt_nv_V4 :
700 case Hexagon::STriw_GP_cPt_nv_V4 :
701 case Hexagon::STriw_GP_cNotPt_nv_V4 :
702 case Hexagon::STriw_GP_cdnPt_nv_V4 :
703 case Hexagon::STriw_GP_cdnNotPt_nv_V4 :
704 case Hexagon::STb_GP_cPt_nv_V4 :
705 case Hexagon::STb_GP_cNotPt_nv_V4 :
706 case Hexagon::STb_GP_cdnPt_nv_V4 :
707 case Hexagon::STb_GP_cdnNotPt_nv_V4 :
708 case Hexagon::STh_GP_cPt_nv_V4 :
709 case Hexagon::STh_GP_cNotPt_nv_V4 :
710 case Hexagon::STh_GP_cdnPt_nv_V4 :
711 case Hexagon::STh_GP_cdnNotPt_nv_V4 :
712 case Hexagon::STw_GP_cPt_nv_V4 :
713 case Hexagon::STw_GP_cNotPt_nv_V4 :
714 case Hexagon::STw_GP_cdnPt_nv_V4 :
715 case Hexagon::STw_GP_cdnNotPt_nv_V4 :
718 case Hexagon::TFR_FI_immext_V4:
723 bool HexagonInstrInfo::isNewValueJump(const MachineInstr *MI) const {
724 switch (MI->getOpcode()) {
725 default: return false;
727 case Hexagon::JMP_EQriPt_nv_V4:
728 case Hexagon::JMP_EQriPnt_nv_V4:
729 case Hexagon::JMP_EQriNotPt_nv_V4:
730 case Hexagon::JMP_EQriNotPnt_nv_V4:
731 case Hexagon::JMP_EQriPt_ie_nv_V4:
732 case Hexagon::JMP_EQriPnt_ie_nv_V4:
733 case Hexagon::JMP_EQriNotPt_ie_nv_V4:
734 case Hexagon::JMP_EQriNotPnt_ie_nv_V4:
736 // JMP_EQri - with -1
737 case Hexagon::JMP_EQriPtneg_nv_V4:
738 case Hexagon::JMP_EQriPntneg_nv_V4:
739 case Hexagon::JMP_EQriNotPtneg_nv_V4:
740 case Hexagon::JMP_EQriNotPntneg_nv_V4:
741 case Hexagon::JMP_EQriPtneg_ie_nv_V4:
742 case Hexagon::JMP_EQriPntneg_ie_nv_V4:
743 case Hexagon::JMP_EQriNotPtneg_ie_nv_V4:
744 case Hexagon::JMP_EQriNotPntneg_ie_nv_V4:
747 case Hexagon::JMP_EQrrPt_nv_V4:
748 case Hexagon::JMP_EQrrPnt_nv_V4:
749 case Hexagon::JMP_EQrrNotPt_nv_V4:
750 case Hexagon::JMP_EQrrNotPnt_nv_V4:
751 case Hexagon::JMP_EQrrPt_ie_nv_V4:
752 case Hexagon::JMP_EQrrPnt_ie_nv_V4:
753 case Hexagon::JMP_EQrrNotPt_ie_nv_V4:
754 case Hexagon::JMP_EQrrNotPnt_ie_nv_V4:
757 case Hexagon::JMP_GTriPt_nv_V4:
758 case Hexagon::JMP_GTriPnt_nv_V4:
759 case Hexagon::JMP_GTriNotPt_nv_V4:
760 case Hexagon::JMP_GTriNotPnt_nv_V4:
761 case Hexagon::JMP_GTriPt_ie_nv_V4:
762 case Hexagon::JMP_GTriPnt_ie_nv_V4:
763 case Hexagon::JMP_GTriNotPt_ie_nv_V4:
764 case Hexagon::JMP_GTriNotPnt_ie_nv_V4:
766 // JMP_GTri - with -1
767 case Hexagon::JMP_GTriPtneg_nv_V4:
768 case Hexagon::JMP_GTriPntneg_nv_V4:
769 case Hexagon::JMP_GTriNotPtneg_nv_V4:
770 case Hexagon::JMP_GTriNotPntneg_nv_V4:
771 case Hexagon::JMP_GTriPtneg_ie_nv_V4:
772 case Hexagon::JMP_GTriPntneg_ie_nv_V4:
773 case Hexagon::JMP_GTriNotPtneg_ie_nv_V4:
774 case Hexagon::JMP_GTriNotPntneg_ie_nv_V4:
777 case Hexagon::JMP_GTrrPt_nv_V4:
778 case Hexagon::JMP_GTrrPnt_nv_V4:
779 case Hexagon::JMP_GTrrNotPt_nv_V4:
780 case Hexagon::JMP_GTrrNotPnt_nv_V4:
781 case Hexagon::JMP_GTrrPt_ie_nv_V4:
782 case Hexagon::JMP_GTrrPnt_ie_nv_V4:
783 case Hexagon::JMP_GTrrNotPt_ie_nv_V4:
784 case Hexagon::JMP_GTrrNotPnt_ie_nv_V4:
787 case Hexagon::JMP_GTrrdnPt_nv_V4:
788 case Hexagon::JMP_GTrrdnPnt_nv_V4:
789 case Hexagon::JMP_GTrrdnNotPt_nv_V4:
790 case Hexagon::JMP_GTrrdnNotPnt_nv_V4:
791 case Hexagon::JMP_GTrrdnPt_ie_nv_V4:
792 case Hexagon::JMP_GTrrdnPnt_ie_nv_V4:
793 case Hexagon::JMP_GTrrdnNotPt_ie_nv_V4:
794 case Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4:
797 case Hexagon::JMP_GTUriPt_nv_V4:
798 case Hexagon::JMP_GTUriPnt_nv_V4:
799 case Hexagon::JMP_GTUriNotPt_nv_V4:
800 case Hexagon::JMP_GTUriNotPnt_nv_V4:
801 case Hexagon::JMP_GTUriPt_ie_nv_V4:
802 case Hexagon::JMP_GTUriPnt_ie_nv_V4:
803 case Hexagon::JMP_GTUriNotPt_ie_nv_V4:
804 case Hexagon::JMP_GTUriNotPnt_ie_nv_V4:
807 case Hexagon::JMP_GTUrrPt_nv_V4:
808 case Hexagon::JMP_GTUrrPnt_nv_V4:
809 case Hexagon::JMP_GTUrrNotPt_nv_V4:
810 case Hexagon::JMP_GTUrrNotPnt_nv_V4:
811 case Hexagon::JMP_GTUrrPt_ie_nv_V4:
812 case Hexagon::JMP_GTUrrPnt_ie_nv_V4:
813 case Hexagon::JMP_GTUrrNotPt_ie_nv_V4:
814 case Hexagon::JMP_GTUrrNotPnt_ie_nv_V4:
817 case Hexagon::JMP_GTUrrdnPt_nv_V4:
818 case Hexagon::JMP_GTUrrdnPnt_nv_V4:
819 case Hexagon::JMP_GTUrrdnNotPt_nv_V4:
820 case Hexagon::JMP_GTUrrdnNotPnt_nv_V4:
821 case Hexagon::JMP_GTUrrdnPt_ie_nv_V4:
822 case Hexagon::JMP_GTUrrdnPnt_ie_nv_V4:
823 case Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4:
824 case Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4:
829 unsigned HexagonInstrInfo::getImmExtForm(const MachineInstr* MI) const {
830 switch(MI->getOpcode()) {
831 default: llvm_unreachable("Unknown type of instruction.");
833 case Hexagon::JMP_EQriPt_nv_V4:
834 return Hexagon::JMP_EQriPt_ie_nv_V4;
835 case Hexagon::JMP_EQriNotPt_nv_V4:
836 return Hexagon::JMP_EQriNotPt_ie_nv_V4;
837 case Hexagon::JMP_EQriPnt_nv_V4:
838 return Hexagon::JMP_EQriPnt_ie_nv_V4;
839 case Hexagon::JMP_EQriNotPnt_nv_V4:
840 return Hexagon::JMP_EQriNotPnt_ie_nv_V4;
842 // JMP_EQri -- with -1
843 case Hexagon::JMP_EQriPtneg_nv_V4:
844 return Hexagon::JMP_EQriPtneg_ie_nv_V4;
845 case Hexagon::JMP_EQriNotPtneg_nv_V4:
846 return Hexagon::JMP_EQriNotPtneg_ie_nv_V4;
847 case Hexagon::JMP_EQriPntneg_nv_V4:
848 return Hexagon::JMP_EQriPntneg_ie_nv_V4;
849 case Hexagon::JMP_EQriNotPntneg_nv_V4:
850 return Hexagon::JMP_EQriNotPntneg_ie_nv_V4;
853 case Hexagon::JMP_EQrrPt_nv_V4:
854 return Hexagon::JMP_EQrrPt_ie_nv_V4;
855 case Hexagon::JMP_EQrrNotPt_nv_V4:
856 return Hexagon::JMP_EQrrNotPt_ie_nv_V4;
857 case Hexagon::JMP_EQrrPnt_nv_V4:
858 return Hexagon::JMP_EQrrPnt_ie_nv_V4;
859 case Hexagon::JMP_EQrrNotPnt_nv_V4:
860 return Hexagon::JMP_EQrrNotPnt_ie_nv_V4;
863 case Hexagon::JMP_GTriPt_nv_V4:
864 return Hexagon::JMP_GTriPt_ie_nv_V4;
865 case Hexagon::JMP_GTriNotPt_nv_V4:
866 return Hexagon::JMP_GTriNotPt_ie_nv_V4;
867 case Hexagon::JMP_GTriPnt_nv_V4:
868 return Hexagon::JMP_GTriPnt_ie_nv_V4;
869 case Hexagon::JMP_GTriNotPnt_nv_V4:
870 return Hexagon::JMP_GTriNotPnt_ie_nv_V4;
872 // JMP_GTri -- with -1
873 case Hexagon::JMP_GTriPtneg_nv_V4:
874 return Hexagon::JMP_GTriPtneg_ie_nv_V4;
875 case Hexagon::JMP_GTriNotPtneg_nv_V4:
876 return Hexagon::JMP_GTriNotPtneg_ie_nv_V4;
877 case Hexagon::JMP_GTriPntneg_nv_V4:
878 return Hexagon::JMP_GTriPntneg_ie_nv_V4;
879 case Hexagon::JMP_GTriNotPntneg_nv_V4:
880 return Hexagon::JMP_GTriNotPntneg_ie_nv_V4;
883 case Hexagon::JMP_GTrrPt_nv_V4:
884 return Hexagon::JMP_GTrrPt_ie_nv_V4;
885 case Hexagon::JMP_GTrrNotPt_nv_V4:
886 return Hexagon::JMP_GTrrNotPt_ie_nv_V4;
887 case Hexagon::JMP_GTrrPnt_nv_V4:
888 return Hexagon::JMP_GTrrPnt_ie_nv_V4;
889 case Hexagon::JMP_GTrrNotPnt_nv_V4:
890 return Hexagon::JMP_GTrrNotPnt_ie_nv_V4;
893 case Hexagon::JMP_GTrrdnPt_nv_V4:
894 return Hexagon::JMP_GTrrdnPt_ie_nv_V4;
895 case Hexagon::JMP_GTrrdnNotPt_nv_V4:
896 return Hexagon::JMP_GTrrdnNotPt_ie_nv_V4;
897 case Hexagon::JMP_GTrrdnPnt_nv_V4:
898 return Hexagon::JMP_GTrrdnPnt_ie_nv_V4;
899 case Hexagon::JMP_GTrrdnNotPnt_nv_V4:
900 return Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4;
903 case Hexagon::JMP_GTUriPt_nv_V4:
904 return Hexagon::JMP_GTUriPt_ie_nv_V4;
905 case Hexagon::JMP_GTUriNotPt_nv_V4:
906 return Hexagon::JMP_GTUriNotPt_ie_nv_V4;
907 case Hexagon::JMP_GTUriPnt_nv_V4:
908 return Hexagon::JMP_GTUriPnt_ie_nv_V4;
909 case Hexagon::JMP_GTUriNotPnt_nv_V4:
910 return Hexagon::JMP_GTUriNotPnt_ie_nv_V4;
913 case Hexagon::JMP_GTUrrPt_nv_V4:
914 return Hexagon::JMP_GTUrrPt_ie_nv_V4;
915 case Hexagon::JMP_GTUrrNotPt_nv_V4:
916 return Hexagon::JMP_GTUrrNotPt_ie_nv_V4;
917 case Hexagon::JMP_GTUrrPnt_nv_V4:
918 return Hexagon::JMP_GTUrrPnt_ie_nv_V4;
919 case Hexagon::JMP_GTUrrNotPnt_nv_V4:
920 return Hexagon::JMP_GTUrrNotPnt_ie_nv_V4;
923 case Hexagon::JMP_GTUrrdnPt_nv_V4:
924 return Hexagon::JMP_GTUrrdnPt_ie_nv_V4;
925 case Hexagon::JMP_GTUrrdnNotPt_nv_V4:
926 return Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4;
927 case Hexagon::JMP_GTUrrdnPnt_nv_V4:
928 return Hexagon::JMP_GTUrrdnPnt_ie_nv_V4;
929 case Hexagon::JMP_GTUrrdnNotPnt_nv_V4:
930 return Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4;
932 case Hexagon::TFR_FI:
933 return Hexagon::TFR_FI_immext_V4;
935 case Hexagon::MEMw_ADDSUBi_indexed_MEM_V4 :
936 case Hexagon::MEMw_ADDi_indexed_MEM_V4 :
937 case Hexagon::MEMw_SUBi_indexed_MEM_V4 :
938 case Hexagon::MEMw_ADDr_indexed_MEM_V4 :
939 case Hexagon::MEMw_SUBr_indexed_MEM_V4 :
940 case Hexagon::MEMw_ANDr_indexed_MEM_V4 :
941 case Hexagon::MEMw_ORr_indexed_MEM_V4 :
942 case Hexagon::MEMw_ADDSUBi_MEM_V4 :
943 case Hexagon::MEMw_ADDi_MEM_V4 :
944 case Hexagon::MEMw_SUBi_MEM_V4 :
945 case Hexagon::MEMw_ADDr_MEM_V4 :
946 case Hexagon::MEMw_SUBr_MEM_V4 :
947 case Hexagon::MEMw_ANDr_MEM_V4 :
948 case Hexagon::MEMw_ORr_MEM_V4 :
949 case Hexagon::MEMh_ADDSUBi_indexed_MEM_V4 :
950 case Hexagon::MEMh_ADDi_indexed_MEM_V4 :
951 case Hexagon::MEMh_SUBi_indexed_MEM_V4 :
952 case Hexagon::MEMh_ADDr_indexed_MEM_V4 :
953 case Hexagon::MEMh_SUBr_indexed_MEM_V4 :
954 case Hexagon::MEMh_ANDr_indexed_MEM_V4 :
955 case Hexagon::MEMh_ORr_indexed_MEM_V4 :
956 case Hexagon::MEMh_ADDSUBi_MEM_V4 :
957 case Hexagon::MEMh_ADDi_MEM_V4 :
958 case Hexagon::MEMh_SUBi_MEM_V4 :
959 case Hexagon::MEMh_ADDr_MEM_V4 :
960 case Hexagon::MEMh_SUBr_MEM_V4 :
961 case Hexagon::MEMh_ANDr_MEM_V4 :
962 case Hexagon::MEMh_ORr_MEM_V4 :
963 case Hexagon::MEMb_ADDSUBi_indexed_MEM_V4 :
964 case Hexagon::MEMb_ADDi_indexed_MEM_V4 :
965 case Hexagon::MEMb_SUBi_indexed_MEM_V4 :
966 case Hexagon::MEMb_ADDr_indexed_MEM_V4 :
967 case Hexagon::MEMb_SUBr_indexed_MEM_V4 :
968 case Hexagon::MEMb_ANDr_indexed_MEM_V4 :
969 case Hexagon::MEMb_ORr_indexed_MEM_V4 :
970 case Hexagon::MEMb_ADDSUBi_MEM_V4 :
971 case Hexagon::MEMb_ADDi_MEM_V4 :
972 case Hexagon::MEMb_SUBi_MEM_V4 :
973 case Hexagon::MEMb_ADDr_MEM_V4 :
974 case Hexagon::MEMb_SUBr_MEM_V4 :
975 case Hexagon::MEMb_ANDr_MEM_V4 :
976 case Hexagon::MEMb_ORr_MEM_V4 :
977 llvm_unreachable("Needs implementing");
981 unsigned HexagonInstrInfo::getNormalBranchForm(const MachineInstr* MI) const {
982 switch(MI->getOpcode()) {
983 default: llvm_unreachable("Unknown type of jump instruction.");
985 case Hexagon::JMP_EQriPt_ie_nv_V4:
986 return Hexagon::JMP_EQriPt_nv_V4;
987 case Hexagon::JMP_EQriNotPt_ie_nv_V4:
988 return Hexagon::JMP_EQriNotPt_nv_V4;
989 case Hexagon::JMP_EQriPnt_ie_nv_V4:
990 return Hexagon::JMP_EQriPnt_nv_V4;
991 case Hexagon::JMP_EQriNotPnt_ie_nv_V4:
992 return Hexagon::JMP_EQriNotPnt_nv_V4;
994 // JMP_EQri -- with -1
995 case Hexagon::JMP_EQriPtneg_ie_nv_V4:
996 return Hexagon::JMP_EQriPtneg_nv_V4;
997 case Hexagon::JMP_EQriNotPtneg_ie_nv_V4:
998 return Hexagon::JMP_EQriNotPtneg_nv_V4;
999 case Hexagon::JMP_EQriPntneg_ie_nv_V4:
1000 return Hexagon::JMP_EQriPntneg_nv_V4;
1001 case Hexagon::JMP_EQriNotPntneg_ie_nv_V4:
1002 return Hexagon::JMP_EQriNotPntneg_nv_V4;
1005 case Hexagon::JMP_EQrrPt_ie_nv_V4:
1006 return Hexagon::JMP_EQrrPt_nv_V4;
1007 case Hexagon::JMP_EQrrNotPt_ie_nv_V4:
1008 return Hexagon::JMP_EQrrNotPt_nv_V4;
1009 case Hexagon::JMP_EQrrPnt_ie_nv_V4:
1010 return Hexagon::JMP_EQrrPnt_nv_V4;
1011 case Hexagon::JMP_EQrrNotPnt_ie_nv_V4:
1012 return Hexagon::JMP_EQrrNotPnt_nv_V4;
1015 case Hexagon::JMP_GTriPt_ie_nv_V4:
1016 return Hexagon::JMP_GTriPt_nv_V4;
1017 case Hexagon::JMP_GTriNotPt_ie_nv_V4:
1018 return Hexagon::JMP_GTriNotPt_nv_V4;
1019 case Hexagon::JMP_GTriPnt_ie_nv_V4:
1020 return Hexagon::JMP_GTriPnt_nv_V4;
1021 case Hexagon::JMP_GTriNotPnt_ie_nv_V4:
1022 return Hexagon::JMP_GTriNotPnt_nv_V4;
1024 // JMP_GTri -- with -1
1025 case Hexagon::JMP_GTriPtneg_ie_nv_V4:
1026 return Hexagon::JMP_GTriPtneg_nv_V4;
1027 case Hexagon::JMP_GTriNotPtneg_ie_nv_V4:
1028 return Hexagon::JMP_GTriNotPtneg_nv_V4;
1029 case Hexagon::JMP_GTriPntneg_ie_nv_V4:
1030 return Hexagon::JMP_GTriPntneg_nv_V4;
1031 case Hexagon::JMP_GTriNotPntneg_ie_nv_V4:
1032 return Hexagon::JMP_GTriNotPntneg_nv_V4;
1035 case Hexagon::JMP_GTrrPt_ie_nv_V4:
1036 return Hexagon::JMP_GTrrPt_nv_V4;
1037 case Hexagon::JMP_GTrrNotPt_ie_nv_V4:
1038 return Hexagon::JMP_GTrrNotPt_nv_V4;
1039 case Hexagon::JMP_GTrrPnt_ie_nv_V4:
1040 return Hexagon::JMP_GTrrPnt_nv_V4;
1041 case Hexagon::JMP_GTrrNotPnt_ie_nv_V4:
1042 return Hexagon::JMP_GTrrNotPnt_nv_V4;
1045 case Hexagon::JMP_GTrrdnPt_ie_nv_V4:
1046 return Hexagon::JMP_GTrrdnPt_nv_V4;
1047 case Hexagon::JMP_GTrrdnNotPt_ie_nv_V4:
1048 return Hexagon::JMP_GTrrdnNotPt_nv_V4;
1049 case Hexagon::JMP_GTrrdnPnt_ie_nv_V4:
1050 return Hexagon::JMP_GTrrdnPnt_nv_V4;
1051 case Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4:
1052 return Hexagon::JMP_GTrrdnNotPnt_nv_V4;
1055 case Hexagon::JMP_GTUriPt_ie_nv_V4:
1056 return Hexagon::JMP_GTUriPt_nv_V4;
1057 case Hexagon::JMP_GTUriNotPt_ie_nv_V4:
1058 return Hexagon::JMP_GTUriNotPt_nv_V4;
1059 case Hexagon::JMP_GTUriPnt_ie_nv_V4:
1060 return Hexagon::JMP_GTUriPnt_nv_V4;
1061 case Hexagon::JMP_GTUriNotPnt_ie_nv_V4:
1062 return Hexagon::JMP_GTUriNotPnt_nv_V4;
1065 case Hexagon::JMP_GTUrrPt_ie_nv_V4:
1066 return Hexagon::JMP_GTUrrPt_nv_V4;
1067 case Hexagon::JMP_GTUrrNotPt_ie_nv_V4:
1068 return Hexagon::JMP_GTUrrNotPt_nv_V4;
1069 case Hexagon::JMP_GTUrrPnt_ie_nv_V4:
1070 return Hexagon::JMP_GTUrrPnt_nv_V4;
1071 case Hexagon::JMP_GTUrrNotPnt_ie_nv_V4:
1072 return Hexagon::JMP_GTUrrNotPnt_nv_V4;
1075 case Hexagon::JMP_GTUrrdnPt_ie_nv_V4:
1076 return Hexagon::JMP_GTUrrdnPt_nv_V4;
1077 case Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4:
1078 return Hexagon::JMP_GTUrrdnNotPt_nv_V4;
1079 case Hexagon::JMP_GTUrrdnPnt_ie_nv_V4:
1080 return Hexagon::JMP_GTUrrdnPnt_nv_V4;
1081 case Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4:
1082 return Hexagon::JMP_GTUrrdnNotPnt_nv_V4;
1087 bool HexagonInstrInfo::isNewValueStore(const MachineInstr *MI) const {
1088 switch (MI->getOpcode()) {
1089 default: return false;
1091 case Hexagon::STrib_nv_V4:
1092 case Hexagon::STrib_indexed_nv_V4:
1093 case Hexagon::STrib_indexed_shl_nv_V4:
1094 case Hexagon::STrib_shl_nv_V4:
1095 case Hexagon::STrib_GP_nv_V4:
1096 case Hexagon::STb_GP_nv_V4:
1097 case Hexagon::POST_STbri_nv_V4:
1098 case Hexagon::STrib_cPt_nv_V4:
1099 case Hexagon::STrib_cdnPt_nv_V4:
1100 case Hexagon::STrib_cNotPt_nv_V4:
1101 case Hexagon::STrib_cdnNotPt_nv_V4:
1102 case Hexagon::STrib_indexed_cPt_nv_V4:
1103 case Hexagon::STrib_indexed_cdnPt_nv_V4:
1104 case Hexagon::STrib_indexed_cNotPt_nv_V4:
1105 case Hexagon::STrib_indexed_cdnNotPt_nv_V4:
1106 case Hexagon::STrib_indexed_shl_cPt_nv_V4:
1107 case Hexagon::STrib_indexed_shl_cdnPt_nv_V4:
1108 case Hexagon::STrib_indexed_shl_cNotPt_nv_V4:
1109 case Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4:
1110 case Hexagon::POST_STbri_cPt_nv_V4:
1111 case Hexagon::POST_STbri_cdnPt_nv_V4:
1112 case Hexagon::POST_STbri_cNotPt_nv_V4:
1113 case Hexagon::POST_STbri_cdnNotPt_nv_V4:
1114 case Hexagon::STb_GP_cPt_nv_V4:
1115 case Hexagon::STb_GP_cNotPt_nv_V4:
1116 case Hexagon::STb_GP_cdnPt_nv_V4:
1117 case Hexagon::STb_GP_cdnNotPt_nv_V4:
1118 case Hexagon::STrib_GP_cPt_nv_V4:
1119 case Hexagon::STrib_GP_cNotPt_nv_V4:
1120 case Hexagon::STrib_GP_cdnPt_nv_V4:
1121 case Hexagon::STrib_GP_cdnNotPt_nv_V4:
1122 case Hexagon::STrib_abs_nv_V4:
1123 case Hexagon::STrib_abs_cPt_nv_V4:
1124 case Hexagon::STrib_abs_cdnPt_nv_V4:
1125 case Hexagon::STrib_abs_cNotPt_nv_V4:
1126 case Hexagon::STrib_abs_cdnNotPt_nv_V4:
1127 case Hexagon::STrib_imm_abs_nv_V4:
1128 case Hexagon::STrib_imm_abs_cPt_nv_V4:
1129 case Hexagon::STrib_imm_abs_cdnPt_nv_V4:
1130 case Hexagon::STrib_imm_abs_cNotPt_nv_V4:
1131 case Hexagon::STrib_imm_abs_cdnNotPt_nv_V4:
1134 case Hexagon::STrih_nv_V4:
1135 case Hexagon::STrih_indexed_nv_V4:
1136 case Hexagon::STrih_indexed_shl_nv_V4:
1137 case Hexagon::STrih_shl_nv_V4:
1138 case Hexagon::STrih_GP_nv_V4:
1139 case Hexagon::STh_GP_nv_V4:
1140 case Hexagon::POST_SThri_nv_V4:
1141 case Hexagon::STrih_cPt_nv_V4:
1142 case Hexagon::STrih_cdnPt_nv_V4:
1143 case Hexagon::STrih_cNotPt_nv_V4:
1144 case Hexagon::STrih_cdnNotPt_nv_V4:
1145 case Hexagon::STrih_indexed_cPt_nv_V4:
1146 case Hexagon::STrih_indexed_cdnPt_nv_V4:
1147 case Hexagon::STrih_indexed_cNotPt_nv_V4:
1148 case Hexagon::STrih_indexed_cdnNotPt_nv_V4:
1149 case Hexagon::STrih_indexed_shl_cPt_nv_V4:
1150 case Hexagon::STrih_indexed_shl_cdnPt_nv_V4:
1151 case Hexagon::STrih_indexed_shl_cNotPt_nv_V4:
1152 case Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4:
1153 case Hexagon::POST_SThri_cPt_nv_V4:
1154 case Hexagon::POST_SThri_cdnPt_nv_V4:
1155 case Hexagon::POST_SThri_cNotPt_nv_V4:
1156 case Hexagon::POST_SThri_cdnNotPt_nv_V4:
1157 case Hexagon::STh_GP_cPt_nv_V4:
1158 case Hexagon::STh_GP_cNotPt_nv_V4:
1159 case Hexagon::STh_GP_cdnPt_nv_V4:
1160 case Hexagon::STh_GP_cdnNotPt_nv_V4:
1161 case Hexagon::STrih_GP_cPt_nv_V4:
1162 case Hexagon::STrih_GP_cNotPt_nv_V4:
1163 case Hexagon::STrih_GP_cdnPt_nv_V4:
1164 case Hexagon::STrih_GP_cdnNotPt_nv_V4:
1165 case Hexagon::STrih_abs_nv_V4:
1166 case Hexagon::STrih_abs_cPt_nv_V4:
1167 case Hexagon::STrih_abs_cdnPt_nv_V4:
1168 case Hexagon::STrih_abs_cNotPt_nv_V4:
1169 case Hexagon::STrih_abs_cdnNotPt_nv_V4:
1170 case Hexagon::STrih_imm_abs_nv_V4:
1171 case Hexagon::STrih_imm_abs_cPt_nv_V4:
1172 case Hexagon::STrih_imm_abs_cdnPt_nv_V4:
1173 case Hexagon::STrih_imm_abs_cNotPt_nv_V4:
1174 case Hexagon::STrih_imm_abs_cdnNotPt_nv_V4:
1177 case Hexagon::STriw_nv_V4:
1178 case Hexagon::STriw_indexed_nv_V4:
1179 case Hexagon::STriw_indexed_shl_nv_V4:
1180 case Hexagon::STriw_shl_nv_V4:
1181 case Hexagon::STriw_GP_nv_V4:
1182 case Hexagon::STw_GP_nv_V4:
1183 case Hexagon::POST_STwri_nv_V4:
1184 case Hexagon::STriw_cPt_nv_V4:
1185 case Hexagon::STriw_cdnPt_nv_V4:
1186 case Hexagon::STriw_cNotPt_nv_V4:
1187 case Hexagon::STriw_cdnNotPt_nv_V4:
1188 case Hexagon::STriw_indexed_cPt_nv_V4:
1189 case Hexagon::STriw_indexed_cdnPt_nv_V4:
1190 case Hexagon::STriw_indexed_cNotPt_nv_V4:
1191 case Hexagon::STriw_indexed_cdnNotPt_nv_V4:
1192 case Hexagon::STriw_indexed_shl_cPt_nv_V4:
1193 case Hexagon::STriw_indexed_shl_cdnPt_nv_V4:
1194 case Hexagon::STriw_indexed_shl_cNotPt_nv_V4:
1195 case Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4:
1196 case Hexagon::POST_STwri_cPt_nv_V4:
1197 case Hexagon::POST_STwri_cdnPt_nv_V4:
1198 case Hexagon::POST_STwri_cNotPt_nv_V4:
1199 case Hexagon::POST_STwri_cdnNotPt_nv_V4:
1200 case Hexagon::STw_GP_cPt_nv_V4:
1201 case Hexagon::STw_GP_cNotPt_nv_V4:
1202 case Hexagon::STw_GP_cdnPt_nv_V4:
1203 case Hexagon::STw_GP_cdnNotPt_nv_V4:
1204 case Hexagon::STriw_GP_cPt_nv_V4:
1205 case Hexagon::STriw_GP_cNotPt_nv_V4:
1206 case Hexagon::STriw_GP_cdnPt_nv_V4:
1207 case Hexagon::STriw_GP_cdnNotPt_nv_V4:
1208 case Hexagon::STriw_abs_nv_V4:
1209 case Hexagon::STriw_abs_cPt_nv_V4:
1210 case Hexagon::STriw_abs_cdnPt_nv_V4:
1211 case Hexagon::STriw_abs_cNotPt_nv_V4:
1212 case Hexagon::STriw_abs_cdnNotPt_nv_V4:
1213 case Hexagon::STriw_imm_abs_nv_V4:
1214 case Hexagon::STriw_imm_abs_cPt_nv_V4:
1215 case Hexagon::STriw_imm_abs_cdnPt_nv_V4:
1216 case Hexagon::STriw_imm_abs_cNotPt_nv_V4:
1217 case Hexagon::STriw_imm_abs_cdnNotPt_nv_V4:
1222 bool HexagonInstrInfo::isPostIncrement (const MachineInstr* MI) const {
1223 switch (MI->getOpcode())
1225 default: return false;
1227 case Hexagon::POST_LDrib:
1228 case Hexagon::POST_LDrib_cPt:
1229 case Hexagon::POST_LDrib_cNotPt:
1230 case Hexagon::POST_LDrib_cdnPt_V4:
1231 case Hexagon::POST_LDrib_cdnNotPt_V4:
1233 // Load unsigned byte
1234 case Hexagon::POST_LDriub:
1235 case Hexagon::POST_LDriub_cPt:
1236 case Hexagon::POST_LDriub_cNotPt:
1237 case Hexagon::POST_LDriub_cdnPt_V4:
1238 case Hexagon::POST_LDriub_cdnNotPt_V4:
1241 case Hexagon::POST_LDrih:
1242 case Hexagon::POST_LDrih_cPt:
1243 case Hexagon::POST_LDrih_cNotPt:
1244 case Hexagon::POST_LDrih_cdnPt_V4:
1245 case Hexagon::POST_LDrih_cdnNotPt_V4:
1247 // Load unsigned halfword
1248 case Hexagon::POST_LDriuh:
1249 case Hexagon::POST_LDriuh_cPt:
1250 case Hexagon::POST_LDriuh_cNotPt:
1251 case Hexagon::POST_LDriuh_cdnPt_V4:
1252 case Hexagon::POST_LDriuh_cdnNotPt_V4:
1255 case Hexagon::POST_LDriw:
1256 case Hexagon::POST_LDriw_cPt:
1257 case Hexagon::POST_LDriw_cNotPt:
1258 case Hexagon::POST_LDriw_cdnPt_V4:
1259 case Hexagon::POST_LDriw_cdnNotPt_V4:
1262 case Hexagon::POST_LDrid:
1263 case Hexagon::POST_LDrid_cPt:
1264 case Hexagon::POST_LDrid_cNotPt:
1265 case Hexagon::POST_LDrid_cdnPt_V4:
1266 case Hexagon::POST_LDrid_cdnNotPt_V4:
1269 case Hexagon::POST_STbri:
1270 case Hexagon::POST_STbri_cPt:
1271 case Hexagon::POST_STbri_cNotPt:
1272 case Hexagon::POST_STbri_cdnPt_V4:
1273 case Hexagon::POST_STbri_cdnNotPt_V4:
1276 case Hexagon::POST_SThri:
1277 case Hexagon::POST_SThri_cPt:
1278 case Hexagon::POST_SThri_cNotPt:
1279 case Hexagon::POST_SThri_cdnPt_V4:
1280 case Hexagon::POST_SThri_cdnNotPt_V4:
1283 case Hexagon::POST_STwri:
1284 case Hexagon::POST_STwri_cPt:
1285 case Hexagon::POST_STwri_cNotPt:
1286 case Hexagon::POST_STwri_cdnPt_V4:
1287 case Hexagon::POST_STwri_cdnNotPt_V4:
1289 // Store double word
1290 case Hexagon::POST_STdri:
1291 case Hexagon::POST_STdri_cPt:
1292 case Hexagon::POST_STdri_cNotPt:
1293 case Hexagon::POST_STdri_cdnPt_V4:
1294 case Hexagon::POST_STdri_cdnNotPt_V4:
1299 bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr *MI) const {
1300 return MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4;
1303 bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
1304 bool isPred = MI->getDesc().isPredicable();
1309 const int Opc = MI->getOpcode();
1313 return isInt<12>(MI->getOperand(1).getImm());
1315 case Hexagon::STrid:
1316 case Hexagon::STrid_indexed:
1317 return isShiftedUInt<6,3>(MI->getOperand(1).getImm());
1319 case Hexagon::STriw:
1320 case Hexagon::STriw_indexed:
1321 case Hexagon::STriw_nv_V4:
1322 return isShiftedUInt<6,2>(MI->getOperand(1).getImm());
1324 case Hexagon::STrih:
1325 case Hexagon::STrih_indexed:
1326 case Hexagon::STrih_nv_V4:
1327 return isShiftedUInt<6,1>(MI->getOperand(1).getImm());
1329 case Hexagon::STrib:
1330 case Hexagon::STrib_indexed:
1331 case Hexagon::STrib_nv_V4:
1332 return isUInt<6>(MI->getOperand(1).getImm());
1334 case Hexagon::LDrid:
1335 case Hexagon::LDrid_indexed:
1336 return isShiftedUInt<6,3>(MI->getOperand(2).getImm());
1338 case Hexagon::LDriw:
1339 case Hexagon::LDriw_indexed:
1340 return isShiftedUInt<6,2>(MI->getOperand(2).getImm());
1342 case Hexagon::LDrih:
1343 case Hexagon::LDriuh:
1344 case Hexagon::LDrih_indexed:
1345 case Hexagon::LDriuh_indexed:
1346 return isShiftedUInt<6,1>(MI->getOperand(2).getImm());
1348 case Hexagon::LDrib:
1349 case Hexagon::LDriub:
1350 case Hexagon::LDrib_indexed:
1351 case Hexagon::LDriub_indexed:
1352 return isUInt<6>(MI->getOperand(2).getImm());
1354 case Hexagon::POST_LDrid:
1355 return isShiftedInt<4,3>(MI->getOperand(3).getImm());
1357 case Hexagon::POST_LDriw:
1358 return isShiftedInt<4,2>(MI->getOperand(3).getImm());
1360 case Hexagon::POST_LDrih:
1361 case Hexagon::POST_LDriuh:
1362 return isShiftedInt<4,1>(MI->getOperand(3).getImm());
1364 case Hexagon::POST_LDrib:
1365 case Hexagon::POST_LDriub:
1366 return isInt<4>(MI->getOperand(3).getImm());
1368 case Hexagon::STrib_imm_V4:
1369 case Hexagon::STrih_imm_V4:
1370 case Hexagon::STriw_imm_V4:
1371 return (isUInt<6>(MI->getOperand(1).getImm()) &&
1372 isInt<6>(MI->getOperand(2).getImm()));
1374 case Hexagon::ADD_ri:
1375 return isInt<8>(MI->getOperand(2).getImm());
1383 return Subtarget.getHexagonArchVersion() == HexagonSubtarget::V4;
1392 unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
1394 default: llvm_unreachable("Unexpected predicated instruction");
1395 case Hexagon::TFR_cPt:
1396 return Hexagon::TFR_cNotPt;
1397 case Hexagon::TFR_cNotPt:
1398 return Hexagon::TFR_cPt;
1400 case Hexagon::TFRI_cPt:
1401 return Hexagon::TFRI_cNotPt;
1402 case Hexagon::TFRI_cNotPt:
1403 return Hexagon::TFRI_cPt;
1405 case Hexagon::JMP_c:
1406 return Hexagon::JMP_cNot;
1407 case Hexagon::JMP_cNot:
1408 return Hexagon::JMP_c;
1410 case Hexagon::ADD_ri_cPt:
1411 return Hexagon::ADD_ri_cNotPt;
1412 case Hexagon::ADD_ri_cNotPt:
1413 return Hexagon::ADD_ri_cPt;
1415 case Hexagon::ADD_rr_cPt:
1416 return Hexagon::ADD_rr_cNotPt;
1417 case Hexagon::ADD_rr_cNotPt:
1418 return Hexagon::ADD_rr_cPt;
1420 case Hexagon::XOR_rr_cPt:
1421 return Hexagon::XOR_rr_cNotPt;
1422 case Hexagon::XOR_rr_cNotPt:
1423 return Hexagon::XOR_rr_cPt;
1425 case Hexagon::AND_rr_cPt:
1426 return Hexagon::AND_rr_cNotPt;
1427 case Hexagon::AND_rr_cNotPt:
1428 return Hexagon::AND_rr_cPt;
1430 case Hexagon::OR_rr_cPt:
1431 return Hexagon::OR_rr_cNotPt;
1432 case Hexagon::OR_rr_cNotPt:
1433 return Hexagon::OR_rr_cPt;
1435 case Hexagon::SUB_rr_cPt:
1436 return Hexagon::SUB_rr_cNotPt;
1437 case Hexagon::SUB_rr_cNotPt:
1438 return Hexagon::SUB_rr_cPt;
1440 case Hexagon::COMBINE_rr_cPt:
1441 return Hexagon::COMBINE_rr_cNotPt;
1442 case Hexagon::COMBINE_rr_cNotPt:
1443 return Hexagon::COMBINE_rr_cPt;
1445 case Hexagon::ASLH_cPt_V4:
1446 return Hexagon::ASLH_cNotPt_V4;
1447 case Hexagon::ASLH_cNotPt_V4:
1448 return Hexagon::ASLH_cPt_V4;
1450 case Hexagon::ASRH_cPt_V4:
1451 return Hexagon::ASRH_cNotPt_V4;
1452 case Hexagon::ASRH_cNotPt_V4:
1453 return Hexagon::ASRH_cPt_V4;
1455 case Hexagon::SXTB_cPt_V4:
1456 return Hexagon::SXTB_cNotPt_V4;
1457 case Hexagon::SXTB_cNotPt_V4:
1458 return Hexagon::SXTB_cPt_V4;
1460 case Hexagon::SXTH_cPt_V4:
1461 return Hexagon::SXTH_cNotPt_V4;
1462 case Hexagon::SXTH_cNotPt_V4:
1463 return Hexagon::SXTH_cPt_V4;
1465 case Hexagon::ZXTB_cPt_V4:
1466 return Hexagon::ZXTB_cNotPt_V4;
1467 case Hexagon::ZXTB_cNotPt_V4:
1468 return Hexagon::ZXTB_cPt_V4;
1470 case Hexagon::ZXTH_cPt_V4:
1471 return Hexagon::ZXTH_cNotPt_V4;
1472 case Hexagon::ZXTH_cNotPt_V4:
1473 return Hexagon::ZXTH_cPt_V4;
1476 case Hexagon::JMPR_cPt:
1477 return Hexagon::JMPR_cNotPt;
1478 case Hexagon::JMPR_cNotPt:
1479 return Hexagon::JMPR_cPt;
1481 // V4 indexed+scaled load.
1482 case Hexagon::LDrid_indexed_cPt_V4:
1483 return Hexagon::LDrid_indexed_cNotPt_V4;
1484 case Hexagon::LDrid_indexed_cNotPt_V4:
1485 return Hexagon::LDrid_indexed_cPt_V4;
1487 case Hexagon::LDrid_indexed_shl_cPt_V4:
1488 return Hexagon::LDrid_indexed_shl_cNotPt_V4;
1489 case Hexagon::LDrid_indexed_shl_cNotPt_V4:
1490 return Hexagon::LDrid_indexed_shl_cPt_V4;
1492 case Hexagon::LDrib_indexed_cPt_V4:
1493 return Hexagon::LDrib_indexed_cNotPt_V4;
1494 case Hexagon::LDrib_indexed_cNotPt_V4:
1495 return Hexagon::LDrib_indexed_cPt_V4;
1497 case Hexagon::LDriub_indexed_cPt_V4:
1498 return Hexagon::LDriub_indexed_cNotPt_V4;
1499 case Hexagon::LDriub_indexed_cNotPt_V4:
1500 return Hexagon::LDriub_indexed_cPt_V4;
1502 case Hexagon::LDrib_indexed_shl_cPt_V4:
1503 return Hexagon::LDrib_indexed_shl_cNotPt_V4;
1504 case Hexagon::LDrib_indexed_shl_cNotPt_V4:
1505 return Hexagon::LDrib_indexed_shl_cPt_V4;
1507 case Hexagon::LDriub_indexed_shl_cPt_V4:
1508 return Hexagon::LDriub_indexed_shl_cNotPt_V4;
1509 case Hexagon::LDriub_indexed_shl_cNotPt_V4:
1510 return Hexagon::LDriub_indexed_shl_cPt_V4;
1512 case Hexagon::LDrih_indexed_cPt_V4:
1513 return Hexagon::LDrih_indexed_cNotPt_V4;
1514 case Hexagon::LDrih_indexed_cNotPt_V4:
1515 return Hexagon::LDrih_indexed_cPt_V4;
1517 case Hexagon::LDriuh_indexed_cPt_V4:
1518 return Hexagon::LDriuh_indexed_cNotPt_V4;
1519 case Hexagon::LDriuh_indexed_cNotPt_V4:
1520 return Hexagon::LDriuh_indexed_cPt_V4;
1522 case Hexagon::LDrih_indexed_shl_cPt_V4:
1523 return Hexagon::LDrih_indexed_shl_cNotPt_V4;
1524 case Hexagon::LDrih_indexed_shl_cNotPt_V4:
1525 return Hexagon::LDrih_indexed_shl_cPt_V4;
1527 case Hexagon::LDriuh_indexed_shl_cPt_V4:
1528 return Hexagon::LDriuh_indexed_shl_cNotPt_V4;
1529 case Hexagon::LDriuh_indexed_shl_cNotPt_V4:
1530 return Hexagon::LDriuh_indexed_shl_cPt_V4;
1532 case Hexagon::LDriw_indexed_cPt_V4:
1533 return Hexagon::LDriw_indexed_cNotPt_V4;
1534 case Hexagon::LDriw_indexed_cNotPt_V4:
1535 return Hexagon::LDriw_indexed_cPt_V4;
1537 case Hexagon::LDriw_indexed_shl_cPt_V4:
1538 return Hexagon::LDriw_indexed_shl_cNotPt_V4;
1539 case Hexagon::LDriw_indexed_shl_cNotPt_V4:
1540 return Hexagon::LDriw_indexed_shl_cPt_V4;
1543 case Hexagon::POST_STbri_cPt:
1544 return Hexagon::POST_STbri_cNotPt;
1545 case Hexagon::POST_STbri_cNotPt:
1546 return Hexagon::POST_STbri_cPt;
1548 case Hexagon::STrib_cPt:
1549 return Hexagon::STrib_cNotPt;
1550 case Hexagon::STrib_cNotPt:
1551 return Hexagon::STrib_cPt;
1553 case Hexagon::STrib_indexed_cPt:
1554 return Hexagon::STrib_indexed_cNotPt;
1555 case Hexagon::STrib_indexed_cNotPt:
1556 return Hexagon::STrib_indexed_cPt;
1558 case Hexagon::STrib_imm_cPt_V4:
1559 return Hexagon::STrib_imm_cNotPt_V4;
1560 case Hexagon::STrib_imm_cNotPt_V4:
1561 return Hexagon::STrib_imm_cPt_V4;
1563 case Hexagon::STrib_indexed_shl_cPt_V4:
1564 return Hexagon::STrib_indexed_shl_cNotPt_V4;
1565 case Hexagon::STrib_indexed_shl_cNotPt_V4:
1566 return Hexagon::STrib_indexed_shl_cPt_V4;
1569 case Hexagon::POST_SThri_cPt:
1570 return Hexagon::POST_SThri_cNotPt;
1571 case Hexagon::POST_SThri_cNotPt:
1572 return Hexagon::POST_SThri_cPt;
1574 case Hexagon::STrih_cPt:
1575 return Hexagon::STrih_cNotPt;
1576 case Hexagon::STrih_cNotPt:
1577 return Hexagon::STrih_cPt;
1579 case Hexagon::STrih_indexed_cPt:
1580 return Hexagon::STrih_indexed_cNotPt;
1581 case Hexagon::STrih_indexed_cNotPt:
1582 return Hexagon::STrih_indexed_cPt;
1584 case Hexagon::STrih_imm_cPt_V4:
1585 return Hexagon::STrih_imm_cNotPt_V4;
1586 case Hexagon::STrih_imm_cNotPt_V4:
1587 return Hexagon::STrih_imm_cPt_V4;
1589 case Hexagon::STrih_indexed_shl_cPt_V4:
1590 return Hexagon::STrih_indexed_shl_cNotPt_V4;
1591 case Hexagon::STrih_indexed_shl_cNotPt_V4:
1592 return Hexagon::STrih_indexed_shl_cPt_V4;
1595 case Hexagon::POST_STwri_cPt:
1596 return Hexagon::POST_STwri_cNotPt;
1597 case Hexagon::POST_STwri_cNotPt:
1598 return Hexagon::POST_STwri_cPt;
1600 case Hexagon::STriw_cPt:
1601 return Hexagon::STriw_cNotPt;
1602 case Hexagon::STriw_cNotPt:
1603 return Hexagon::STriw_cPt;
1605 case Hexagon::STriw_indexed_cPt:
1606 return Hexagon::STriw_indexed_cNotPt;
1607 case Hexagon::STriw_indexed_cNotPt:
1608 return Hexagon::STriw_indexed_cPt;
1610 case Hexagon::STriw_indexed_shl_cPt_V4:
1611 return Hexagon::STriw_indexed_shl_cNotPt_V4;
1612 case Hexagon::STriw_indexed_shl_cNotPt_V4:
1613 return Hexagon::STriw_indexed_shl_cPt_V4;
1615 case Hexagon::STriw_imm_cPt_V4:
1616 return Hexagon::STriw_imm_cNotPt_V4;
1617 case Hexagon::STriw_imm_cNotPt_V4:
1618 return Hexagon::STriw_imm_cPt_V4;
1621 case Hexagon::POST_STdri_cPt:
1622 return Hexagon::POST_STdri_cNotPt;
1623 case Hexagon::POST_STdri_cNotPt:
1624 return Hexagon::POST_STdri_cPt;
1626 case Hexagon::STrid_cPt:
1627 return Hexagon::STrid_cNotPt;
1628 case Hexagon::STrid_cNotPt:
1629 return Hexagon::STrid_cPt;
1631 case Hexagon::STrid_indexed_cPt:
1632 return Hexagon::STrid_indexed_cNotPt;
1633 case Hexagon::STrid_indexed_cNotPt:
1634 return Hexagon::STrid_indexed_cPt;
1636 case Hexagon::STrid_indexed_shl_cPt_V4:
1637 return Hexagon::STrid_indexed_shl_cNotPt_V4;
1638 case Hexagon::STrid_indexed_shl_cNotPt_V4:
1639 return Hexagon::STrid_indexed_shl_cPt_V4;
1641 // V4 Store to global address.
1642 case Hexagon::STd_GP_cPt_V4:
1643 return Hexagon::STd_GP_cNotPt_V4;
1644 case Hexagon::STd_GP_cNotPt_V4:
1645 return Hexagon::STd_GP_cPt_V4;
1647 case Hexagon::STb_GP_cPt_V4:
1648 return Hexagon::STb_GP_cNotPt_V4;
1649 case Hexagon::STb_GP_cNotPt_V4:
1650 return Hexagon::STb_GP_cPt_V4;
1652 case Hexagon::STh_GP_cPt_V4:
1653 return Hexagon::STh_GP_cNotPt_V4;
1654 case Hexagon::STh_GP_cNotPt_V4:
1655 return Hexagon::STh_GP_cPt_V4;
1657 case Hexagon::STw_GP_cPt_V4:
1658 return Hexagon::STw_GP_cNotPt_V4;
1659 case Hexagon::STw_GP_cNotPt_V4:
1660 return Hexagon::STw_GP_cPt_V4;
1662 case Hexagon::STrid_GP_cPt_V4:
1663 return Hexagon::STrid_GP_cNotPt_V4;
1664 case Hexagon::STrid_GP_cNotPt_V4:
1665 return Hexagon::STrid_GP_cPt_V4;
1667 case Hexagon::STrib_GP_cPt_V4:
1668 return Hexagon::STrib_GP_cNotPt_V4;
1669 case Hexagon::STrib_GP_cNotPt_V4:
1670 return Hexagon::STrib_GP_cPt_V4;
1672 case Hexagon::STrih_GP_cPt_V4:
1673 return Hexagon::STrih_GP_cNotPt_V4;
1674 case Hexagon::STrih_GP_cNotPt_V4:
1675 return Hexagon::STrih_GP_cPt_V4;
1677 case Hexagon::STriw_GP_cPt_V4:
1678 return Hexagon::STriw_GP_cNotPt_V4;
1679 case Hexagon::STriw_GP_cNotPt_V4:
1680 return Hexagon::STriw_GP_cPt_V4;
1683 case Hexagon::LDrid_cPt:
1684 return Hexagon::LDrid_cNotPt;
1685 case Hexagon::LDrid_cNotPt:
1686 return Hexagon::LDrid_cPt;
1688 case Hexagon::LDriw_cPt:
1689 return Hexagon::LDriw_cNotPt;
1690 case Hexagon::LDriw_cNotPt:
1691 return Hexagon::LDriw_cPt;
1693 case Hexagon::LDrih_cPt:
1694 return Hexagon::LDrih_cNotPt;
1695 case Hexagon::LDrih_cNotPt:
1696 return Hexagon::LDrih_cPt;
1698 case Hexagon::LDriuh_cPt:
1699 return Hexagon::LDriuh_cNotPt;
1700 case Hexagon::LDriuh_cNotPt:
1701 return Hexagon::LDriuh_cPt;
1703 case Hexagon::LDrib_cPt:
1704 return Hexagon::LDrib_cNotPt;
1705 case Hexagon::LDrib_cNotPt:
1706 return Hexagon::LDrib_cPt;
1708 case Hexagon::LDriub_cPt:
1709 return Hexagon::LDriub_cNotPt;
1710 case Hexagon::LDriub_cNotPt:
1711 return Hexagon::LDriub_cPt;
1714 case Hexagon::LDrid_indexed_cPt:
1715 return Hexagon::LDrid_indexed_cNotPt;
1716 case Hexagon::LDrid_indexed_cNotPt:
1717 return Hexagon::LDrid_indexed_cPt;
1719 case Hexagon::LDriw_indexed_cPt:
1720 return Hexagon::LDriw_indexed_cNotPt;
1721 case Hexagon::LDriw_indexed_cNotPt:
1722 return Hexagon::LDriw_indexed_cPt;
1724 case Hexagon::LDrih_indexed_cPt:
1725 return Hexagon::LDrih_indexed_cNotPt;
1726 case Hexagon::LDrih_indexed_cNotPt:
1727 return Hexagon::LDrih_indexed_cPt;
1729 case Hexagon::LDriuh_indexed_cPt:
1730 return Hexagon::LDriuh_indexed_cNotPt;
1731 case Hexagon::LDriuh_indexed_cNotPt:
1732 return Hexagon::LDriuh_indexed_cPt;
1734 case Hexagon::LDrib_indexed_cPt:
1735 return Hexagon::LDrib_indexed_cNotPt;
1736 case Hexagon::LDrib_indexed_cNotPt:
1737 return Hexagon::LDrib_indexed_cPt;
1739 case Hexagon::LDriub_indexed_cPt:
1740 return Hexagon::LDriub_indexed_cNotPt;
1741 case Hexagon::LDriub_indexed_cNotPt:
1742 return Hexagon::LDriub_indexed_cPt;
1745 case Hexagon::POST_LDrid_cPt:
1746 return Hexagon::POST_LDrid_cNotPt;
1747 case Hexagon::POST_LDriw_cNotPt:
1748 return Hexagon::POST_LDriw_cPt;
1750 case Hexagon::POST_LDrih_cPt:
1751 return Hexagon::POST_LDrih_cNotPt;
1752 case Hexagon::POST_LDrih_cNotPt:
1753 return Hexagon::POST_LDrih_cPt;
1755 case Hexagon::POST_LDriuh_cPt:
1756 return Hexagon::POST_LDriuh_cNotPt;
1757 case Hexagon::POST_LDriuh_cNotPt:
1758 return Hexagon::POST_LDriuh_cPt;
1760 case Hexagon::POST_LDrib_cPt:
1761 return Hexagon::POST_LDrib_cNotPt;
1762 case Hexagon::POST_LDrib_cNotPt:
1763 return Hexagon::POST_LDrib_cPt;
1765 case Hexagon::POST_LDriub_cPt:
1766 return Hexagon::POST_LDriub_cNotPt;
1767 case Hexagon::POST_LDriub_cNotPt:
1768 return Hexagon::POST_LDriub_cPt;
1771 case Hexagon::DEALLOC_RET_cPt_V4:
1772 return Hexagon::DEALLOC_RET_cNotPt_V4;
1773 case Hexagon::DEALLOC_RET_cNotPt_V4:
1774 return Hexagon::DEALLOC_RET_cPt_V4;
1777 // JMPEQ_ri - with -1.
1778 case Hexagon::JMP_EQriPtneg_nv_V4:
1779 return Hexagon::JMP_EQriNotPtneg_nv_V4;
1780 case Hexagon::JMP_EQriNotPtneg_nv_V4:
1781 return Hexagon::JMP_EQriPtneg_nv_V4;
1783 case Hexagon::JMP_EQriPntneg_nv_V4:
1784 return Hexagon::JMP_EQriNotPntneg_nv_V4;
1785 case Hexagon::JMP_EQriNotPntneg_nv_V4:
1786 return Hexagon::JMP_EQriPntneg_nv_V4;
1789 case Hexagon::JMP_EQriPt_nv_V4:
1790 return Hexagon::JMP_EQriNotPt_nv_V4;
1791 case Hexagon::JMP_EQriNotPt_nv_V4:
1792 return Hexagon::JMP_EQriPt_nv_V4;
1794 case Hexagon::JMP_EQriPnt_nv_V4:
1795 return Hexagon::JMP_EQriNotPnt_nv_V4;
1796 case Hexagon::JMP_EQriNotPnt_nv_V4:
1797 return Hexagon::JMP_EQriPnt_nv_V4;
1800 case Hexagon::JMP_EQrrPt_nv_V4:
1801 return Hexagon::JMP_EQrrNotPt_nv_V4;
1802 case Hexagon::JMP_EQrrNotPt_nv_V4:
1803 return Hexagon::JMP_EQrrPt_nv_V4;
1805 case Hexagon::JMP_EQrrPnt_nv_V4:
1806 return Hexagon::JMP_EQrrNotPnt_nv_V4;
1807 case Hexagon::JMP_EQrrNotPnt_nv_V4:
1808 return Hexagon::JMP_EQrrPnt_nv_V4;
1810 // JMPGT_ri - with -1.
1811 case Hexagon::JMP_GTriPtneg_nv_V4:
1812 return Hexagon::JMP_GTriNotPtneg_nv_V4;
1813 case Hexagon::JMP_GTriNotPtneg_nv_V4:
1814 return Hexagon::JMP_GTriPtneg_nv_V4;
1816 case Hexagon::JMP_GTriPntneg_nv_V4:
1817 return Hexagon::JMP_GTriNotPntneg_nv_V4;
1818 case Hexagon::JMP_GTriNotPntneg_nv_V4:
1819 return Hexagon::JMP_GTriPntneg_nv_V4;
1822 case Hexagon::JMP_GTriPt_nv_V4:
1823 return Hexagon::JMP_GTriNotPt_nv_V4;
1824 case Hexagon::JMP_GTriNotPt_nv_V4:
1825 return Hexagon::JMP_GTriPt_nv_V4;
1827 case Hexagon::JMP_GTriPnt_nv_V4:
1828 return Hexagon::JMP_GTriNotPnt_nv_V4;
1829 case Hexagon::JMP_GTriNotPnt_nv_V4:
1830 return Hexagon::JMP_GTriPnt_nv_V4;
1833 case Hexagon::JMP_GTrrPt_nv_V4:
1834 return Hexagon::JMP_GTrrNotPt_nv_V4;
1835 case Hexagon::JMP_GTrrNotPt_nv_V4:
1836 return Hexagon::JMP_GTrrPt_nv_V4;
1838 case Hexagon::JMP_GTrrPnt_nv_V4:
1839 return Hexagon::JMP_GTrrNotPnt_nv_V4;
1840 case Hexagon::JMP_GTrrNotPnt_nv_V4:
1841 return Hexagon::JMP_GTrrPnt_nv_V4;
1844 case Hexagon::JMP_GTrrdnPt_nv_V4:
1845 return Hexagon::JMP_GTrrdnNotPt_nv_V4;
1846 case Hexagon::JMP_GTrrdnNotPt_nv_V4:
1847 return Hexagon::JMP_GTrrdnPt_nv_V4;
1849 case Hexagon::JMP_GTrrdnPnt_nv_V4:
1850 return Hexagon::JMP_GTrrdnNotPnt_nv_V4;
1851 case Hexagon::JMP_GTrrdnNotPnt_nv_V4:
1852 return Hexagon::JMP_GTrrdnPnt_nv_V4;
1855 case Hexagon::JMP_GTUriPt_nv_V4:
1856 return Hexagon::JMP_GTUriNotPt_nv_V4;
1857 case Hexagon::JMP_GTUriNotPt_nv_V4:
1858 return Hexagon::JMP_GTUriPt_nv_V4;
1860 case Hexagon::JMP_GTUriPnt_nv_V4:
1861 return Hexagon::JMP_GTUriNotPnt_nv_V4;
1862 case Hexagon::JMP_GTUriNotPnt_nv_V4:
1863 return Hexagon::JMP_GTUriPnt_nv_V4;
1866 case Hexagon::JMP_GTUrrPt_nv_V4:
1867 return Hexagon::JMP_GTUrrNotPt_nv_V4;
1868 case Hexagon::JMP_GTUrrNotPt_nv_V4:
1869 return Hexagon::JMP_GTUrrPt_nv_V4;
1871 case Hexagon::JMP_GTUrrPnt_nv_V4:
1872 return Hexagon::JMP_GTUrrNotPnt_nv_V4;
1873 case Hexagon::JMP_GTUrrNotPnt_nv_V4:
1874 return Hexagon::JMP_GTUrrPnt_nv_V4;
1877 case Hexagon::JMP_GTUrrdnPt_nv_V4:
1878 return Hexagon::JMP_GTUrrdnNotPt_nv_V4;
1879 case Hexagon::JMP_GTUrrdnNotPt_nv_V4:
1880 return Hexagon::JMP_GTUrrdnPt_nv_V4;
1882 case Hexagon::JMP_GTUrrdnPnt_nv_V4:
1883 return Hexagon::JMP_GTUrrdnNotPnt_nv_V4;
1884 case Hexagon::JMP_GTUrrdnNotPnt_nv_V4:
1885 return Hexagon::JMP_GTUrrdnPnt_nv_V4;
1890 int HexagonInstrInfo::
1891 getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const {
1894 return !invertPredicate ? Hexagon::TFR_cPt :
1895 Hexagon::TFR_cNotPt;
1897 return !invertPredicate ? Hexagon::TFRI_cPt :
1898 Hexagon::TFRI_cNotPt;
1900 return !invertPredicate ? Hexagon::JMP_c :
1902 case Hexagon::JMP_EQrrPt_nv_V4:
1903 return !invertPredicate ? Hexagon::JMP_EQrrPt_nv_V4 :
1904 Hexagon::JMP_EQrrNotPt_nv_V4;
1905 case Hexagon::JMP_EQriPt_nv_V4:
1906 return !invertPredicate ? Hexagon::JMP_EQriPt_nv_V4 :
1907 Hexagon::JMP_EQriNotPt_nv_V4;
1908 case Hexagon::ADD_ri:
1909 return !invertPredicate ? Hexagon::ADD_ri_cPt :
1910 Hexagon::ADD_ri_cNotPt;
1911 case Hexagon::ADD_rr:
1912 return !invertPredicate ? Hexagon::ADD_rr_cPt :
1913 Hexagon::ADD_rr_cNotPt;
1914 case Hexagon::XOR_rr:
1915 return !invertPredicate ? Hexagon::XOR_rr_cPt :
1916 Hexagon::XOR_rr_cNotPt;
1917 case Hexagon::AND_rr:
1918 return !invertPredicate ? Hexagon::AND_rr_cPt :
1919 Hexagon::AND_rr_cNotPt;
1920 case Hexagon::OR_rr:
1921 return !invertPredicate ? Hexagon::OR_rr_cPt :
1922 Hexagon::OR_rr_cNotPt;
1923 case Hexagon::SUB_rr:
1924 return !invertPredicate ? Hexagon::SUB_rr_cPt :
1925 Hexagon::SUB_rr_cNotPt;
1926 case Hexagon::COMBINE_rr:
1927 return !invertPredicate ? Hexagon::COMBINE_rr_cPt :
1928 Hexagon::COMBINE_rr_cNotPt;
1930 return !invertPredicate ? Hexagon::ASLH_cPt_V4 :
1931 Hexagon::ASLH_cNotPt_V4;
1933 return !invertPredicate ? Hexagon::ASRH_cPt_V4 :
1934 Hexagon::ASRH_cNotPt_V4;
1936 return !invertPredicate ? Hexagon::SXTB_cPt_V4 :
1937 Hexagon::SXTB_cNotPt_V4;
1939 return !invertPredicate ? Hexagon::SXTH_cPt_V4 :
1940 Hexagon::SXTH_cNotPt_V4;
1942 return !invertPredicate ? Hexagon::ZXTB_cPt_V4 :
1943 Hexagon::ZXTB_cNotPt_V4;
1945 return !invertPredicate ? Hexagon::ZXTH_cPt_V4 :
1946 Hexagon::ZXTH_cNotPt_V4;
1949 return !invertPredicate ? Hexagon::JMPR_cPt :
1950 Hexagon::JMPR_cNotPt;
1952 // V4 indexed+scaled load.
1953 case Hexagon::LDrid_indexed_V4:
1954 return !invertPredicate ? Hexagon::LDrid_indexed_cPt_V4 :
1955 Hexagon::LDrid_indexed_cNotPt_V4;
1956 case Hexagon::LDrid_indexed_shl_V4:
1957 return !invertPredicate ? Hexagon::LDrid_indexed_shl_cPt_V4 :
1958 Hexagon::LDrid_indexed_shl_cNotPt_V4;
1959 case Hexagon::LDrib_indexed_V4:
1960 return !invertPredicate ? Hexagon::LDrib_indexed_cPt_V4 :
1961 Hexagon::LDrib_indexed_cNotPt_V4;
1962 case Hexagon::LDriub_indexed_V4:
1963 return !invertPredicate ? Hexagon::LDriub_indexed_cPt_V4 :
1964 Hexagon::LDriub_indexed_cNotPt_V4;
1965 case Hexagon::LDriub_ae_indexed_V4:
1966 return !invertPredicate ? Hexagon::LDriub_indexed_cPt_V4 :
1967 Hexagon::LDriub_indexed_cNotPt_V4;
1968 case Hexagon::LDrib_indexed_shl_V4:
1969 return !invertPredicate ? Hexagon::LDrib_indexed_shl_cPt_V4 :
1970 Hexagon::LDrib_indexed_shl_cNotPt_V4;
1971 case Hexagon::LDriub_indexed_shl_V4:
1972 return !invertPredicate ? Hexagon::LDriub_indexed_shl_cPt_V4 :
1973 Hexagon::LDriub_indexed_shl_cNotPt_V4;
1974 case Hexagon::LDriub_ae_indexed_shl_V4:
1975 return !invertPredicate ? Hexagon::LDriub_indexed_shl_cPt_V4 :
1976 Hexagon::LDriub_indexed_shl_cNotPt_V4;
1977 case Hexagon::LDrih_indexed_V4:
1978 return !invertPredicate ? Hexagon::LDrih_indexed_cPt_V4 :
1979 Hexagon::LDrih_indexed_cNotPt_V4;
1980 case Hexagon::LDriuh_indexed_V4:
1981 return !invertPredicate ? Hexagon::LDriuh_indexed_cPt_V4 :
1982 Hexagon::LDriuh_indexed_cNotPt_V4;
1983 case Hexagon::LDriuh_ae_indexed_V4:
1984 return !invertPredicate ? Hexagon::LDriuh_indexed_cPt_V4 :
1985 Hexagon::LDriuh_indexed_cNotPt_V4;
1986 case Hexagon::LDrih_indexed_shl_V4:
1987 return !invertPredicate ? Hexagon::LDrih_indexed_shl_cPt_V4 :
1988 Hexagon::LDrih_indexed_shl_cNotPt_V4;
1989 case Hexagon::LDriuh_indexed_shl_V4:
1990 return !invertPredicate ? Hexagon::LDriuh_indexed_shl_cPt_V4 :
1991 Hexagon::LDriuh_indexed_shl_cNotPt_V4;
1992 case Hexagon::LDriuh_ae_indexed_shl_V4:
1993 return !invertPredicate ? Hexagon::LDriuh_indexed_shl_cPt_V4 :
1994 Hexagon::LDriuh_indexed_shl_cNotPt_V4;
1995 case Hexagon::LDriw_indexed_V4:
1996 return !invertPredicate ? Hexagon::LDriw_indexed_cPt_V4 :
1997 Hexagon::LDriw_indexed_cNotPt_V4;
1998 case Hexagon::LDriw_indexed_shl_V4:
1999 return !invertPredicate ? Hexagon::LDriw_indexed_shl_cPt_V4 :
2000 Hexagon::LDriw_indexed_shl_cNotPt_V4;
2002 // V4 Load from global address
2003 case Hexagon::LDrid_GP_V4:
2004 return !invertPredicate ? Hexagon::LDrid_GP_cPt_V4 :
2005 Hexagon::LDrid_GP_cNotPt_V4;
2006 case Hexagon::LDrib_GP_V4:
2007 return !invertPredicate ? Hexagon::LDrib_GP_cPt_V4 :
2008 Hexagon::LDrib_GP_cNotPt_V4;
2009 case Hexagon::LDriub_GP_V4:
2010 return !invertPredicate ? Hexagon::LDriub_GP_cPt_V4 :
2011 Hexagon::LDriub_GP_cNotPt_V4;
2012 case Hexagon::LDrih_GP_V4:
2013 return !invertPredicate ? Hexagon::LDrih_GP_cPt_V4 :
2014 Hexagon::LDrih_GP_cNotPt_V4;
2015 case Hexagon::LDriuh_GP_V4:
2016 return !invertPredicate ? Hexagon::LDriuh_GP_cPt_V4 :
2017 Hexagon::LDriuh_GP_cNotPt_V4;
2018 case Hexagon::LDriw_GP_V4:
2019 return !invertPredicate ? Hexagon::LDriw_GP_cPt_V4 :
2020 Hexagon::LDriw_GP_cNotPt_V4;
2022 case Hexagon::LDd_GP_V4:
2023 return !invertPredicate ? Hexagon::LDd_GP_cPt_V4 :
2024 Hexagon::LDd_GP_cNotPt_V4;
2025 case Hexagon::LDb_GP_V4:
2026 return !invertPredicate ? Hexagon::LDb_GP_cPt_V4 :
2027 Hexagon::LDb_GP_cNotPt_V4;
2028 case Hexagon::LDub_GP_V4:
2029 return !invertPredicate ? Hexagon::LDub_GP_cPt_V4 :
2030 Hexagon::LDub_GP_cNotPt_V4;
2031 case Hexagon::LDh_GP_V4:
2032 return !invertPredicate ? Hexagon::LDh_GP_cPt_V4 :
2033 Hexagon::LDh_GP_cNotPt_V4;
2034 case Hexagon::LDuh_GP_V4:
2035 return !invertPredicate ? Hexagon::LDuh_GP_cPt_V4 :
2036 Hexagon::LDuh_GP_cNotPt_V4;
2037 case Hexagon::LDw_GP_V4:
2038 return !invertPredicate ? Hexagon::LDw_GP_cPt_V4 :
2039 Hexagon::LDw_GP_cNotPt_V4;
2042 case Hexagon::POST_STbri:
2043 return !invertPredicate ? Hexagon::POST_STbri_cPt :
2044 Hexagon::POST_STbri_cNotPt;
2045 case Hexagon::STrib:
2046 return !invertPredicate ? Hexagon::STrib_cPt :
2047 Hexagon::STrib_cNotPt;
2048 case Hexagon::STrib_indexed:
2049 return !invertPredicate ? Hexagon::STrib_indexed_cPt :
2050 Hexagon::STrib_indexed_cNotPt;
2051 case Hexagon::STrib_imm_V4:
2052 return !invertPredicate ? Hexagon::STrib_imm_cPt_V4 :
2053 Hexagon::STrib_imm_cNotPt_V4;
2054 case Hexagon::STrib_indexed_shl_V4:
2055 return !invertPredicate ? Hexagon::STrib_indexed_shl_cPt_V4 :
2056 Hexagon::STrib_indexed_shl_cNotPt_V4;
2058 case Hexagon::POST_SThri:
2059 return !invertPredicate ? Hexagon::POST_SThri_cPt :
2060 Hexagon::POST_SThri_cNotPt;
2061 case Hexagon::STrih:
2062 return !invertPredicate ? Hexagon::STrih_cPt :
2063 Hexagon::STrih_cNotPt;
2064 case Hexagon::STrih_indexed:
2065 return !invertPredicate ? Hexagon::STrih_indexed_cPt :
2066 Hexagon::STrih_indexed_cNotPt;
2067 case Hexagon::STrih_imm_V4:
2068 return !invertPredicate ? Hexagon::STrih_imm_cPt_V4 :
2069 Hexagon::STrih_imm_cNotPt_V4;
2070 case Hexagon::STrih_indexed_shl_V4:
2071 return !invertPredicate ? Hexagon::STrih_indexed_shl_cPt_V4 :
2072 Hexagon::STrih_indexed_shl_cNotPt_V4;
2074 case Hexagon::POST_STwri:
2075 return !invertPredicate ? Hexagon::POST_STwri_cPt :
2076 Hexagon::POST_STwri_cNotPt;
2077 case Hexagon::STriw:
2078 return !invertPredicate ? Hexagon::STriw_cPt :
2079 Hexagon::STriw_cNotPt;
2080 case Hexagon::STriw_indexed:
2081 return !invertPredicate ? Hexagon::STriw_indexed_cPt :
2082 Hexagon::STriw_indexed_cNotPt;
2083 case Hexagon::STriw_indexed_shl_V4:
2084 return !invertPredicate ? Hexagon::STriw_indexed_shl_cPt_V4 :
2085 Hexagon::STriw_indexed_shl_cNotPt_V4;
2086 case Hexagon::STriw_imm_V4:
2087 return !invertPredicate ? Hexagon::STriw_imm_cPt_V4 :
2088 Hexagon::STriw_imm_cNotPt_V4;
2090 case Hexagon::POST_STdri:
2091 return !invertPredicate ? Hexagon::POST_STdri_cPt :
2092 Hexagon::POST_STdri_cNotPt;
2093 case Hexagon::STrid:
2094 return !invertPredicate ? Hexagon::STrid_cPt :
2095 Hexagon::STrid_cNotPt;
2096 case Hexagon::STrid_indexed:
2097 return !invertPredicate ? Hexagon::STrid_indexed_cPt :
2098 Hexagon::STrid_indexed_cNotPt;
2099 case Hexagon::STrid_indexed_shl_V4:
2100 return !invertPredicate ? Hexagon::STrid_indexed_shl_cPt_V4 :
2101 Hexagon::STrid_indexed_shl_cNotPt_V4;
2103 // V4 Store to global address
2104 case Hexagon::STrid_GP_V4:
2105 return !invertPredicate ? Hexagon::STrid_GP_cPt_V4 :
2106 Hexagon::STrid_GP_cNotPt_V4;
2107 case Hexagon::STrib_GP_V4:
2108 return !invertPredicate ? Hexagon::STrib_GP_cPt_V4 :
2109 Hexagon::STrib_GP_cNotPt_V4;
2110 case Hexagon::STrih_GP_V4:
2111 return !invertPredicate ? Hexagon::STrih_GP_cPt_V4 :
2112 Hexagon::STrih_GP_cNotPt_V4;
2113 case Hexagon::STriw_GP_V4:
2114 return !invertPredicate ? Hexagon::STriw_GP_cPt_V4 :
2115 Hexagon::STriw_GP_cNotPt_V4;
2117 case Hexagon::STd_GP_V4:
2118 return !invertPredicate ? Hexagon::STd_GP_cPt_V4 :
2119 Hexagon::STd_GP_cNotPt_V4;
2120 case Hexagon::STb_GP_V4:
2121 return !invertPredicate ? Hexagon::STb_GP_cPt_V4 :
2122 Hexagon::STb_GP_cNotPt_V4;
2123 case Hexagon::STh_GP_V4:
2124 return !invertPredicate ? Hexagon::STh_GP_cPt_V4 :
2125 Hexagon::STh_GP_cNotPt_V4;
2126 case Hexagon::STw_GP_V4:
2127 return !invertPredicate ? Hexagon::STw_GP_cPt_V4 :
2128 Hexagon::STw_GP_cNotPt_V4;
2131 case Hexagon::LDrid:
2132 return !invertPredicate ? Hexagon::LDrid_cPt :
2133 Hexagon::LDrid_cNotPt;
2134 case Hexagon::LDriw:
2135 return !invertPredicate ? Hexagon::LDriw_cPt :
2136 Hexagon::LDriw_cNotPt;
2137 case Hexagon::LDrih:
2138 return !invertPredicate ? Hexagon::LDrih_cPt :
2139 Hexagon::LDrih_cNotPt;
2140 case Hexagon::LDriuh:
2141 return !invertPredicate ? Hexagon::LDriuh_cPt :
2142 Hexagon::LDriuh_cNotPt;
2143 case Hexagon::LDrib:
2144 return !invertPredicate ? Hexagon::LDrib_cPt :
2145 Hexagon::LDrib_cNotPt;
2146 case Hexagon::LDriub:
2147 return !invertPredicate ? Hexagon::LDriub_cPt :
2148 Hexagon::LDriub_cNotPt;
2150 case Hexagon::LDrid_indexed:
2151 return !invertPredicate ? Hexagon::LDrid_indexed_cPt :
2152 Hexagon::LDrid_indexed_cNotPt;
2153 case Hexagon::LDriw_indexed:
2154 return !invertPredicate ? Hexagon::LDriw_indexed_cPt :
2155 Hexagon::LDriw_indexed_cNotPt;
2156 case Hexagon::LDrih_indexed:
2157 return !invertPredicate ? Hexagon::LDrih_indexed_cPt :
2158 Hexagon::LDrih_indexed_cNotPt;
2159 case Hexagon::LDriuh_indexed:
2160 return !invertPredicate ? Hexagon::LDriuh_indexed_cPt :
2161 Hexagon::LDriuh_indexed_cNotPt;
2162 case Hexagon::LDrib_indexed:
2163 return !invertPredicate ? Hexagon::LDrib_indexed_cPt :
2164 Hexagon::LDrib_indexed_cNotPt;
2165 case Hexagon::LDriub_indexed:
2166 return !invertPredicate ? Hexagon::LDriub_indexed_cPt :
2167 Hexagon::LDriub_indexed_cNotPt;
2168 // Post Increment Load.
2169 case Hexagon::POST_LDrid:
2170 return !invertPredicate ? Hexagon::POST_LDrid_cPt :
2171 Hexagon::POST_LDrid_cNotPt;
2172 case Hexagon::POST_LDriw:
2173 return !invertPredicate ? Hexagon::POST_LDriw_cPt :
2174 Hexagon::POST_LDriw_cNotPt;
2175 case Hexagon::POST_LDrih:
2176 return !invertPredicate ? Hexagon::POST_LDrih_cPt :
2177 Hexagon::POST_LDrih_cNotPt;
2178 case Hexagon::POST_LDriuh:
2179 return !invertPredicate ? Hexagon::POST_LDriuh_cPt :
2180 Hexagon::POST_LDriuh_cNotPt;
2181 case Hexagon::POST_LDrib:
2182 return !invertPredicate ? Hexagon::POST_LDrib_cPt :
2183 Hexagon::POST_LDrib_cNotPt;
2184 case Hexagon::POST_LDriub:
2185 return !invertPredicate ? Hexagon::POST_LDriub_cPt :
2186 Hexagon::POST_LDriub_cNotPt;
2188 case Hexagon::DEALLOC_RET_V4:
2189 return !invertPredicate ? Hexagon::DEALLOC_RET_cPt_V4 :
2190 Hexagon::DEALLOC_RET_cNotPt_V4;
2192 llvm_unreachable("Unexpected predicable instruction");
2196 bool HexagonInstrInfo::
2197 PredicateInstruction(MachineInstr *MI,
2198 const SmallVectorImpl<MachineOperand> &Cond) const {
2199 int Opc = MI->getOpcode();
2200 assert (isPredicable(MI) && "Expected predicable instruction");
2201 bool invertJump = (!Cond.empty() && Cond[0].isImm() &&
2202 (Cond[0].getImm() == 0));
2203 MI->setDesc(get(getMatchingCondBranchOpcode(Opc, invertJump)));
2205 // This assumes that the predicate is always the first operand
2206 // in the set of inputs.
2208 MI->addOperand(MI->getOperand(MI->getNumOperands()-1));
2210 for (oper = MI->getNumOperands() - 3; oper >= 0; --oper) {
2211 MachineOperand MO = MI->getOperand(oper);
2212 if ((MO.isReg() && !MO.isUse() && !MO.isImplicit())) {
2217 MI->getOperand(oper+1).ChangeToRegister(MO.getReg(), MO.isDef(),
2218 MO.isImplicit(), MO.isKill(),
2219 MO.isDead(), MO.isUndef(),
2221 } else if (MO.isImm()) {
2222 MI->getOperand(oper+1).ChangeToImmediate(MO.getImm());
2224 llvm_unreachable("Unexpected operand type");
2228 int regPos = invertJump ? 1 : 0;
2229 MachineOperand PredMO = Cond[regPos];
2230 MI->getOperand(oper+1).ChangeToRegister(PredMO.getReg(), PredMO.isDef(),
2231 PredMO.isImplicit(), PredMO.isKill(),
2232 PredMO.isDead(), PredMO.isUndef(),
2241 isProfitableToIfCvt(MachineBasicBlock &MBB,
2243 unsigned ExtraPredCycles,
2244 const BranchProbability &Probability) const {
2251 isProfitableToIfCvt(MachineBasicBlock &TMBB,
2252 unsigned NumTCycles,
2253 unsigned ExtraTCycles,
2254 MachineBasicBlock &FMBB,
2255 unsigned NumFCycles,
2256 unsigned ExtraFCycles,
2257 const BranchProbability &Probability) const {
2262 bool HexagonInstrInfo::isPredicated(const MachineInstr *MI) const {
2263 const uint64_t F = MI->getDesc().TSFlags;
2265 return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
2269 HexagonInstrInfo::DefinesPredicate(MachineInstr *MI,
2270 std::vector<MachineOperand> &Pred) const {
2271 for (unsigned oper = 0; oper < MI->getNumOperands(); ++oper) {
2272 MachineOperand MO = MI->getOperand(oper);
2273 if (MO.isReg() && MO.isDef()) {
2274 const TargetRegisterClass* RC = RI.getMinimalPhysRegClass(MO.getReg());
2275 if (RC == &Hexagon::PredRegsRegClass) {
2287 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
2288 const SmallVectorImpl<MachineOperand> &Pred2) const {
2295 // We indicate that we want to reverse the branch by
2296 // inserting a 0 at the beginning of the Cond vector.
2298 bool HexagonInstrInfo::
2299 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
2300 if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) {
2301 Cond.erase(Cond.begin());
2303 Cond.insert(Cond.begin(), MachineOperand::CreateImm(0));
2309 bool HexagonInstrInfo::
2310 isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumInstrs,
2311 const BranchProbability &Probability) const {
2312 return (NumInstrs <= 4);
2315 bool HexagonInstrInfo::isDeallocRet(const MachineInstr *MI) const {
2316 switch (MI->getOpcode()) {
2317 default: return false;
2318 case Hexagon::DEALLOC_RET_V4 :
2319 case Hexagon::DEALLOC_RET_cPt_V4 :
2320 case Hexagon::DEALLOC_RET_cNotPt_V4 :
2321 case Hexagon::DEALLOC_RET_cdnPnt_V4 :
2322 case Hexagon::DEALLOC_RET_cNotdnPnt_V4 :
2323 case Hexagon::DEALLOC_RET_cdnPt_V4 :
2324 case Hexagon::DEALLOC_RET_cNotdnPt_V4 :
2330 bool HexagonInstrInfo::
2331 isValidOffset(const int Opcode, const int Offset) const {
2332 // This function is to check whether the "Offset" is in the correct range of
2333 // the given "Opcode". If "Offset" is not in the correct range, "ADD_ri" is
2334 // inserted to calculate the final address. Due to this reason, the function
2335 // assumes that the "Offset" has correct alignment.
2339 case Hexagon::LDriw:
2340 case Hexagon::STriw:
2341 assert((Offset % 4 == 0) && "Offset has incorrect alignment");
2342 return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
2343 (Offset <= Hexagon_MEMW_OFFSET_MAX);
2345 case Hexagon::LDrid:
2346 case Hexagon::STrid:
2347 assert((Offset % 8 == 0) && "Offset has incorrect alignment");
2348 return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
2349 (Offset <= Hexagon_MEMD_OFFSET_MAX);
2351 case Hexagon::LDrih:
2352 case Hexagon::LDriuh:
2353 case Hexagon::STrih:
2354 assert((Offset % 2 == 0) && "Offset has incorrect alignment");
2355 return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
2356 (Offset <= Hexagon_MEMH_OFFSET_MAX);
2358 case Hexagon::LDrib:
2359 case Hexagon::STrib:
2360 case Hexagon::LDriub:
2361 return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
2362 (Offset <= Hexagon_MEMB_OFFSET_MAX);
2364 case Hexagon::ADD_ri:
2365 case Hexagon::TFR_FI:
2366 return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
2367 (Offset <= Hexagon_ADDI_OFFSET_MAX);
2369 case Hexagon::MEMw_ADDSUBi_indexed_MEM_V4 :
2370 case Hexagon::MEMw_ADDi_indexed_MEM_V4 :
2371 case Hexagon::MEMw_SUBi_indexed_MEM_V4 :
2372 case Hexagon::MEMw_ADDr_indexed_MEM_V4 :
2373 case Hexagon::MEMw_SUBr_indexed_MEM_V4 :
2374 case Hexagon::MEMw_ANDr_indexed_MEM_V4 :
2375 case Hexagon::MEMw_ORr_indexed_MEM_V4 :
2376 case Hexagon::MEMw_ADDSUBi_MEM_V4 :
2377 case Hexagon::MEMw_ADDi_MEM_V4 :
2378 case Hexagon::MEMw_SUBi_MEM_V4 :
2379 case Hexagon::MEMw_ADDr_MEM_V4 :
2380 case Hexagon::MEMw_SUBr_MEM_V4 :
2381 case Hexagon::MEMw_ANDr_MEM_V4 :
2382 case Hexagon::MEMw_ORr_MEM_V4 :
2383 assert ((Offset % 4) == 0 && "MEMOPw offset is not aligned correctly." );
2384 return (0 <= Offset && Offset <= 255);
2386 case Hexagon::MEMh_ADDSUBi_indexed_MEM_V4 :
2387 case Hexagon::MEMh_ADDi_indexed_MEM_V4 :
2388 case Hexagon::MEMh_SUBi_indexed_MEM_V4 :
2389 case Hexagon::MEMh_ADDr_indexed_MEM_V4 :
2390 case Hexagon::MEMh_SUBr_indexed_MEM_V4 :
2391 case Hexagon::MEMh_ANDr_indexed_MEM_V4 :
2392 case Hexagon::MEMh_ORr_indexed_MEM_V4 :
2393 case Hexagon::MEMh_ADDSUBi_MEM_V4 :
2394 case Hexagon::MEMh_ADDi_MEM_V4 :
2395 case Hexagon::MEMh_SUBi_MEM_V4 :
2396 case Hexagon::MEMh_ADDr_MEM_V4 :
2397 case Hexagon::MEMh_SUBr_MEM_V4 :
2398 case Hexagon::MEMh_ANDr_MEM_V4 :
2399 case Hexagon::MEMh_ORr_MEM_V4 :
2400 assert ((Offset % 2) == 0 && "MEMOPh offset is not aligned correctly." );
2401 return (0 <= Offset && Offset <= 127);
2403 case Hexagon::MEMb_ADDSUBi_indexed_MEM_V4 :
2404 case Hexagon::MEMb_ADDi_indexed_MEM_V4 :
2405 case Hexagon::MEMb_SUBi_indexed_MEM_V4 :
2406 case Hexagon::MEMb_ADDr_indexed_MEM_V4 :
2407 case Hexagon::MEMb_SUBr_indexed_MEM_V4 :
2408 case Hexagon::MEMb_ANDr_indexed_MEM_V4 :
2409 case Hexagon::MEMb_ORr_indexed_MEM_V4 :
2410 case Hexagon::MEMb_ADDSUBi_MEM_V4 :
2411 case Hexagon::MEMb_ADDi_MEM_V4 :
2412 case Hexagon::MEMb_SUBi_MEM_V4 :
2413 case Hexagon::MEMb_ADDr_MEM_V4 :
2414 case Hexagon::MEMb_SUBr_MEM_V4 :
2415 case Hexagon::MEMb_ANDr_MEM_V4 :
2416 case Hexagon::MEMb_ORr_MEM_V4 :
2417 return (0 <= Offset && Offset <= 63);
2419 // LDri_pred and STriw_pred are pseudo operations, so it has to take offset of
2420 // any size. Later pass knows how to handle it.
2421 case Hexagon::STriw_pred:
2422 case Hexagon::LDriw_pred:
2425 // INLINEASM is very special.
2426 case Hexagon::INLINEASM:
2430 llvm_unreachable("No offset range is defined for this opcode. "
2431 "Please define it in the above switch statement!");
2436 // Check if the Offset is a valid auto-inc imm by Load/Store Type.
2438 bool HexagonInstrInfo::
2439 isValidAutoIncImm(const EVT VT, const int Offset) const {
2441 if (VT == MVT::i64) {
2442 return (Offset >= Hexagon_MEMD_AUTOINC_MIN &&
2443 Offset <= Hexagon_MEMD_AUTOINC_MAX &&
2444 (Offset & 0x7) == 0);
2446 if (VT == MVT::i32) {
2447 return (Offset >= Hexagon_MEMW_AUTOINC_MIN &&
2448 Offset <= Hexagon_MEMW_AUTOINC_MAX &&
2449 (Offset & 0x3) == 0);
2451 if (VT == MVT::i16) {
2452 return (Offset >= Hexagon_MEMH_AUTOINC_MIN &&
2453 Offset <= Hexagon_MEMH_AUTOINC_MAX &&
2454 (Offset & 0x1) == 0);
2456 if (VT == MVT::i8) {
2457 return (Offset >= Hexagon_MEMB_AUTOINC_MIN &&
2458 Offset <= Hexagon_MEMB_AUTOINC_MAX);
2460 llvm_unreachable("Not an auto-inc opc!");
2464 bool HexagonInstrInfo::
2465 isMemOp(const MachineInstr *MI) const {
2466 switch (MI->getOpcode())
2468 default: return false;
2469 case Hexagon::MEMw_ADDSUBi_indexed_MEM_V4 :
2470 case Hexagon::MEMw_ADDi_indexed_MEM_V4 :
2471 case Hexagon::MEMw_SUBi_indexed_MEM_V4 :
2472 case Hexagon::MEMw_ADDr_indexed_MEM_V4 :
2473 case Hexagon::MEMw_SUBr_indexed_MEM_V4 :
2474 case Hexagon::MEMw_ANDr_indexed_MEM_V4 :
2475 case Hexagon::MEMw_ORr_indexed_MEM_V4 :
2476 case Hexagon::MEMw_ADDSUBi_MEM_V4 :
2477 case Hexagon::MEMw_ADDi_MEM_V4 :
2478 case Hexagon::MEMw_SUBi_MEM_V4 :
2479 case Hexagon::MEMw_ADDr_MEM_V4 :
2480 case Hexagon::MEMw_SUBr_MEM_V4 :
2481 case Hexagon::MEMw_ANDr_MEM_V4 :
2482 case Hexagon::MEMw_ORr_MEM_V4 :
2483 case Hexagon::MEMh_ADDSUBi_indexed_MEM_V4 :
2484 case Hexagon::MEMh_ADDi_indexed_MEM_V4 :
2485 case Hexagon::MEMh_SUBi_indexed_MEM_V4 :
2486 case Hexagon::MEMh_ADDr_indexed_MEM_V4 :
2487 case Hexagon::MEMh_SUBr_indexed_MEM_V4 :
2488 case Hexagon::MEMh_ANDr_indexed_MEM_V4 :
2489 case Hexagon::MEMh_ORr_indexed_MEM_V4 :
2490 case Hexagon::MEMh_ADDSUBi_MEM_V4 :
2491 case Hexagon::MEMh_ADDi_MEM_V4 :
2492 case Hexagon::MEMh_SUBi_MEM_V4 :
2493 case Hexagon::MEMh_ADDr_MEM_V4 :
2494 case Hexagon::MEMh_SUBr_MEM_V4 :
2495 case Hexagon::MEMh_ANDr_MEM_V4 :
2496 case Hexagon::MEMh_ORr_MEM_V4 :
2497 case Hexagon::MEMb_ADDSUBi_indexed_MEM_V4 :
2498 case Hexagon::MEMb_ADDi_indexed_MEM_V4 :
2499 case Hexagon::MEMb_SUBi_indexed_MEM_V4 :
2500 case Hexagon::MEMb_ADDr_indexed_MEM_V4 :
2501 case Hexagon::MEMb_SUBr_indexed_MEM_V4 :
2502 case Hexagon::MEMb_ANDr_indexed_MEM_V4 :
2503 case Hexagon::MEMb_ORr_indexed_MEM_V4 :
2504 case Hexagon::MEMb_ADDSUBi_MEM_V4 :
2505 case Hexagon::MEMb_ADDi_MEM_V4 :
2506 case Hexagon::MEMb_SUBi_MEM_V4 :
2507 case Hexagon::MEMb_ADDr_MEM_V4 :
2508 case Hexagon::MEMb_SUBr_MEM_V4 :
2509 case Hexagon::MEMb_ANDr_MEM_V4 :
2510 case Hexagon::MEMb_ORr_MEM_V4 :
2516 bool HexagonInstrInfo::
2517 isSpillPredRegOp(const MachineInstr *MI) const {
2518 switch (MI->getOpcode()) {
2519 default: return false;
2520 case Hexagon::STriw_pred :
2521 case Hexagon::LDriw_pred :
2526 bool HexagonInstrInfo::isNewValueJumpCandidate(const MachineInstr *MI) const {
2527 switch (MI->getOpcode()) {
2528 case Hexagon::CMPEQrr:
2529 case Hexagon::CMPEQri:
2530 case Hexagon::CMPLTrr:
2531 case Hexagon::CMPGTrr:
2532 case Hexagon::CMPGTri:
2533 case Hexagon::CMPLTUrr:
2534 case Hexagon::CMPGTUrr:
2535 case Hexagon::CMPGTUri:
2536 case Hexagon::CMPGEri:
2537 case Hexagon::CMPGEUri:
2546 bool HexagonInstrInfo::
2547 isConditionalTransfer (const MachineInstr *MI) const {
2548 switch (MI->getOpcode()) {
2549 default: return false;
2550 case Hexagon::TFR_cPt:
2551 case Hexagon::TFR_cNotPt:
2552 case Hexagon::TFRI_cPt:
2553 case Hexagon::TFRI_cNotPt:
2554 case Hexagon::TFR_cdnPt:
2555 case Hexagon::TFR_cdnNotPt:
2556 case Hexagon::TFRI_cdnPt:
2557 case Hexagon::TFRI_cdnNotPt:
2562 bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const {
2563 const HexagonRegisterInfo& QRI = getRegisterInfo();
2564 switch (MI->getOpcode())
2566 default: return false;
2567 case Hexagon::ADD_ri_cPt:
2568 case Hexagon::ADD_ri_cNotPt:
2569 case Hexagon::ADD_rr_cPt:
2570 case Hexagon::ADD_rr_cNotPt:
2571 case Hexagon::XOR_rr_cPt:
2572 case Hexagon::XOR_rr_cNotPt:
2573 case Hexagon::AND_rr_cPt:
2574 case Hexagon::AND_rr_cNotPt:
2575 case Hexagon::OR_rr_cPt:
2576 case Hexagon::OR_rr_cNotPt:
2577 case Hexagon::SUB_rr_cPt:
2578 case Hexagon::SUB_rr_cNotPt:
2579 case Hexagon::COMBINE_rr_cPt:
2580 case Hexagon::COMBINE_rr_cNotPt:
2582 case Hexagon::ASLH_cPt_V4:
2583 case Hexagon::ASLH_cNotPt_V4:
2584 case Hexagon::ASRH_cPt_V4:
2585 case Hexagon::ASRH_cNotPt_V4:
2586 case Hexagon::SXTB_cPt_V4:
2587 case Hexagon::SXTB_cNotPt_V4:
2588 case Hexagon::SXTH_cPt_V4:
2589 case Hexagon::SXTH_cNotPt_V4:
2590 case Hexagon::ZXTB_cPt_V4:
2591 case Hexagon::ZXTB_cNotPt_V4:
2592 case Hexagon::ZXTH_cPt_V4:
2593 case Hexagon::ZXTH_cNotPt_V4:
2594 return QRI.Subtarget.hasV4TOps();
2598 bool HexagonInstrInfo::
2599 isConditionalLoad (const MachineInstr* MI) const {
2600 const HexagonRegisterInfo& QRI = getRegisterInfo();
2601 switch (MI->getOpcode())
2603 default: return false;
2604 case Hexagon::LDrid_cPt :
2605 case Hexagon::LDrid_cNotPt :
2606 case Hexagon::LDrid_indexed_cPt :
2607 case Hexagon::LDrid_indexed_cNotPt :
2608 case Hexagon::LDriw_cPt :
2609 case Hexagon::LDriw_cNotPt :
2610 case Hexagon::LDriw_indexed_cPt :
2611 case Hexagon::LDriw_indexed_cNotPt :
2612 case Hexagon::LDrih_cPt :
2613 case Hexagon::LDrih_cNotPt :
2614 case Hexagon::LDrih_indexed_cPt :
2615 case Hexagon::LDrih_indexed_cNotPt :
2616 case Hexagon::LDrib_cPt :
2617 case Hexagon::LDrib_cNotPt :
2618 case Hexagon::LDrib_indexed_cPt :
2619 case Hexagon::LDrib_indexed_cNotPt :
2620 case Hexagon::LDriuh_cPt :
2621 case Hexagon::LDriuh_cNotPt :
2622 case Hexagon::LDriuh_indexed_cPt :
2623 case Hexagon::LDriuh_indexed_cNotPt :
2624 case Hexagon::LDriub_cPt :
2625 case Hexagon::LDriub_cNotPt :
2626 case Hexagon::LDriub_indexed_cPt :
2627 case Hexagon::LDriub_indexed_cNotPt :
2629 case Hexagon::POST_LDrid_cPt :
2630 case Hexagon::POST_LDrid_cNotPt :
2631 case Hexagon::POST_LDriw_cPt :
2632 case Hexagon::POST_LDriw_cNotPt :
2633 case Hexagon::POST_LDrih_cPt :
2634 case Hexagon::POST_LDrih_cNotPt :
2635 case Hexagon::POST_LDrib_cPt :
2636 case Hexagon::POST_LDrib_cNotPt :
2637 case Hexagon::POST_LDriuh_cPt :
2638 case Hexagon::POST_LDriuh_cNotPt :
2639 case Hexagon::POST_LDriub_cPt :
2640 case Hexagon::POST_LDriub_cNotPt :
2641 return QRI.Subtarget.hasV4TOps();
2642 case Hexagon::LDrid_indexed_cPt_V4 :
2643 case Hexagon::LDrid_indexed_cNotPt_V4 :
2644 case Hexagon::LDrid_indexed_shl_cPt_V4 :
2645 case Hexagon::LDrid_indexed_shl_cNotPt_V4 :
2646 case Hexagon::LDrib_indexed_cPt_V4 :
2647 case Hexagon::LDrib_indexed_cNotPt_V4 :
2648 case Hexagon::LDrib_indexed_shl_cPt_V4 :
2649 case Hexagon::LDrib_indexed_shl_cNotPt_V4 :
2650 case Hexagon::LDriub_indexed_cPt_V4 :
2651 case Hexagon::LDriub_indexed_cNotPt_V4 :
2652 case Hexagon::LDriub_indexed_shl_cPt_V4 :
2653 case Hexagon::LDriub_indexed_shl_cNotPt_V4 :
2654 case Hexagon::LDrih_indexed_cPt_V4 :
2655 case Hexagon::LDrih_indexed_cNotPt_V4 :
2656 case Hexagon::LDrih_indexed_shl_cPt_V4 :
2657 case Hexagon::LDrih_indexed_shl_cNotPt_V4 :
2658 case Hexagon::LDriuh_indexed_cPt_V4 :
2659 case Hexagon::LDriuh_indexed_cNotPt_V4 :
2660 case Hexagon::LDriuh_indexed_shl_cPt_V4 :
2661 case Hexagon::LDriuh_indexed_shl_cNotPt_V4 :
2662 case Hexagon::LDriw_indexed_cPt_V4 :
2663 case Hexagon::LDriw_indexed_cNotPt_V4 :
2664 case Hexagon::LDriw_indexed_shl_cPt_V4 :
2665 case Hexagon::LDriw_indexed_shl_cNotPt_V4 :
2666 return QRI.Subtarget.hasV4TOps();
2670 // Returns true if an instruction is a conditional store.
2672 // Note: It doesn't include conditional new-value stores as they can't be
2673 // converted to .new predicate.
2675 // p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ]
2677 // / \ (not OK. it will cause new-value store to be
2678 // / X conditional on p0.new while R2 producer is
2681 // p.new store p.old NV store
2682 // [if(p0.new)memw(R0+#0)=R2] [if(p0)memw(R0+#0)=R2.new]
2688 // [if (p0)memw(R0+#0)=R2]
2690 // The above diagram shows the steps involoved in the conversion of a predicated
2691 // store instruction to its .new predicated new-value form.
2693 // The following set of instructions further explains the scenario where
2694 // conditional new-value store becomes invalid when promoted to .new predicate
2697 // { 1) if (p0) r0 = add(r1, r2)
2698 // 2) p0 = cmp.eq(r3, #0) }
2700 // 3) if (p0) memb(r1+#0) = r0 --> this instruction can't be grouped with
2701 // the first two instructions because in instr 1, r0 is conditional on old value
2702 // of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which
2703 // is not valid for new-value stores.
2704 bool HexagonInstrInfo::
2705 isConditionalStore (const MachineInstr* MI) const {
2706 const HexagonRegisterInfo& QRI = getRegisterInfo();
2707 switch (MI->getOpcode())
2709 default: return false;
2710 case Hexagon::STrib_imm_cPt_V4 :
2711 case Hexagon::STrib_imm_cNotPt_V4 :
2712 case Hexagon::STrib_indexed_shl_cPt_V4 :
2713 case Hexagon::STrib_indexed_shl_cNotPt_V4 :
2714 case Hexagon::STrib_cPt :
2715 case Hexagon::STrib_cNotPt :
2716 case Hexagon::POST_STbri_cPt :
2717 case Hexagon::POST_STbri_cNotPt :
2718 case Hexagon::STrid_indexed_cPt :
2719 case Hexagon::STrid_indexed_cNotPt :
2720 case Hexagon::STrid_indexed_shl_cPt_V4 :
2721 case Hexagon::POST_STdri_cPt :
2722 case Hexagon::POST_STdri_cNotPt :
2723 case Hexagon::STrih_cPt :
2724 case Hexagon::STrih_cNotPt :
2725 case Hexagon::STrih_indexed_cPt :
2726 case Hexagon::STrih_indexed_cNotPt :
2727 case Hexagon::STrih_imm_cPt_V4 :
2728 case Hexagon::STrih_imm_cNotPt_V4 :
2729 case Hexagon::STrih_indexed_shl_cPt_V4 :
2730 case Hexagon::STrih_indexed_shl_cNotPt_V4 :
2731 case Hexagon::POST_SThri_cPt :
2732 case Hexagon::POST_SThri_cNotPt :
2733 case Hexagon::STriw_cPt :
2734 case Hexagon::STriw_cNotPt :
2735 case Hexagon::STriw_indexed_cPt :
2736 case Hexagon::STriw_indexed_cNotPt :
2737 case Hexagon::STriw_imm_cPt_V4 :
2738 case Hexagon::STriw_imm_cNotPt_V4 :
2739 case Hexagon::STriw_indexed_shl_cPt_V4 :
2740 case Hexagon::STriw_indexed_shl_cNotPt_V4 :
2741 case Hexagon::POST_STwri_cPt :
2742 case Hexagon::POST_STwri_cNotPt :
2743 return QRI.Subtarget.hasV4TOps();
2745 // V4 global address store before promoting to dot new.
2746 case Hexagon::STrid_GP_cPt_V4 :
2747 case Hexagon::STrid_GP_cNotPt_V4 :
2748 case Hexagon::STrib_GP_cPt_V4 :
2749 case Hexagon::STrib_GP_cNotPt_V4 :
2750 case Hexagon::STrih_GP_cPt_V4 :
2751 case Hexagon::STrih_GP_cNotPt_V4 :
2752 case Hexagon::STriw_GP_cPt_V4 :
2753 case Hexagon::STriw_GP_cNotPt_V4 :
2754 case Hexagon::STd_GP_cPt_V4 :
2755 case Hexagon::STd_GP_cNotPt_V4 :
2756 case Hexagon::STb_GP_cPt_V4 :
2757 case Hexagon::STb_GP_cNotPt_V4 :
2758 case Hexagon::STh_GP_cPt_V4 :
2759 case Hexagon::STh_GP_cNotPt_V4 :
2760 case Hexagon::STw_GP_cPt_V4 :
2761 case Hexagon::STw_GP_cNotPt_V4 :
2762 return QRI.Subtarget.hasV4TOps();
2764 // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
2765 // from the "Conditional Store" list. Because a predicated new value store
2766 // would NOT be promoted to a double dot new store. See diagram below:
2767 // This function returns yes for those stores that are predicated but not
2768 // yet promoted to predicate dot new instructions.
2770 // +---------------------+
2771 // /-----| if (p0) memw(..)=r0 |---------\~
2772 // || +---------------------+ ||
2773 // promote || /\ /\ || promote
2775 // \||/ demote || \||/
2777 // +-------------------------+ || +-------------------------+
2778 // | if (p0.new) memw(..)=r0 | || | if (p0) memw(..)=r0.new |
2779 // +-------------------------+ || +-------------------------+
2782 // promote || \/ NOT possible
2786 // +-----------------------------+
2787 // | if (p0.new) memw(..)=r0.new |
2788 // +-----------------------------+
2789 // Double Dot New Store
2796 DFAPacketizer *HexagonInstrInfo::
2797 CreateTargetScheduleState(const TargetMachine *TM,
2798 const ScheduleDAG *DAG) const {
2799 const InstrItineraryData *II = TM->getInstrItineraryData();
2800 return TM->getSubtarget<HexagonGenSubtargetInfo>().createDFAPacketizer(II);
2803 bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
2804 const MachineBasicBlock *MBB,
2805 const MachineFunction &MF) const {
2806 // Debug info is never a scheduling boundary. It's necessary to be explicit
2807 // due to the special treatment of IT instructions below, otherwise a
2808 // dbg_value followed by an IT will result in the IT instruction being
2809 // considered a scheduling hazard, which is wrong. It should be the actual
2810 // instruction preceding the dbg_value instruction(s), just like it is
2811 // when debug info is not present.
2812 if (MI->isDebugValue())
2815 // Terminators and labels can't be scheduled around.
2816 if (MI->getDesc().isTerminator() || MI->isLabel() || MI->isInlineAsm())