1 //===-- HexagonInstrInfo.cpp - Hexagon Instruction Information ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Hexagon implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "HexagonInstrInfo.h"
16 #include "HexagonRegisterInfo.h"
17 #include "HexagonSubtarget.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/CodeGen/DFAPacketizer.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineMemOperand.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/PseudoSourceValue.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/MathExtras.h"
28 #include "llvm/Support/raw_ostream.h"
32 #define DEBUG_TYPE "hexagon-instrinfo"
34 #define GET_INSTRINFO_CTOR_DTOR
35 #define GET_INSTRMAP_INFO
36 #include "HexagonGenInstrInfo.inc"
37 #include "HexagonGenDFAPacketizer.inc"
40 /// Constants for Hexagon instructions.
42 const int Hexagon_MEMW_OFFSET_MAX = 4095;
43 const int Hexagon_MEMW_OFFSET_MIN = -4096;
44 const int Hexagon_MEMD_OFFSET_MAX = 8191;
45 const int Hexagon_MEMD_OFFSET_MIN = -8192;
46 const int Hexagon_MEMH_OFFSET_MAX = 2047;
47 const int Hexagon_MEMH_OFFSET_MIN = -2048;
48 const int Hexagon_MEMB_OFFSET_MAX = 1023;
49 const int Hexagon_MEMB_OFFSET_MIN = -1024;
50 const int Hexagon_ADDI_OFFSET_MAX = 32767;
51 const int Hexagon_ADDI_OFFSET_MIN = -32768;
52 const int Hexagon_MEMD_AUTOINC_MAX = 56;
53 const int Hexagon_MEMD_AUTOINC_MIN = -64;
54 const int Hexagon_MEMW_AUTOINC_MAX = 28;
55 const int Hexagon_MEMW_AUTOINC_MIN = -32;
56 const int Hexagon_MEMH_AUTOINC_MAX = 14;
57 const int Hexagon_MEMH_AUTOINC_MIN = -16;
58 const int Hexagon_MEMB_AUTOINC_MAX = 7;
59 const int Hexagon_MEMB_AUTOINC_MIN = -8;
61 // Pin the vtable to this file.
62 void HexagonInstrInfo::anchor() {}
64 HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST)
65 : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
66 RI(ST), Subtarget(ST) {
70 /// isLoadFromStackSlot - If the specified machine instruction is a direct
71 /// load from a stack slot, return the virtual or physical register number of
72 /// the destination along with the FrameIndex of the loaded stack slot. If
73 /// not, return 0. This predicate must return 0 if the instruction has
74 /// any side effects other than loading from the stack slot.
75 unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
76 int &FrameIndex) const {
79 switch (MI->getOpcode()) {
81 case Hexagon::L2_loadri_io:
82 case Hexagon::L2_loadrd_io:
83 case Hexagon::L2_loadrh_io:
84 case Hexagon::L2_loadrb_io:
85 case Hexagon::L2_loadrub_io:
86 if (MI->getOperand(2).isFI() &&
87 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
88 FrameIndex = MI->getOperand(2).getIndex();
89 return MI->getOperand(0).getReg();
97 /// isStoreToStackSlot - If the specified machine instruction is a direct
98 /// store to a stack slot, return the virtual or physical register number of
99 /// the source reg along with the FrameIndex of the loaded stack slot. If
100 /// not, return 0. This predicate must return 0 if the instruction has
101 /// any side effects other than storing to the stack slot.
102 unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
103 int &FrameIndex) const {
104 switch (MI->getOpcode()) {
106 case Hexagon::S2_storeri_io:
107 case Hexagon::S2_storerd_io:
108 case Hexagon::S2_storerh_io:
109 case Hexagon::S2_storerb_io:
110 if (MI->getOperand(2).isFI() &&
111 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
112 FrameIndex = MI->getOperand(0).getIndex();
113 return MI->getOperand(2).getReg();
122 HexagonInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
123 MachineBasicBlock *FBB,
124 const SmallVectorImpl<MachineOperand> &Cond,
127 int BOpc = Hexagon::J2_jump;
128 int BccOpc = Hexagon::J2_jumpt;
130 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
133 // Check if ReverseBranchCondition has asked to reverse this branch
134 // If we want to reverse the branch an odd number of times, we want
136 if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) {
137 BccOpc = Hexagon::J2_jumpf;
143 // Due to a bug in TailMerging/CFG Optimization, we need to add a
144 // special case handling of a predicated jump followed by an
145 // unconditional jump. If not, Tail Merging and CFG Optimization go
146 // into an infinite loop.
147 MachineBasicBlock *NewTBB, *NewFBB;
148 SmallVector<MachineOperand, 4> Cond;
149 MachineInstr *Term = MBB.getFirstTerminator();
150 if (isPredicated(Term) && !AnalyzeBranch(MBB, NewTBB, NewFBB, Cond,
152 MachineBasicBlock *NextBB =
153 std::next(MachineFunction::iterator(&MBB));
154 if (NewTBB == NextBB) {
155 ReverseBranchCondition(Cond);
157 return InsertBranch(MBB, TBB, nullptr, Cond, DL);
160 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
163 get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
168 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
169 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
175 bool HexagonInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
176 MachineBasicBlock *&TBB,
177 MachineBasicBlock *&FBB,
178 SmallVectorImpl<MachineOperand> &Cond,
179 bool AllowModify) const {
183 // If the block has no terminators, it just falls into the block after it.
184 MachineBasicBlock::instr_iterator I = MBB.instr_end();
185 if (I == MBB.instr_begin())
188 // A basic block may looks like this:
198 // It has two succs but does not have a terminator
199 // Don't know how to handle it.
204 } while (I != MBB.instr_begin());
209 while (I->isDebugValue()) {
210 if (I == MBB.instr_begin())
215 // Delete the JMP if it's equivalent to a fall-through.
216 if (AllowModify && I->getOpcode() == Hexagon::J2_jump &&
217 MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
218 DEBUG(dbgs()<< "\nErasing the jump to successor block\n";);
219 I->eraseFromParent();
221 if (I == MBB.instr_begin())
225 if (!isUnpredicatedTerminator(I))
228 // Get the last instruction in the block.
229 MachineInstr *LastInst = I;
230 MachineInstr *SecondLastInst = nullptr;
231 // Find one more terminator if present.
233 if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(I)) {
237 // This is a third branch.
240 if (I == MBB.instr_begin())
245 int LastOpcode = LastInst->getOpcode();
247 bool LastOpcodeHasJMP_c = PredOpcodeHasJMP_c(LastOpcode);
248 bool LastOpcodeHasNot = PredOpcodeHasNot(LastOpcode);
250 // If there is only one terminator instruction, process it.
251 if (LastInst && !SecondLastInst) {
252 if (LastOpcode == Hexagon::J2_jump) {
253 TBB = LastInst->getOperand(0).getMBB();
256 if (LastOpcode == Hexagon::ENDLOOP0) {
257 TBB = LastInst->getOperand(0).getMBB();
258 Cond.push_back(LastInst->getOperand(0));
261 if (LastOpcodeHasJMP_c) {
262 TBB = LastInst->getOperand(1).getMBB();
263 if (LastOpcodeHasNot) {
264 Cond.push_back(MachineOperand::CreateImm(0));
266 Cond.push_back(LastInst->getOperand(0));
269 // Otherwise, don't know what this is.
273 int SecLastOpcode = SecondLastInst->getOpcode();
275 bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c(SecLastOpcode);
276 bool SecLastOpcodeHasNot = PredOpcodeHasNot(SecLastOpcode);
277 if (SecLastOpcodeHasJMP_c && (LastOpcode == Hexagon::J2_jump)) {
278 TBB = SecondLastInst->getOperand(1).getMBB();
279 if (SecLastOpcodeHasNot)
280 Cond.push_back(MachineOperand::CreateImm(0));
281 Cond.push_back(SecondLastInst->getOperand(0));
282 FBB = LastInst->getOperand(0).getMBB();
286 // If the block ends with two Hexagon:JMPs, handle it. The second one is not
287 // executed, so remove it.
288 if (SecLastOpcode == Hexagon::J2_jump && LastOpcode == Hexagon::J2_jump) {
289 TBB = SecondLastInst->getOperand(0).getMBB();
292 I->eraseFromParent();
296 // If the block ends with an ENDLOOP, and JMP, handle it.
297 if (SecLastOpcode == Hexagon::ENDLOOP0 &&
298 LastOpcode == Hexagon::J2_jump) {
299 TBB = SecondLastInst->getOperand(0).getMBB();
300 Cond.push_back(SecondLastInst->getOperand(0));
301 FBB = LastInst->getOperand(0).getMBB();
305 // Otherwise, can't handle this.
310 unsigned HexagonInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
311 int BOpc = Hexagon::J2_jump;
312 int BccOpc = Hexagon::J2_jumpt;
313 int BccOpcNot = Hexagon::J2_jumpf;
315 MachineBasicBlock::iterator I = MBB.end();
316 if (I == MBB.begin()) return 0;
318 if (I->getOpcode() != BOpc && I->getOpcode() != BccOpc &&
319 I->getOpcode() != BccOpcNot)
322 // Remove the branch.
323 I->eraseFromParent();
327 if (I == MBB.begin()) return 1;
329 if (I->getOpcode() != BccOpc && I->getOpcode() != BccOpcNot)
332 // Remove the branch.
333 I->eraseFromParent();
338 /// \brief For a comparison instruction, return the source registers in
339 /// \p SrcReg and \p SrcReg2 if having two register operands, and the value it
340 /// compares against in CmpValue. Return true if the comparison instruction
342 bool HexagonInstrInfo::analyzeCompare(const MachineInstr *MI,
343 unsigned &SrcReg, unsigned &SrcReg2,
344 int &Mask, int &Value) const {
345 unsigned Opc = MI->getOpcode();
347 // Set mask and the first source register.
349 case Hexagon::C2_cmpeqp:
350 case Hexagon::C2_cmpeqi:
351 case Hexagon::C2_cmpeq:
352 case Hexagon::C2_cmpgtp:
353 case Hexagon::C2_cmpgtup:
354 case Hexagon::C2_cmpgtui:
355 case Hexagon::C2_cmpgtu:
356 case Hexagon::C2_cmpgti:
357 case Hexagon::C2_cmpgt:
358 SrcReg = MI->getOperand(1).getReg();
361 case Hexagon::A4_cmpbeqi:
362 case Hexagon::A4_cmpbeq:
363 case Hexagon::A4_cmpbgtui:
364 case Hexagon::A4_cmpbgtu:
365 case Hexagon::A4_cmpbgt:
366 SrcReg = MI->getOperand(1).getReg();
369 case Hexagon::A4_cmpheqi:
370 case Hexagon::A4_cmpheq:
371 case Hexagon::A4_cmphgtui:
372 case Hexagon::A4_cmphgtu:
373 case Hexagon::A4_cmphgt:
374 SrcReg = MI->getOperand(1).getReg();
379 // Set the value/second source register.
381 case Hexagon::C2_cmpeqp:
382 case Hexagon::C2_cmpeq:
383 case Hexagon::C2_cmpgtp:
384 case Hexagon::C2_cmpgtup:
385 case Hexagon::C2_cmpgtu:
386 case Hexagon::C2_cmpgt:
387 case Hexagon::A4_cmpbeq:
388 case Hexagon::A4_cmpbgtu:
389 case Hexagon::A4_cmpbgt:
390 case Hexagon::A4_cmpheq:
391 case Hexagon::A4_cmphgtu:
392 case Hexagon::A4_cmphgt:
393 SrcReg2 = MI->getOperand(2).getReg();
396 case Hexagon::C2_cmpeqi:
397 case Hexagon::C2_cmpgtui:
398 case Hexagon::C2_cmpgti:
399 case Hexagon::A4_cmpbeqi:
400 case Hexagon::A4_cmpbgtui:
401 case Hexagon::A4_cmpheqi:
402 case Hexagon::A4_cmphgtui:
404 Value = MI->getOperand(2).getImm();
412 void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
413 MachineBasicBlock::iterator I, DebugLoc DL,
414 unsigned DestReg, unsigned SrcReg,
415 bool KillSrc) const {
416 if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
417 BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), DestReg).addReg(SrcReg);
420 if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
421 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrp), DestReg).addReg(SrcReg);
424 if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
425 // Map Pd = Ps to Pd = or(Ps, Ps).
426 BuildMI(MBB, I, DL, get(Hexagon::C2_or),
427 DestReg).addReg(SrcReg).addReg(SrcReg);
430 if (Hexagon::DoubleRegsRegClass.contains(DestReg) &&
431 Hexagon::IntRegsRegClass.contains(SrcReg)) {
432 // We can have an overlap between single and double reg: r1:0 = r0.
433 if(SrcReg == RI.getSubReg(DestReg, Hexagon::subreg_loreg)) {
435 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrsi), (RI.getSubReg(DestReg,
436 Hexagon::subreg_hireg))).addImm(0);
438 // r1:0 = r1 or no overlap.
439 BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), (RI.getSubReg(DestReg,
440 Hexagon::subreg_loreg))).addReg(SrcReg);
441 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrsi), (RI.getSubReg(DestReg,
442 Hexagon::subreg_hireg))).addImm(0);
446 if (Hexagon::CtrRegsRegClass.contains(DestReg) &&
447 Hexagon::IntRegsRegClass.contains(SrcReg)) {
448 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg).addReg(SrcReg);
451 if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
452 Hexagon::IntRegsRegClass.contains(DestReg)) {
453 BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg).
454 addReg(SrcReg, getKillRegState(KillSrc));
457 if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
458 Hexagon::PredRegsRegClass.contains(DestReg)) {
459 BuildMI(MBB, I, DL, get(Hexagon::C2_tfrrp), DestReg).
460 addReg(SrcReg, getKillRegState(KillSrc));
464 llvm_unreachable("Unimplemented");
468 void HexagonInstrInfo::
469 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
470 unsigned SrcReg, bool isKill, int FI,
471 const TargetRegisterClass *RC,
472 const TargetRegisterInfo *TRI) const {
474 DebugLoc DL = MBB.findDebugLoc(I);
475 MachineFunction &MF = *MBB.getParent();
476 MachineFrameInfo &MFI = *MF.getFrameInfo();
477 unsigned Align = MFI.getObjectAlignment(FI);
479 MachineMemOperand *MMO =
480 MF.getMachineMemOperand(
481 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
482 MachineMemOperand::MOStore,
483 MFI.getObjectSize(FI),
486 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
487 BuildMI(MBB, I, DL, get(Hexagon::S2_storeri_io))
488 .addFrameIndex(FI).addImm(0)
489 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
490 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
491 BuildMI(MBB, I, DL, get(Hexagon::S2_storerd_io))
492 .addFrameIndex(FI).addImm(0)
493 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
494 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
495 BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
496 .addFrameIndex(FI).addImm(0)
497 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
499 llvm_unreachable("Unimplemented");
504 void HexagonInstrInfo::storeRegToAddr(
505 MachineFunction &MF, unsigned SrcReg,
507 SmallVectorImpl<MachineOperand> &Addr,
508 const TargetRegisterClass *RC,
509 SmallVectorImpl<MachineInstr*> &NewMIs) const
511 llvm_unreachable("Unimplemented");
515 void HexagonInstrInfo::
516 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
517 unsigned DestReg, int FI,
518 const TargetRegisterClass *RC,
519 const TargetRegisterInfo *TRI) const {
520 DebugLoc DL = MBB.findDebugLoc(I);
521 MachineFunction &MF = *MBB.getParent();
522 MachineFrameInfo &MFI = *MF.getFrameInfo();
523 unsigned Align = MFI.getObjectAlignment(FI);
525 MachineMemOperand *MMO =
526 MF.getMachineMemOperand(
527 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
528 MachineMemOperand::MOLoad,
529 MFI.getObjectSize(FI),
531 if (RC == &Hexagon::IntRegsRegClass) {
532 BuildMI(MBB, I, DL, get(Hexagon::L2_loadri_io), DestReg)
533 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
534 } else if (RC == &Hexagon::DoubleRegsRegClass) {
535 BuildMI(MBB, I, DL, get(Hexagon::L2_loadrd_io), DestReg)
536 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
537 } else if (RC == &Hexagon::PredRegsRegClass) {
538 BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
539 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
541 llvm_unreachable("Can't store this register to stack slot");
546 void HexagonInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
547 SmallVectorImpl<MachineOperand> &Addr,
548 const TargetRegisterClass *RC,
549 SmallVectorImpl<MachineInstr*> &NewMIs) const {
550 llvm_unreachable("Unimplemented");
554 MachineInstr *HexagonInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
556 const SmallVectorImpl<unsigned> &Ops,
558 // Hexagon_TODO: Implement.
562 unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const {
564 MachineRegisterInfo &RegInfo = MF->getRegInfo();
565 const TargetRegisterClass *TRC;
567 TRC = &Hexagon::PredRegsRegClass;
568 } else if (VT == MVT::i32 || VT == MVT::f32) {
569 TRC = &Hexagon::IntRegsRegClass;
570 } else if (VT == MVT::i64 || VT == MVT::f64) {
571 TRC = &Hexagon::DoubleRegsRegClass;
573 llvm_unreachable("Cannot handle this register class");
576 unsigned NewReg = RegInfo.createVirtualRegister(TRC);
580 bool HexagonInstrInfo::isExtendable(const MachineInstr *MI) const {
581 const MCInstrDesc &MID = MI->getDesc();
582 const uint64_t F = MID.TSFlags;
583 if ((F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask)
586 // TODO: This is largely obsolete now. Will need to be removed
587 // in consecutive patches.
588 switch(MI->getOpcode()) {
589 // TFR_FI Remains a special case.
590 case Hexagon::TFR_FI:
598 // This returns true in two cases:
599 // - The OP code itself indicates that this is an extended instruction.
600 // - One of MOs has been marked with HMOTF_ConstExtended flag.
601 bool HexagonInstrInfo::isExtended(const MachineInstr *MI) const {
602 // First check if this is permanently extended op code.
603 const uint64_t F = MI->getDesc().TSFlags;
604 if ((F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask)
606 // Use MO operand flags to determine if one of MI's operands
607 // has HMOTF_ConstExtended flag set.
608 for (MachineInstr::const_mop_iterator I = MI->operands_begin(),
609 E = MI->operands_end(); I != E; ++I) {
610 if (I->getTargetFlags() && HexagonII::HMOTF_ConstExtended)
616 bool HexagonInstrInfo::isBranch (const MachineInstr *MI) const {
617 return MI->getDesc().isBranch();
620 bool HexagonInstrInfo::isNewValueInst(const MachineInstr *MI) const {
621 if (isNewValueJump(MI))
624 if (isNewValueStore(MI))
630 bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr *MI) const {
631 return MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4;
634 bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
635 bool isPred = MI->getDesc().isPredicable();
640 const int Opc = MI->getOpcode();
643 case Hexagon::A2_tfrsi:
644 return isInt<12>(MI->getOperand(1).getImm());
646 case Hexagon::S2_storerd_io:
647 return isShiftedUInt<6,3>(MI->getOperand(1).getImm());
649 case Hexagon::S2_storeri_io:
650 case Hexagon::S2_storerinew_io:
651 return isShiftedUInt<6,2>(MI->getOperand(1).getImm());
653 case Hexagon::S2_storerh_io:
654 case Hexagon::S2_storerhnew_io:
655 return isShiftedUInt<6,1>(MI->getOperand(1).getImm());
657 case Hexagon::S2_storerb_io:
658 case Hexagon::S2_storerbnew_io:
659 return isUInt<6>(MI->getOperand(1).getImm());
661 case Hexagon::L2_loadrd_io:
662 return isShiftedUInt<6,3>(MI->getOperand(2).getImm());
664 case Hexagon::L2_loadri_io:
665 return isShiftedUInt<6,2>(MI->getOperand(2).getImm());
667 case Hexagon::L2_loadrh_io:
668 case Hexagon::L2_loadruh_io:
669 return isShiftedUInt<6,1>(MI->getOperand(2).getImm());
671 case Hexagon::L2_loadrb_io:
672 case Hexagon::L2_loadrub_io:
673 return isUInt<6>(MI->getOperand(2).getImm());
675 case Hexagon::L2_loadrd_pi:
676 return isShiftedInt<4,3>(MI->getOperand(3).getImm());
678 case Hexagon::L2_loadri_pi:
679 return isShiftedInt<4,2>(MI->getOperand(3).getImm());
681 case Hexagon::L2_loadrh_pi:
682 case Hexagon::L2_loadruh_pi:
683 return isShiftedInt<4,1>(MI->getOperand(3).getImm());
685 case Hexagon::L2_loadrb_pi:
686 case Hexagon::L2_loadrub_pi:
687 return isInt<4>(MI->getOperand(3).getImm());
689 case Hexagon::S4_storeirb_io:
690 case Hexagon::S4_storeirh_io:
691 case Hexagon::S4_storeiri_io:
692 return (isUInt<6>(MI->getOperand(1).getImm()) &&
693 isInt<6>(MI->getOperand(2).getImm()));
695 case Hexagon::A2_addi:
696 return isInt<8>(MI->getOperand(2).getImm());
698 case Hexagon::A2_aslh:
699 case Hexagon::A2_asrh:
700 case Hexagon::A2_sxtb:
701 case Hexagon::A2_sxth:
702 case Hexagon::A2_zxtb:
703 case Hexagon::A2_zxth:
710 // This function performs the following inversiones:
715 unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
717 InvPredOpcode = isPredicatedTrue(Opc) ? Hexagon::getFalsePredOpcode(Opc)
718 : Hexagon::getTruePredOpcode(Opc);
719 if (InvPredOpcode >= 0) // Valid instruction with the inverted predicate.
720 return InvPredOpcode;
723 default: llvm_unreachable("Unexpected predicated instruction");
724 case Hexagon::C2_ccombinewt:
725 return Hexagon::C2_ccombinewf;
726 case Hexagon::C2_ccombinewf:
727 return Hexagon::C2_ccombinewt;
730 case Hexagon::L4_return_t:
731 return Hexagon::L4_return_f;
732 case Hexagon::L4_return_f:
733 return Hexagon::L4_return_t;
737 // New Value Store instructions.
738 bool HexagonInstrInfo::isNewValueStore(const MachineInstr *MI) const {
739 const uint64_t F = MI->getDesc().TSFlags;
741 return ((F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask);
744 bool HexagonInstrInfo::isNewValueStore(unsigned Opcode) const {
745 const uint64_t F = get(Opcode).TSFlags;
747 return ((F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask);
750 int HexagonInstrInfo::
751 getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const {
752 enum Hexagon::PredSense inPredSense;
753 inPredSense = invertPredicate ? Hexagon::PredSense_false :
754 Hexagon::PredSense_true;
755 int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense);
756 if (CondOpcode >= 0) // Valid Conditional opcode/instruction
759 // This switch case will be removed once all the instructions have been
760 // modified to use relation maps.
762 case Hexagon::TFRI_f:
763 return !invertPredicate ? Hexagon::TFRI_cPt_f :
764 Hexagon::TFRI_cNotPt_f;
765 case Hexagon::A2_combinew:
766 return !invertPredicate ? Hexagon::C2_ccombinewt :
767 Hexagon::C2_ccombinewf;
770 case Hexagon::L4_return:
771 return !invertPredicate ? Hexagon::L4_return_t:
772 Hexagon::L4_return_f;
774 llvm_unreachable("Unexpected predicable instruction");
778 bool HexagonInstrInfo::
779 PredicateInstruction(MachineInstr *MI,
780 const SmallVectorImpl<MachineOperand> &Cond) const {
781 int Opc = MI->getOpcode();
782 assert (isPredicable(MI) && "Expected predicable instruction");
783 bool invertJump = (!Cond.empty() && Cond[0].isImm() &&
784 (Cond[0].getImm() == 0));
786 // This will change MI's opcode to its predicate version.
787 // However, its operand list is still the old one, i.e. the
788 // non-predicate one.
789 MI->setDesc(get(getMatchingCondBranchOpcode(Opc, invertJump)));
792 unsigned int GAIdx = 0;
794 // Indicates whether the current MI has a GlobalAddress operand
795 bool hasGAOpnd = false;
796 std::vector<MachineOperand> tmpOpnds;
798 // Indicates whether we need to shift operands to right.
799 bool needShift = true;
801 // The predicate is ALWAYS the FIRST input operand !!!
802 if (MI->getNumOperands() == 0) {
803 // The non-predicate version of MI does not take any operands,
804 // i.e. no outs and no ins. In this condition, the predicate
805 // operand will be directly placed at Operands[0]. No operand
811 else if ( MI->getOperand(MI->getNumOperands()-1).isReg()
812 && MI->getOperand(MI->getNumOperands()-1).isDef()
813 && !MI->getOperand(MI->getNumOperands()-1).isImplicit()) {
814 // The non-predicate version of MI does not have any input operands.
815 // In this condition, we extend the length of Operands[] by one and
816 // copy the original last operand to the newly allocated slot.
817 // At this moment, it is just a place holder. Later, we will put
818 // predicate operand directly into it. No operand shift is needed.
819 // Example: r0=BARRIER (this is a faked insn used here for illustration)
820 MI->addOperand(MI->getOperand(MI->getNumOperands()-1));
822 oper = MI->getNumOperands() - 2;
825 // We need to right shift all input operands by one. Duplicate the
826 // last operand into the newly allocated slot.
827 MI->addOperand(MI->getOperand(MI->getNumOperands()-1));
832 // Operands[ MI->getNumOperands() - 2 ] has been copied into
833 // Operands[ MI->getNumOperands() - 1 ], so we start from
834 // Operands[ MI->getNumOperands() - 3 ].
835 // oper is a signed int.
836 // It is ok if "MI->getNumOperands()-3" is -3, -2, or -1.
837 for (oper = MI->getNumOperands() - 3; oper >= 0; --oper)
839 MachineOperand &MO = MI->getOperand(oper);
841 // Opnd[0] Opnd[1] Opnd[2] Opnd[3] Opnd[4] Opnd[5] Opnd[6] Opnd[7]
842 // <Def0> <Def1> <Use0> <Use1> <ImpDef0> <ImpDef1> <ImpUse0> <ImpUse1>
846 // Predicate Operand here
847 if (MO.isReg() && !MO.isUse() && !MO.isImplicit()) {
851 MI->getOperand(oper+1).ChangeToRegister(MO.getReg(), MO.isDef(),
852 MO.isImplicit(), MO.isKill(),
853 MO.isDead(), MO.isUndef(),
856 else if (MO.isImm()) {
857 MI->getOperand(oper+1).ChangeToImmediate(MO.getImm());
859 else if (MO.isGlobal()) {
860 // MI can not have more than one GlobalAddress operand.
861 assert(hasGAOpnd == false && "MI can only have one GlobalAddress opnd");
863 // There is no member function called "ChangeToGlobalAddress" in the
864 // MachineOperand class (not like "ChangeToRegister" and
865 // "ChangeToImmediate"). So we have to remove them from Operands[] list
866 // first, and then add them back after we have inserted the predicate
867 // operand. tmpOpnds[] is to remember these operands before we remove
869 tmpOpnds.push_back(MO);
871 // Operands[oper] is a GlobalAddress operand;
872 // Operands[oper+1] has been copied into Operands[oper+2];
878 llvm_unreachable("Unexpected operand type");
883 int regPos = invertJump ? 1 : 0;
884 MachineOperand PredMO = Cond[regPos];
886 // [oper] now points to the last explicit Def. Predicate operand must be
887 // located at [oper+1]. See diagram above.
888 // This assumes that the predicate is always the first operand,
889 // i.e. Operands[0+numResults], in the set of inputs
890 // It is better to have an assert here to check this. But I don't know how
891 // to write this assert because findFirstPredOperandIdx() would return -1
892 if (oper < -1) oper = -1;
894 MI->getOperand(oper+1).ChangeToRegister(PredMO.getReg(), PredMO.isDef(),
895 PredMO.isImplicit(), false,
896 PredMO.isDead(), PredMO.isUndef(),
899 MachineRegisterInfo &RegInfo = MI->getParent()->getParent()->getRegInfo();
900 RegInfo.clearKillFlags(PredMO.getReg());
906 // Operands[GAIdx] is the original GlobalAddress operand, which is
907 // already copied into tmpOpnds[0].
908 // Operands[GAIdx] now stores a copy of Operands[GAIdx-1]
909 // Operands[GAIdx+1] has already been copied into Operands[GAIdx+2],
910 // so we start from [GAIdx+2]
911 for (i = GAIdx + 2; i < MI->getNumOperands(); ++i)
912 tmpOpnds.push_back(MI->getOperand(i));
914 // Remove all operands in range [ (GAIdx+1) ... (MI->getNumOperands()-1) ]
915 // It is very important that we always remove from the end of Operands[]
916 // MI->getNumOperands() is at least 2 if program goes to here.
917 for (i = MI->getNumOperands() - 1; i > GAIdx; --i)
918 MI->RemoveOperand(i);
920 for (i = 0; i < tmpOpnds.size(); ++i)
921 MI->addOperand(tmpOpnds[i]);
930 isProfitableToIfCvt(MachineBasicBlock &MBB,
932 unsigned ExtraPredCycles,
933 const BranchProbability &Probability) const {
940 isProfitableToIfCvt(MachineBasicBlock &TMBB,
942 unsigned ExtraTCycles,
943 MachineBasicBlock &FMBB,
945 unsigned ExtraFCycles,
946 const BranchProbability &Probability) const {
950 // Returns true if an instruction is predicated irrespective of the predicate
951 // sense. For example, all of the following will return true.
952 // if (p0) R1 = add(R2, R3)
953 // if (!p0) R1 = add(R2, R3)
954 // if (p0.new) R1 = add(R2, R3)
955 // if (!p0.new) R1 = add(R2, R3)
956 bool HexagonInstrInfo::isPredicated(const MachineInstr *MI) const {
957 const uint64_t F = MI->getDesc().TSFlags;
959 return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
962 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const {
963 const uint64_t F = get(Opcode).TSFlags;
965 return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
968 bool HexagonInstrInfo::isPredicatedTrue(const MachineInstr *MI) const {
969 const uint64_t F = MI->getDesc().TSFlags;
971 assert(isPredicated(MI));
972 return (!((F >> HexagonII::PredicatedFalsePos) &
973 HexagonII::PredicatedFalseMask));
976 bool HexagonInstrInfo::isPredicatedTrue(unsigned Opcode) const {
977 const uint64_t F = get(Opcode).TSFlags;
979 // Make sure that the instruction is predicated.
980 assert((F>> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
981 return (!((F >> HexagonII::PredicatedFalsePos) &
982 HexagonII::PredicatedFalseMask));
985 bool HexagonInstrInfo::isPredicatedNew(const MachineInstr *MI) const {
986 const uint64_t F = MI->getDesc().TSFlags;
988 assert(isPredicated(MI));
989 return ((F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask);
992 bool HexagonInstrInfo::isPredicatedNew(unsigned Opcode) const {
993 const uint64_t F = get(Opcode).TSFlags;
995 assert(isPredicated(Opcode));
996 return ((F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask);
999 // Returns true, if a ST insn can be promoted to a new-value store.
1000 bool HexagonInstrInfo::mayBeNewStore(const MachineInstr *MI) const {
1001 const HexagonRegisterInfo& QRI = getRegisterInfo();
1002 const uint64_t F = MI->getDesc().TSFlags;
1004 return ((F >> HexagonII::mayNVStorePos) &
1005 HexagonII::mayNVStoreMask);
1009 HexagonInstrInfo::DefinesPredicate(MachineInstr *MI,
1010 std::vector<MachineOperand> &Pred) const {
1011 for (unsigned oper = 0; oper < MI->getNumOperands(); ++oper) {
1012 MachineOperand MO = MI->getOperand(oper);
1013 if (MO.isReg() && MO.isDef()) {
1014 const TargetRegisterClass* RC = RI.getMinimalPhysRegClass(MO.getReg());
1015 if (RC == &Hexagon::PredRegsRegClass) {
1027 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
1028 const SmallVectorImpl<MachineOperand> &Pred2) const {
1035 // We indicate that we want to reverse the branch by
1036 // inserting a 0 at the beginning of the Cond vector.
1038 bool HexagonInstrInfo::
1039 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
1040 if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) {
1041 Cond.erase(Cond.begin());
1043 Cond.insert(Cond.begin(), MachineOperand::CreateImm(0));
1049 bool HexagonInstrInfo::
1050 isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumInstrs,
1051 const BranchProbability &Probability) const {
1052 return (NumInstrs <= 4);
1055 bool HexagonInstrInfo::isDeallocRet(const MachineInstr *MI) const {
1056 switch (MI->getOpcode()) {
1057 default: return false;
1058 case Hexagon::L4_return:
1059 case Hexagon::L4_return_t:
1060 case Hexagon::L4_return_f:
1061 case Hexagon::L4_return_tnew_pnt:
1062 case Hexagon::L4_return_fnew_pnt:
1063 case Hexagon::L4_return_tnew_pt:
1064 case Hexagon::L4_return_fnew_pt:
1070 bool HexagonInstrInfo::
1071 isValidOffset(const int Opcode, const int Offset) const {
1072 // This function is to check whether the "Offset" is in the correct range of
1073 // the given "Opcode". If "Offset" is not in the correct range, "ADD_ri" is
1074 // inserted to calculate the final address. Due to this reason, the function
1075 // assumes that the "Offset" has correct alignment.
1076 // We used to assert if the offset was not properly aligned, however,
1077 // there are cases where a misaligned pointer recast can cause this
1078 // problem, and we need to allow for it. The front end warns of such
1079 // misaligns with respect to load size.
1083 case Hexagon::L2_loadri_io:
1084 case Hexagon::S2_storeri_io:
1085 return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
1086 (Offset <= Hexagon_MEMW_OFFSET_MAX);
1088 case Hexagon::L2_loadrd_io:
1089 case Hexagon::S2_storerd_io:
1090 return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
1091 (Offset <= Hexagon_MEMD_OFFSET_MAX);
1093 case Hexagon::L2_loadrh_io:
1094 case Hexagon::L2_loadruh_io:
1095 case Hexagon::S2_storerh_io:
1096 return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
1097 (Offset <= Hexagon_MEMH_OFFSET_MAX);
1099 case Hexagon::L2_loadrb_io:
1100 case Hexagon::S2_storerb_io:
1101 case Hexagon::L2_loadrub_io:
1102 return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
1103 (Offset <= Hexagon_MEMB_OFFSET_MAX);
1105 case Hexagon::A2_addi:
1106 case Hexagon::TFR_FI:
1107 return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
1108 (Offset <= Hexagon_ADDI_OFFSET_MAX);
1110 case Hexagon::L4_iadd_memopw_io:
1111 case Hexagon::L4_isub_memopw_io:
1112 case Hexagon::L4_add_memopw_io:
1113 case Hexagon::L4_sub_memopw_io:
1114 case Hexagon::L4_and_memopw_io:
1115 case Hexagon::L4_or_memopw_io:
1116 return (0 <= Offset && Offset <= 255);
1118 case Hexagon::L4_iadd_memoph_io:
1119 case Hexagon::L4_isub_memoph_io:
1120 case Hexagon::L4_add_memoph_io:
1121 case Hexagon::L4_sub_memoph_io:
1122 case Hexagon::L4_and_memoph_io:
1123 case Hexagon::L4_or_memoph_io:
1124 return (0 <= Offset && Offset <= 127);
1126 case Hexagon::L4_iadd_memopb_io:
1127 case Hexagon::L4_isub_memopb_io:
1128 case Hexagon::L4_add_memopb_io:
1129 case Hexagon::L4_sub_memopb_io:
1130 case Hexagon::L4_and_memopb_io:
1131 case Hexagon::L4_or_memopb_io:
1132 return (0 <= Offset && Offset <= 63);
1134 // LDri_pred and STriw_pred are pseudo operations, so it has to take offset of
1135 // any size. Later pass knows how to handle it.
1136 case Hexagon::STriw_pred:
1137 case Hexagon::LDriw_pred:
1140 case Hexagon::J2_loop0i:
1141 return isUInt<10>(Offset);
1143 // INLINEASM is very special.
1144 case Hexagon::INLINEASM:
1148 llvm_unreachable("No offset range is defined for this opcode. "
1149 "Please define it in the above switch statement!");
1154 // Check if the Offset is a valid auto-inc imm by Load/Store Type.
1156 bool HexagonInstrInfo::
1157 isValidAutoIncImm(const EVT VT, const int Offset) const {
1159 if (VT == MVT::i64) {
1160 return (Offset >= Hexagon_MEMD_AUTOINC_MIN &&
1161 Offset <= Hexagon_MEMD_AUTOINC_MAX &&
1162 (Offset & 0x7) == 0);
1164 if (VT == MVT::i32) {
1165 return (Offset >= Hexagon_MEMW_AUTOINC_MIN &&
1166 Offset <= Hexagon_MEMW_AUTOINC_MAX &&
1167 (Offset & 0x3) == 0);
1169 if (VT == MVT::i16) {
1170 return (Offset >= Hexagon_MEMH_AUTOINC_MIN &&
1171 Offset <= Hexagon_MEMH_AUTOINC_MAX &&
1172 (Offset & 0x1) == 0);
1174 if (VT == MVT::i8) {
1175 return (Offset >= Hexagon_MEMB_AUTOINC_MIN &&
1176 Offset <= Hexagon_MEMB_AUTOINC_MAX);
1178 llvm_unreachable("Not an auto-inc opc!");
1182 bool HexagonInstrInfo::
1183 isMemOp(const MachineInstr *MI) const {
1184 // return MI->getDesc().mayLoad() && MI->getDesc().mayStore();
1186 switch (MI->getOpcode())
1188 default: return false;
1189 case Hexagon::L4_iadd_memopw_io:
1190 case Hexagon::L4_isub_memopw_io:
1191 case Hexagon::L4_add_memopw_io:
1192 case Hexagon::L4_sub_memopw_io:
1193 case Hexagon::L4_and_memopw_io:
1194 case Hexagon::L4_or_memopw_io:
1195 case Hexagon::L4_iadd_memoph_io:
1196 case Hexagon::L4_isub_memoph_io:
1197 case Hexagon::L4_add_memoph_io:
1198 case Hexagon::L4_sub_memoph_io:
1199 case Hexagon::L4_and_memoph_io:
1200 case Hexagon::L4_or_memoph_io:
1201 case Hexagon::L4_iadd_memopb_io:
1202 case Hexagon::L4_isub_memopb_io:
1203 case Hexagon::L4_add_memopb_io:
1204 case Hexagon::L4_sub_memopb_io:
1205 case Hexagon::L4_and_memopb_io:
1206 case Hexagon::L4_or_memopb_io:
1207 case Hexagon::L4_ior_memopb_io:
1208 case Hexagon::L4_ior_memoph_io:
1209 case Hexagon::L4_ior_memopw_io:
1210 case Hexagon::L4_iand_memopb_io:
1211 case Hexagon::L4_iand_memoph_io:
1212 case Hexagon::L4_iand_memopw_io:
1219 bool HexagonInstrInfo::
1220 isSpillPredRegOp(const MachineInstr *MI) const {
1221 switch (MI->getOpcode()) {
1222 default: return false;
1223 case Hexagon::STriw_pred :
1224 case Hexagon::LDriw_pred :
1229 bool HexagonInstrInfo::isNewValueJumpCandidate(const MachineInstr *MI) const {
1230 switch (MI->getOpcode()) {
1231 default: return false;
1232 case Hexagon::C2_cmpeq:
1233 case Hexagon::C2_cmpeqi:
1234 case Hexagon::C2_cmpgt:
1235 case Hexagon::C2_cmpgti:
1236 case Hexagon::C2_cmpgtu:
1237 case Hexagon::C2_cmpgtui:
1242 bool HexagonInstrInfo::
1243 isConditionalTransfer (const MachineInstr *MI) const {
1244 switch (MI->getOpcode()) {
1245 default: return false;
1246 case Hexagon::A2_tfrt:
1247 case Hexagon::A2_tfrf:
1248 case Hexagon::C2_cmoveit:
1249 case Hexagon::C2_cmoveif:
1250 case Hexagon::A2_tfrtnew:
1251 case Hexagon::A2_tfrfnew:
1252 case Hexagon::C2_cmovenewit:
1253 case Hexagon::C2_cmovenewif:
1258 bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const {
1259 switch (MI->getOpcode())
1261 default: return false;
1262 case Hexagon::A2_paddf:
1263 case Hexagon::A2_paddfnew:
1264 case Hexagon::A2_paddt:
1265 case Hexagon::A2_paddtnew:
1266 case Hexagon::A2_pandf:
1267 case Hexagon::A2_pandfnew:
1268 case Hexagon::A2_pandt:
1269 case Hexagon::A2_pandtnew:
1270 case Hexagon::A4_paslhf:
1271 case Hexagon::A4_paslhfnew:
1272 case Hexagon::A4_paslht:
1273 case Hexagon::A4_paslhtnew:
1274 case Hexagon::A4_pasrhf:
1275 case Hexagon::A4_pasrhfnew:
1276 case Hexagon::A4_pasrht:
1277 case Hexagon::A4_pasrhtnew:
1278 case Hexagon::A2_porf:
1279 case Hexagon::A2_porfnew:
1280 case Hexagon::A2_port:
1281 case Hexagon::A2_portnew:
1282 case Hexagon::A2_psubf:
1283 case Hexagon::A2_psubfnew:
1284 case Hexagon::A2_psubt:
1285 case Hexagon::A2_psubtnew:
1286 case Hexagon::A2_pxorf:
1287 case Hexagon::A2_pxorfnew:
1288 case Hexagon::A2_pxort:
1289 case Hexagon::A2_pxortnew:
1290 case Hexagon::A4_psxthf:
1291 case Hexagon::A4_psxthfnew:
1292 case Hexagon::A4_psxtht:
1293 case Hexagon::A4_psxthtnew:
1294 case Hexagon::A4_psxtbf:
1295 case Hexagon::A4_psxtbfnew:
1296 case Hexagon::A4_psxtbt:
1297 case Hexagon::A4_psxtbtnew:
1298 case Hexagon::A4_pzxtbf:
1299 case Hexagon::A4_pzxtbfnew:
1300 case Hexagon::A4_pzxtbt:
1301 case Hexagon::A4_pzxtbtnew:
1302 case Hexagon::A4_pzxthf:
1303 case Hexagon::A4_pzxthfnew:
1304 case Hexagon::A4_pzxtht:
1305 case Hexagon::A4_pzxthtnew:
1306 case Hexagon::A2_paddit:
1307 case Hexagon::A2_paddif:
1308 case Hexagon::C2_ccombinewt:
1309 case Hexagon::C2_ccombinewf:
1314 bool HexagonInstrInfo::
1315 isConditionalLoad (const MachineInstr* MI) const {
1316 const HexagonRegisterInfo& QRI = getRegisterInfo();
1317 switch (MI->getOpcode())
1319 default: return false;
1320 case Hexagon::L2_ploadrdt_io :
1321 case Hexagon::L2_ploadrdf_io:
1322 case Hexagon::L2_ploadrit_io:
1323 case Hexagon::L2_ploadrif_io:
1324 case Hexagon::L2_ploadrht_io:
1325 case Hexagon::L2_ploadrhf_io:
1326 case Hexagon::L2_ploadrbt_io:
1327 case Hexagon::L2_ploadrbf_io:
1328 case Hexagon::L2_ploadruht_io:
1329 case Hexagon::L2_ploadruhf_io:
1330 case Hexagon::L2_ploadrubt_io:
1331 case Hexagon::L2_ploadrubf_io:
1332 case Hexagon::L2_ploadrdt_pi:
1333 case Hexagon::L2_ploadrdf_pi:
1334 case Hexagon::L2_ploadrit_pi:
1335 case Hexagon::L2_ploadrif_pi:
1336 case Hexagon::L2_ploadrht_pi:
1337 case Hexagon::L2_ploadrhf_pi:
1338 case Hexagon::L2_ploadrbt_pi:
1339 case Hexagon::L2_ploadrbf_pi:
1340 case Hexagon::L2_ploadruht_pi:
1341 case Hexagon::L2_ploadruhf_pi:
1342 case Hexagon::L2_ploadrubt_pi:
1343 case Hexagon::L2_ploadrubf_pi:
1344 case Hexagon::L4_ploadrdt_rr:
1345 case Hexagon::L4_ploadrdf_rr:
1346 case Hexagon::L4_ploadrbt_rr:
1347 case Hexagon::L4_ploadrbf_rr:
1348 case Hexagon::L4_ploadrubt_rr:
1349 case Hexagon::L4_ploadrubf_rr:
1350 case Hexagon::L4_ploadrht_rr:
1351 case Hexagon::L4_ploadrhf_rr:
1352 case Hexagon::L4_ploadruht_rr:
1353 case Hexagon::L4_ploadruhf_rr:
1354 case Hexagon::L4_ploadrit_rr:
1355 case Hexagon::L4_ploadrif_rr:
1360 // Returns true if an instruction is a conditional store.
1362 // Note: It doesn't include conditional new-value stores as they can't be
1363 // converted to .new predicate.
1365 // p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ]
1367 // / \ (not OK. it will cause new-value store to be
1368 // / X conditional on p0.new while R2 producer is
1371 // p.new store p.old NV store
1372 // [if(p0.new)memw(R0+#0)=R2] [if(p0)memw(R0+#0)=R2.new]
1378 // [if (p0)memw(R0+#0)=R2]
1380 // The above diagram shows the steps involoved in the conversion of a predicated
1381 // store instruction to its .new predicated new-value form.
1383 // The following set of instructions further explains the scenario where
1384 // conditional new-value store becomes invalid when promoted to .new predicate
1387 // { 1) if (p0) r0 = add(r1, r2)
1388 // 2) p0 = cmp.eq(r3, #0) }
1390 // 3) if (p0) memb(r1+#0) = r0 --> this instruction can't be grouped with
1391 // the first two instructions because in instr 1, r0 is conditional on old value
1392 // of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which
1393 // is not valid for new-value stores.
1394 bool HexagonInstrInfo::
1395 isConditionalStore (const MachineInstr* MI) const {
1396 const HexagonRegisterInfo& QRI = getRegisterInfo();
1397 switch (MI->getOpcode())
1399 default: return false;
1400 case Hexagon::S4_storeirbt_io:
1401 case Hexagon::S4_storeirbf_io:
1402 case Hexagon::S4_pstorerbt_rr:
1403 case Hexagon::S4_pstorerbf_rr:
1404 case Hexagon::S2_pstorerbt_io:
1405 case Hexagon::S2_pstorerbf_io:
1406 case Hexagon::S2_pstorerbt_pi:
1407 case Hexagon::S2_pstorerbf_pi:
1408 case Hexagon::S2_pstorerdt_io:
1409 case Hexagon::S2_pstorerdf_io:
1410 case Hexagon::S4_pstorerdt_rr:
1411 case Hexagon::S4_pstorerdf_rr:
1412 case Hexagon::S2_pstorerdt_pi:
1413 case Hexagon::S2_pstorerdf_pi:
1414 case Hexagon::S2_pstorerht_io:
1415 case Hexagon::S2_pstorerhf_io:
1416 case Hexagon::S4_storeirht_io:
1417 case Hexagon::S4_storeirhf_io:
1418 case Hexagon::S4_pstorerht_rr:
1419 case Hexagon::S4_pstorerhf_rr:
1420 case Hexagon::S2_pstorerht_pi:
1421 case Hexagon::S2_pstorerhf_pi:
1422 case Hexagon::S2_pstorerit_io:
1423 case Hexagon::S2_pstorerif_io:
1424 case Hexagon::S4_storeirit_io:
1425 case Hexagon::S4_storeirif_io:
1426 case Hexagon::S4_pstorerit_rr:
1427 case Hexagon::S4_pstorerif_rr:
1428 case Hexagon::S2_pstorerit_pi:
1429 case Hexagon::S2_pstorerif_pi:
1431 // V4 global address store before promoting to dot new.
1432 case Hexagon::S4_pstorerdt_abs:
1433 case Hexagon::S4_pstorerdf_abs:
1434 case Hexagon::S4_pstorerbt_abs:
1435 case Hexagon::S4_pstorerbf_abs:
1436 case Hexagon::S4_pstorerht_abs:
1437 case Hexagon::S4_pstorerhf_abs:
1438 case Hexagon::S4_pstorerit_abs:
1439 case Hexagon::S4_pstorerif_abs:
1442 // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
1443 // from the "Conditional Store" list. Because a predicated new value store
1444 // would NOT be promoted to a double dot new store. See diagram below:
1445 // This function returns yes for those stores that are predicated but not
1446 // yet promoted to predicate dot new instructions.
1448 // +---------------------+
1449 // /-----| if (p0) memw(..)=r0 |---------\~
1450 // || +---------------------+ ||
1451 // promote || /\ /\ || promote
1453 // \||/ demote || \||/
1455 // +-------------------------+ || +-------------------------+
1456 // | if (p0.new) memw(..)=r0 | || | if (p0) memw(..)=r0.new |
1457 // +-------------------------+ || +-------------------------+
1460 // promote || \/ NOT possible
1464 // +-----------------------------+
1465 // | if (p0.new) memw(..)=r0.new |
1466 // +-----------------------------+
1467 // Double Dot New Store
1473 bool HexagonInstrInfo::isNewValueJump(const MachineInstr *MI) const {
1474 if (isNewValue(MI) && isBranch(MI))
1479 bool HexagonInstrInfo::isPostIncrement (const MachineInstr* MI) const {
1480 return (getAddrMode(MI) == HexagonII::PostInc);
1483 bool HexagonInstrInfo::isNewValue(const MachineInstr* MI) const {
1484 const uint64_t F = MI->getDesc().TSFlags;
1485 return ((F >> HexagonII::NewValuePos) & HexagonII::NewValueMask);
1488 // Returns true, if any one of the operands is a dot new
1489 // insn, whether it is predicated dot new or register dot new.
1490 bool HexagonInstrInfo::isDotNewInst (const MachineInstr* MI) const {
1491 return (isNewValueInst(MI) ||
1492 (isPredicated(MI) && isPredicatedNew(MI)));
1495 // Returns the most basic instruction for the .new predicated instructions and
1496 // new-value stores.
1497 // For example, all of the following instructions will be converted back to the
1498 // same instruction:
1499 // 1) if (p0.new) memw(R0+#0) = R1.new --->
1500 // 2) if (p0) memw(R0+#0)= R1.new -------> if (p0) memw(R0+#0) = R1
1501 // 3) if (p0.new) memw(R0+#0) = R1 --->
1504 int HexagonInstrInfo::GetDotOldOp(const int opc) const {
1506 if (isPredicated(NewOp) && isPredicatedNew(NewOp)) { // Get predicate old form
1507 NewOp = Hexagon::getPredOldOpcode(NewOp);
1508 assert(NewOp >= 0 &&
1509 "Couldn't change predicate new instruction to its old form.");
1512 if (isNewValueStore(NewOp)) { // Convert into non-new-value format
1513 NewOp = Hexagon::getNonNVStore(NewOp);
1514 assert(NewOp >= 0 && "Couldn't change new-value store to its old form.");
1519 // Return the new value instruction for a given store.
1520 int HexagonInstrInfo::GetDotNewOp(const MachineInstr* MI) const {
1521 int NVOpcode = Hexagon::getNewValueOpcode(MI->getOpcode());
1522 if (NVOpcode >= 0) // Valid new-value store instruction.
1525 switch (MI->getOpcode()) {
1526 default: llvm_unreachable("Unknown .new type");
1527 // store new value byte
1528 case Hexagon::S4_storerb_ur:
1529 return Hexagon::S4_storerbnew_ur;
1531 case Hexagon::S4_storerh_ur:
1532 return Hexagon::S4_storerhnew_ur;
1534 case Hexagon::S4_storeri_ur:
1535 return Hexagon::S4_storerinew_ur;
1541 // Return .new predicate version for an instruction.
1542 int HexagonInstrInfo::GetDotNewPredOp(MachineInstr *MI,
1543 const MachineBranchProbabilityInfo
1546 int NewOpcode = Hexagon::getPredNewOpcode(MI->getOpcode());
1547 if (NewOpcode >= 0) // Valid predicate new instruction
1550 switch (MI->getOpcode()) {
1551 default: llvm_unreachable("Unknown .new type");
1553 case Hexagon::J2_jumpt:
1554 case Hexagon::J2_jumpf:
1555 return getDotNewPredJumpOp(MI, MBPI);
1557 case Hexagon::J2_jumprt:
1558 return Hexagon::J2_jumptnewpt;
1560 case Hexagon::J2_jumprf:
1561 return Hexagon::J2_jumprfnewpt;
1563 case Hexagon::JMPrett:
1564 return Hexagon::J2_jumprtnewpt;
1566 case Hexagon::JMPretf:
1567 return Hexagon::J2_jumprfnewpt;
1570 // Conditional combine
1571 case Hexagon::C2_ccombinewt:
1572 return Hexagon::C2_ccombinewnewt;
1573 case Hexagon::C2_ccombinewf:
1574 return Hexagon::C2_ccombinewnewf;
1579 unsigned HexagonInstrInfo::getAddrMode(const MachineInstr* MI) const {
1580 const uint64_t F = MI->getDesc().TSFlags;
1582 return((F >> HexagonII::AddrModePos) & HexagonII::AddrModeMask);
1585 /// immediateExtend - Changes the instruction in place to one using an immediate
1587 void HexagonInstrInfo::immediateExtend(MachineInstr *MI) const {
1588 assert((isExtendable(MI)||isConstExtended(MI)) &&
1589 "Instruction must be extendable");
1590 // Find which operand is extendable.
1591 short ExtOpNum = getCExtOpNum(MI);
1592 MachineOperand &MO = MI->getOperand(ExtOpNum);
1593 // This needs to be something we understand.
1594 assert((MO.isMBB() || MO.isImm()) &&
1595 "Branch with unknown extendable field type");
1596 // Mark given operand as extended.
1597 MO.addTargetFlag(HexagonII::HMOTF_ConstExtended);
1600 DFAPacketizer *HexagonInstrInfo::CreateTargetScheduleState(
1601 const TargetSubtargetInfo &STI) const {
1602 const InstrItineraryData *II = STI.getInstrItineraryData();
1603 return static_cast<const HexagonSubtarget &>(STI).createDFAPacketizer(II);
1606 bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1607 const MachineBasicBlock *MBB,
1608 const MachineFunction &MF) const {
1609 // Debug info is never a scheduling boundary. It's necessary to be explicit
1610 // due to the special treatment of IT instructions below, otherwise a
1611 // dbg_value followed by an IT will result in the IT instruction being
1612 // considered a scheduling hazard, which is wrong. It should be the actual
1613 // instruction preceding the dbg_value instruction(s), just like it is
1614 // when debug info is not present.
1615 if (MI->isDebugValue())
1618 // Terminators and labels can't be scheduled around.
1619 if (MI->getDesc().isTerminator() || MI->isPosition() || MI->isInlineAsm())
1625 bool HexagonInstrInfo::isConstExtended(MachineInstr *MI) const {
1626 const uint64_t F = MI->getDesc().TSFlags;
1627 unsigned isExtended = (F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;
1628 if (isExtended) // Instruction must be extended.
1631 unsigned isExtendable = (F >> HexagonII::ExtendablePos)
1632 & HexagonII::ExtendableMask;
1636 short ExtOpNum = getCExtOpNum(MI);
1637 const MachineOperand &MO = MI->getOperand(ExtOpNum);
1638 // Use MO operand flags to determine if MO
1639 // has the HMOTF_ConstExtended flag set.
1640 if (MO.getTargetFlags() && HexagonII::HMOTF_ConstExtended)
1642 // If this is a Machine BB address we are talking about, and it is
1643 // not marked as extended, say so.
1647 // We could be using an instruction with an extendable immediate and shoehorn
1648 // a global address into it. If it is a global address it will be constant
1649 // extended. We do this for COMBINE.
1650 // We currently only handle isGlobal() because it is the only kind of
1651 // object we are going to end up with here for now.
1652 // In the future we probably should add isSymbol(), etc.
1653 if (MO.isGlobal() || MO.isSymbol())
1656 // If the extendable operand is not 'Immediate' type, the instruction should
1657 // have 'isExtended' flag set.
1658 assert(MO.isImm() && "Extendable operand must be Immediate type");
1660 int MinValue = getMinValue(MI);
1661 int MaxValue = getMaxValue(MI);
1662 int ImmValue = MO.getImm();
1664 return (ImmValue < MinValue || ImmValue > MaxValue);
1667 // Returns the opcode to use when converting MI, which is a conditional jump,
1668 // into a conditional instruction which uses the .new value of the predicate.
1669 // We also use branch probabilities to add a hint to the jump.
1671 HexagonInstrInfo::getDotNewPredJumpOp(MachineInstr *MI,
1673 MachineBranchProbabilityInfo *MBPI) const {
1675 // We assume that block can have at most two successors.
1677 MachineBasicBlock *Src = MI->getParent();
1678 MachineOperand *BrTarget = &MI->getOperand(1);
1679 MachineBasicBlock *Dst = BrTarget->getMBB();
1681 const BranchProbability Prediction = MBPI->getEdgeProbability(Src, Dst);
1682 if (Prediction >= BranchProbability(1,2))
1685 switch (MI->getOpcode()) {
1686 case Hexagon::J2_jumpt:
1687 return taken ? Hexagon::J2_jumptnewpt : Hexagon::J2_jumptnew;
1688 case Hexagon::J2_jumpf:
1689 return taken ? Hexagon::J2_jumpfnewpt : Hexagon::J2_jumpfnew;
1692 llvm_unreachable("Unexpected jump instruction.");
1695 // Returns true if a particular operand is extendable for an instruction.
1696 bool HexagonInstrInfo::isOperandExtended(const MachineInstr *MI,
1697 unsigned short OperandNum) const {
1698 const uint64_t F = MI->getDesc().TSFlags;
1700 return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask)
1704 // Returns Operand Index for the constant extended instruction.
1705 unsigned short HexagonInstrInfo::getCExtOpNum(const MachineInstr *MI) const {
1706 const uint64_t F = MI->getDesc().TSFlags;
1707 return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask);
1710 // Returns the min value that doesn't need to be extended.
1711 int HexagonInstrInfo::getMinValue(const MachineInstr *MI) const {
1712 const uint64_t F = MI->getDesc().TSFlags;
1713 unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
1714 & HexagonII::ExtentSignedMask;
1715 unsigned bits = (F >> HexagonII::ExtentBitsPos)
1716 & HexagonII::ExtentBitsMask;
1718 if (isSigned) // if value is signed
1719 return -1U << (bits - 1);
1724 // Returns the max value that doesn't need to be extended.
1725 int HexagonInstrInfo::getMaxValue(const MachineInstr *MI) const {
1726 const uint64_t F = MI->getDesc().TSFlags;
1727 unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
1728 & HexagonII::ExtentSignedMask;
1729 unsigned bits = (F >> HexagonII::ExtentBitsPos)
1730 & HexagonII::ExtentBitsMask;
1732 if (isSigned) // if value is signed
1733 return ~(-1U << (bits - 1));
1735 return ~(-1U << bits);
1738 // Returns true if an instruction can be converted into a non-extended
1739 // equivalent instruction.
1740 bool HexagonInstrInfo::NonExtEquivalentExists (const MachineInstr *MI) const {
1743 // Check if the instruction has a register form that uses register in place
1744 // of the extended operand, if so return that as the non-extended form.
1745 if (Hexagon::getRegForm(MI->getOpcode()) >= 0)
1748 if (MI->getDesc().mayLoad() || MI->getDesc().mayStore()) {
1749 // Check addressing mode and retrieve non-ext equivalent instruction.
1751 switch (getAddrMode(MI)) {
1752 case HexagonII::Absolute :
1753 // Load/store with absolute addressing mode can be converted into
1754 // base+offset mode.
1755 NonExtOpcode = Hexagon::getBasedWithImmOffset(MI->getOpcode());
1757 case HexagonII::BaseImmOffset :
1758 // Load/store with base+offset addressing mode can be converted into
1759 // base+register offset addressing mode. However left shift operand should
1761 NonExtOpcode = Hexagon::getBaseWithRegOffset(MI->getOpcode());
1766 if (NonExtOpcode < 0)
1773 // Returns opcode of the non-extended equivalent instruction.
1774 short HexagonInstrInfo::getNonExtOpcode (const MachineInstr *MI) const {
1776 // Check if the instruction has a register form that uses register in place
1777 // of the extended operand, if so return that as the non-extended form.
1778 short NonExtOpcode = Hexagon::getRegForm(MI->getOpcode());
1779 if (NonExtOpcode >= 0)
1780 return NonExtOpcode;
1782 if (MI->getDesc().mayLoad() || MI->getDesc().mayStore()) {
1783 // Check addressing mode and retrieve non-ext equivalent instruction.
1784 switch (getAddrMode(MI)) {
1785 case HexagonII::Absolute :
1786 return Hexagon::getBasedWithImmOffset(MI->getOpcode());
1787 case HexagonII::BaseImmOffset :
1788 return Hexagon::getBaseWithRegOffset(MI->getOpcode());
1796 bool HexagonInstrInfo::PredOpcodeHasJMP_c(Opcode_t Opcode) const {
1797 return (Opcode == Hexagon::J2_jumpt) ||
1798 (Opcode == Hexagon::J2_jumpf) ||
1799 (Opcode == Hexagon::J2_jumptnewpt) ||
1800 (Opcode == Hexagon::J2_jumpfnewpt) ||
1801 (Opcode == Hexagon::J2_jumpt) ||
1802 (Opcode == Hexagon::J2_jumpf);
1805 bool HexagonInstrInfo::PredOpcodeHasNot(Opcode_t Opcode) const {
1806 return (Opcode == Hexagon::J2_jumpf) ||
1807 (Opcode == Hexagon::J2_jumpfnewpt) ||
1808 (Opcode == Hexagon::J2_jumpfnew);