1 //==- HexagonInstrFormats.td - Hexagon Instruction Formats --*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Hexagon Intruction Flags +
13 // *** Must match HexagonBaseInfo.h ***
14 //===----------------------------------------------------------------------===//
16 class Type<bits<5> t> {
19 def TypePSEUDO : Type<0>;
20 def TypeALU32 : Type<1>;
26 def TypeSYSTEM : Type<7>;
27 def TypeXTYPE : Type<8>;
28 def TypeMARKER : Type<31>;
30 //===----------------------------------------------------------------------===//
31 // Intruction Class Declaration +
32 //===----------------------------------------------------------------------===//
34 class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
35 string cstr, InstrItinClass itin, Type type> : Instruction {
38 let Namespace = "Hexagon";
40 dag OutOperandList = outs;
41 dag InOperandList = ins;
42 let AsmString = asmstr;
43 let Pattern = pattern;
44 let Constraints = cstr;
47 // *** Must match HexagonBaseInfo.h ***
48 Type HexagonType = type;
49 let TSFlags{4-0} = HexagonType.Value;
50 bits<1> isHexagonSolo = 0;
51 let TSFlags{5} = isHexagonSolo;
53 // Predicated instructions.
54 bits<1> isPredicated = 0;
55 let TSFlags{6} = isPredicated;
57 // *** The code above must match HexagonBaseInfo.h ***
60 //===----------------------------------------------------------------------===//
61 // Intruction Classes Definitions +
62 //===----------------------------------------------------------------------===//
64 // LD Instruction Class in V2/V3/V4.
65 // Definition of the instruction class NOT CHANGED.
66 class LDInst<dag outs, dag ins, string asmstr, list<dag> pattern>
67 : InstHexagon<outs, ins, asmstr, pattern, "", LD, TypeLD> {
73 class LDInst2<dag outs, dag ins, string asmstr, list<dag> pattern>
74 : InstHexagon<outs, ins, asmstr, pattern, "", LD, TypeLD> {
81 // LD Instruction Class in V2/V3/V4.
82 // Definition of the instruction class NOT CHANGED.
83 class LDInstPost<dag outs, dag ins, string asmstr, list<dag> pattern,
85 : InstHexagon<outs, ins, asmstr, pattern, cstr, LD, TypeLD> {
92 // ST Instruction Class in V2/V3 can take SLOT0 only.
93 // ST Instruction Class in V4 can take SLOT0 & SLOT1.
94 // Definition of the instruction class CHANGED from V2/V3 to V4.
95 class STInst<dag outs, dag ins, string asmstr, list<dag> pattern>
96 : InstHexagon<outs, ins, asmstr, pattern, "", ST, TypeST> {
102 class STInst2<dag outs, dag ins, string asmstr, list<dag> pattern>
103 : InstHexagon<outs, ins, asmstr, pattern, "", ST, TypeST> {
110 // SYSTEM Instruction Class in V4 can take SLOT0 only
111 // In V2/V3 we used ST for this but in v4 ST can take SLOT0 or SLOT1.
112 class SYSInst<dag outs, dag ins, string asmstr, list<dag> pattern>
113 : InstHexagon<outs, ins, asmstr, pattern, "", SYS, TypeSYSTEM> {
119 // ST Instruction Class in V2/V3 can take SLOT0 only.
120 // ST Instruction Class in V4 can take SLOT0 & SLOT1.
121 // Definition of the instruction class CHANGED from V2/V3 to V4.
122 class STInstPost<dag outs, dag ins, string asmstr, list<dag> pattern,
124 : InstHexagon<outs, ins, asmstr, pattern, cstr, ST, TypeST> {
131 // ALU32 Instruction Class in V2/V3/V4.
132 // Definition of the instruction class NOT CHANGED.
133 class ALU32Type<dag outs, dag ins, string asmstr, list<dag> pattern>
134 : InstHexagon<outs, ins, asmstr, pattern, "", ALU32, TypeALU32> {
142 // ALU64 Instruction Class in V2/V3.
143 // XTYPE Instruction Class in V4.
144 // Definition of the instruction class NOT CHANGED.
145 // Name of the Instruction Class changed from ALU64 to XTYPE from V2/V3 to V4.
146 class ALU64Type<dag outs, dag ins, string asmstr, list<dag> pattern>
147 : InstHexagon<outs, ins, asmstr, pattern, "", ALU64, TypeXTYPE> {
155 class ALU64_acc<dag outs, dag ins, string asmstr, list<dag> pattern,
157 : InstHexagon<outs, ins, asmstr, pattern, cstr, ALU64, TypeXTYPE> {
165 // M Instruction Class in V2/V3.
166 // XTYPE Instruction Class in V4.
167 // Definition of the instruction class NOT CHANGED.
168 // Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4.
169 class MInst<dag outs, dag ins, string asmstr, list<dag> pattern>
170 : InstHexagon<outs, ins, asmstr, pattern, "", M, TypeXTYPE> {
176 // M Instruction Class in V2/V3.
177 // XTYPE Instruction Class in V4.
178 // Definition of the instruction class NOT CHANGED.
179 // Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4.
180 class MInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern,
182 : InstHexagon<outs, ins, asmstr, pattern, cstr, M, TypeXTYPE> {
188 // S Instruction Class in V2/V3.
189 // XTYPE Instruction Class in V4.
190 // Definition of the instruction class NOT CHANGED.
191 // Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4.
192 class SInst<dag outs, dag ins, string asmstr, list<dag> pattern>
193 : InstHexagon<outs, ins, asmstr, pattern, "", S, TypeXTYPE> {
199 // S Instruction Class in V2/V3.
200 // XTYPE Instruction Class in V4.
201 // Definition of the instruction class NOT CHANGED.
202 // Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4.
203 class SInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern,
205 : InstHexagon<outs, ins, asmstr, pattern, cstr, S, TypeXTYPE> {
206 // : InstHexagon<outs, ins, asmstr, pattern, cstr, S> {
207 // : InstHexagon<outs, ins, asmstr, pattern, cstr, !if(V4T, XTYPE_V4, S)> {
213 // J Instruction Class in V2/V3/V4.
214 // Definition of the instruction class NOT CHANGED.
215 class JType<dag outs, dag ins, string asmstr, list<dag> pattern>
216 : InstHexagon<outs, ins, asmstr, pattern, "", J, TypeJ> {
220 // JR Instruction Class in V2/V3/V4.
221 // Definition of the instruction class NOT CHANGED.
222 class JRType<dag outs, dag ins, string asmstr, list<dag> pattern>
223 : InstHexagon<outs, ins, asmstr, pattern, "", JR, TypeJR> {
225 bits<5> pu; // Predicate register
228 // CR Instruction Class in V2/V3/V4.
229 // Definition of the instruction class NOT CHANGED.
230 class CRInst<dag outs, dag ins, string asmstr, list<dag> pattern>
231 : InstHexagon<outs, ins, asmstr, pattern, "", CR, TypeCR> {
236 class Marker<dag outs, dag ins, string asmstr, list<dag> pattern>
237 : InstHexagon<outs, ins, asmstr, pattern, "", MARKER, TypeMARKER> {
238 let isCodeGenOnly = 1;
242 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
243 : InstHexagon<outs, ins, asmstr, pattern, "", PSEUDO, TypePSEUDO> {
244 let isCodeGenOnly = 1;
248 //===----------------------------------------------------------------------===//
249 // Intruction Classes Definitions -
250 //===----------------------------------------------------------------------===//
256 class ALU32_rr<dag outs, dag ins, string asmstr, list<dag> pattern>
257 : ALU32Type<outs, ins, asmstr, pattern> {
260 class ALU32_ir<dag outs, dag ins, string asmstr, list<dag> pattern>
261 : ALU32Type<outs, ins, asmstr, pattern> {
265 class ALU32_ri<dag outs, dag ins, string asmstr, list<dag> pattern>
266 : ALU32Type<outs, ins, asmstr, pattern> {
270 class ALU32_ii<dag outs, dag ins, string asmstr, list<dag> pattern>
271 : ALU32Type<outs, ins, asmstr, pattern> {
278 class ALU64_rr<dag outs, dag ins, string asmstr, list<dag> pattern>
279 : ALU64Type<outs, ins, asmstr, pattern> {
282 class ALU64_ri<dag outs, dag ins, string asmstr, list<dag> pattern>
283 : ALU64Type<outs, ins, asmstr, pattern> {
287 // J Type Instructions.
288 class JInst<dag outs, dag ins, string asmstr, list<dag> pattern>
289 : JType<outs, ins, asmstr, pattern> {
292 // JR type Instructions.
293 class JRInst<dag outs, dag ins, string asmstr, list<dag> pattern>
294 : JRType<outs, ins, asmstr, pattern> {
298 // Post increment ST Instruction.
299 class STInstPI<dag outs, dag ins, string asmstr, list<dag> pattern, string cstr>
300 : STInstPost<outs, ins, asmstr, pattern, cstr> {
304 class STInst2PI<dag outs, dag ins, string asmstr, list<dag> pattern, string cstr>
305 : STInstPost<outs, ins, asmstr, pattern, cstr> {
312 // Post increment LD Instruction.
313 class LDInstPI<dag outs, dag ins, string asmstr, list<dag> pattern, string cstr>
314 : LDInstPost<outs, ins, asmstr, pattern, cstr> {
318 class LDInst2PI<dag outs, dag ins, string asmstr, list<dag> pattern, string cstr>
319 : LDInstPost<outs, ins, asmstr, pattern, cstr> {
325 //===----------------------------------------------------------------------===//
326 // V4 Instruction Format Definitions +
327 //===----------------------------------------------------------------------===//
329 include "HexagonInstrFormatsV4.td"
331 //===----------------------------------------------------------------------===//
332 // V4 Instruction Format Definitions +
333 //===----------------------------------------------------------------------===//