1 //==- HexagonInstrFormats.td - Hexagon Instruction Formats --*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Hexagon Intruction Flags +
13 // *** Must match HexagonBaseInfo.h ***
14 //===----------------------------------------------------------------------===//
16 class Type<bits<5> t> {
19 def TypePSEUDO : Type<0>;
20 def TypeALU32 : Type<1>;
26 def TypeSYSTEM : Type<7>;
27 def TypeXTYPE : Type<8>;
28 def TypeMARKER : Type<31>;
30 //===----------------------------------------------------------------------===//
31 // Intruction Class Declaration +
32 //===----------------------------------------------------------------------===//
34 class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
35 string cstr, InstrItinClass itin, Type type> : Instruction {
38 let Namespace = "Hexagon";
40 dag OutOperandList = outs;
41 dag InOperandList = ins;
42 let AsmString = asmstr;
43 let Pattern = pattern;
44 let Constraints = cstr;
48 // *** Must match HexagonBaseInfo.h ***
49 // Instruction type according to the ISA.
50 Type HexagonType = type;
51 let TSFlags{4-0} = HexagonType.Value;
52 // Solo instructions, i.e., those that cannot be in a packet with others.
53 bits<1> isHexagonSolo = 0;
54 let TSFlags{5} = isHexagonSolo;
55 // Predicated instructions.
56 bits<1> isPredicated = 0;
57 let TSFlags{6} = isPredicated;
59 // Dot new value store instructions.
60 bits<1> isNVStore = 0;
61 let TSFlags{8} = isNVStore;
63 // Fields used for relation models.
64 string BaseOpcode = "";
65 string CextOpcode = "";
66 string PredSense = "";
67 string PNewValue = "";
68 string InputType = ""; // Input is "imm" or "reg" type.
69 // *** The code above must match HexagonBaseInfo.h ***
72 //===----------------------------------------------------------------------===//
73 // Intruction Classes Definitions +
74 //===----------------------------------------------------------------------===//
76 // LD Instruction Class in V2/V3/V4.
77 // Definition of the instruction class NOT CHANGED.
78 class LDInst<dag outs, dag ins, string asmstr, list<dag> pattern>
79 : InstHexagon<outs, ins, asmstr, pattern, "", LD, TypeLD> {
85 class LDInst2<dag outs, dag ins, string asmstr, list<dag> pattern>
86 : InstHexagon<outs, ins, asmstr, pattern, "", LD, TypeLD> {
93 // LD Instruction Class in V2/V3/V4.
94 // Definition of the instruction class NOT CHANGED.
95 class LDInstPost<dag outs, dag ins, string asmstr, list<dag> pattern,
97 : InstHexagon<outs, ins, asmstr, pattern, cstr, LD, TypeLD> {
104 // ST Instruction Class in V2/V3 can take SLOT0 only.
105 // ST Instruction Class in V4 can take SLOT0 & SLOT1.
106 // Definition of the instruction class CHANGED from V2/V3 to V4.
107 class STInst<dag outs, dag ins, string asmstr, list<dag> pattern>
108 : InstHexagon<outs, ins, asmstr, pattern, "", ST, TypeST> {
114 class STInst2<dag outs, dag ins, string asmstr, list<dag> pattern>
115 : InstHexagon<outs, ins, asmstr, pattern, "", ST, TypeST> {
122 // SYSTEM Instruction Class in V4 can take SLOT0 only
123 // In V2/V3 we used ST for this but in v4 ST can take SLOT0 or SLOT1.
124 class SYSInst<dag outs, dag ins, string asmstr, list<dag> pattern>
125 : InstHexagon<outs, ins, asmstr, pattern, "", SYS, TypeSYSTEM> {
131 // ST Instruction Class in V2/V3 can take SLOT0 only.
132 // ST Instruction Class in V4 can take SLOT0 & SLOT1.
133 // Definition of the instruction class CHANGED from V2/V3 to V4.
134 class STInstPost<dag outs, dag ins, string asmstr, list<dag> pattern,
136 : InstHexagon<outs, ins, asmstr, pattern, cstr, ST, TypeST> {
143 // ALU32 Instruction Class in V2/V3/V4.
144 // Definition of the instruction class NOT CHANGED.
145 class ALU32Type<dag outs, dag ins, string asmstr, list<dag> pattern>
146 : InstHexagon<outs, ins, asmstr, pattern, "", ALU32, TypeALU32> {
154 // ALU64 Instruction Class in V2/V3.
155 // XTYPE Instruction Class in V4.
156 // Definition of the instruction class NOT CHANGED.
157 // Name of the Instruction Class changed from ALU64 to XTYPE from V2/V3 to V4.
158 class ALU64Type<dag outs, dag ins, string asmstr, list<dag> pattern>
159 : InstHexagon<outs, ins, asmstr, pattern, "", ALU64, TypeXTYPE> {
167 class ALU64_acc<dag outs, dag ins, string asmstr, list<dag> pattern,
169 : InstHexagon<outs, ins, asmstr, pattern, cstr, ALU64, TypeXTYPE> {
177 // M Instruction Class in V2/V3.
178 // XTYPE Instruction Class in V4.
179 // Definition of the instruction class NOT CHANGED.
180 // Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4.
181 class MInst<dag outs, dag ins, string asmstr, list<dag> pattern>
182 : InstHexagon<outs, ins, asmstr, pattern, "", M, TypeXTYPE> {
188 // M Instruction Class in V2/V3.
189 // XTYPE Instruction Class in V4.
190 // Definition of the instruction class NOT CHANGED.
191 // Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4.
192 class MInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern,
194 : InstHexagon<outs, ins, asmstr, pattern, cstr, M, TypeXTYPE> {
200 // S Instruction Class in V2/V3.
201 // XTYPE Instruction Class in V4.
202 // Definition of the instruction class NOT CHANGED.
203 // Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4.
204 class SInst<dag outs, dag ins, string asmstr, list<dag> pattern>
205 : InstHexagon<outs, ins, asmstr, pattern, "", S, TypeXTYPE> {
211 // S Instruction Class in V2/V3.
212 // XTYPE Instruction Class in V4.
213 // Definition of the instruction class NOT CHANGED.
214 // Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4.
215 class SInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern,
217 : InstHexagon<outs, ins, asmstr, pattern, cstr, S, TypeXTYPE> {
218 // : InstHexagon<outs, ins, asmstr, pattern, cstr, S> {
219 // : InstHexagon<outs, ins, asmstr, pattern, cstr, !if(V4T, XTYPE_V4, S)> {
225 // J Instruction Class in V2/V3/V4.
226 // Definition of the instruction class NOT CHANGED.
227 class JType<dag outs, dag ins, string asmstr, list<dag> pattern>
228 : InstHexagon<outs, ins, asmstr, pattern, "", J, TypeJ> {
232 // JR Instruction Class in V2/V3/V4.
233 // Definition of the instruction class NOT CHANGED.
234 class JRType<dag outs, dag ins, string asmstr, list<dag> pattern>
235 : InstHexagon<outs, ins, asmstr, pattern, "", JR, TypeJR> {
237 bits<5> pu; // Predicate register
240 // CR Instruction Class in V2/V3/V4.
241 // Definition of the instruction class NOT CHANGED.
242 class CRInst<dag outs, dag ins, string asmstr, list<dag> pattern>
243 : InstHexagon<outs, ins, asmstr, pattern, "", CR, TypeCR> {
248 class Marker<dag outs, dag ins, string asmstr, list<dag> pattern>
249 : InstHexagon<outs, ins, asmstr, pattern, "", MARKER, TypeMARKER> {
250 let isCodeGenOnly = 1;
254 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
255 : InstHexagon<outs, ins, asmstr, pattern, "", PSEUDO, TypePSEUDO> {
256 let isCodeGenOnly = 1;
260 //===----------------------------------------------------------------------===//
261 // Intruction Classes Definitions -
262 //===----------------------------------------------------------------------===//
268 class ALU32_rr<dag outs, dag ins, string asmstr, list<dag> pattern>
269 : ALU32Type<outs, ins, asmstr, pattern> {
272 class ALU32_ir<dag outs, dag ins, string asmstr, list<dag> pattern>
273 : ALU32Type<outs, ins, asmstr, pattern> {
277 class ALU32_ri<dag outs, dag ins, string asmstr, list<dag> pattern>
278 : ALU32Type<outs, ins, asmstr, pattern> {
282 class ALU32_ii<dag outs, dag ins, string asmstr, list<dag> pattern>
283 : ALU32Type<outs, ins, asmstr, pattern> {
290 class ALU64_rr<dag outs, dag ins, string asmstr, list<dag> pattern>
291 : ALU64Type<outs, ins, asmstr, pattern> {
294 class ALU64_ri<dag outs, dag ins, string asmstr, list<dag> pattern>
295 : ALU64Type<outs, ins, asmstr, pattern> {
299 // J Type Instructions.
300 class JInst<dag outs, dag ins, string asmstr, list<dag> pattern>
301 : JType<outs, ins, asmstr, pattern> {
304 // JR type Instructions.
305 class JRInst<dag outs, dag ins, string asmstr, list<dag> pattern>
306 : JRType<outs, ins, asmstr, pattern> {
310 // Post increment ST Instruction.
311 class STInstPI<dag outs, dag ins, string asmstr, list<dag> pattern,
313 : STInstPost<outs, ins, asmstr, pattern, cstr> {
317 class STInst2PI<dag outs, dag ins, string asmstr, list<dag> pattern,
319 : STInstPost<outs, ins, asmstr, pattern, cstr> {
324 // Post increment LD Instruction.
325 class LDInstPI<dag outs, dag ins, string asmstr, list<dag> pattern,
327 : LDInstPost<outs, ins, asmstr, pattern, cstr> {
331 class LDInst2PI<dag outs, dag ins, string asmstr, list<dag> pattern,
333 : LDInstPost<outs, ins, asmstr, pattern, cstr> {
338 //===----------------------------------------------------------------------===//
339 // V4 Instruction Format Definitions +
340 //===----------------------------------------------------------------------===//
342 include "HexagonInstrFormatsV4.td"
344 //===----------------------------------------------------------------------===//
345 // V4 Instruction Format Definitions +
346 //===----------------------------------------------------------------------===//