1 //==- HexagonInstrFormats.td - Hexagon Instruction Formats --*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Hexagon Intruction Flags +
13 // *** Must match HexagonBaseInfo.h ***
14 //===----------------------------------------------------------------------===//
16 class Type<bits<5> t> {
19 def TypePSEUDO : Type<0>;
20 def TypeALU32 : Type<1>;
26 def TypeSYSTEM : Type<7>;
27 def TypeXTYPE : Type<8>;
28 def TypeMARKER : Type<31>;
30 // Maintain list of valid subtargets for each instruction.
31 class SubTarget<bits<4> value> {
32 bits<4> Value = value;
35 def HasV2SubT : SubTarget<0xf>;
36 def HasV2SubTOnly : SubTarget<0x1>;
37 def NoV2SubT : SubTarget<0x0>;
38 def HasV3SubT : SubTarget<0xe>;
39 def HasV3SubTOnly : SubTarget<0x2>;
40 def NoV3SubT : SubTarget<0x1>;
41 def HasV4SubT : SubTarget<0xc>;
42 def NoV4SubT : SubTarget<0x3>;
43 def HasV5SubT : SubTarget<0x8>;
44 def NoV5SubT : SubTarget<0x7>;
46 // Addressing modes for load/store instructions
47 class AddrModeType<bits<4> value> {
48 bits<4> Value = value;
51 def NoAddrMode : AddrModeType<0>; // No addressing mode
52 def Absolute : AddrModeType<1>; // Absolute addressing mode
53 def AbsoluteSet : AddrModeType<2>; // Absolute set addressing mode
54 def BaseImmOffset : AddrModeType<3>; // Indirect with offset
55 def BaseLongOffset : AddrModeType<4>; // Indirect with long offset
56 def BaseRegOffset : AddrModeType<5>; // Indirect with register offset
58 //===----------------------------------------------------------------------===//
59 // Intruction Class Declaration +
60 //===----------------------------------------------------------------------===//
62 class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
63 string cstr, InstrItinClass itin, Type type> : Instruction {
66 let Namespace = "Hexagon";
68 dag OutOperandList = outs;
69 dag InOperandList = ins;
70 let AsmString = asmstr;
71 let Pattern = pattern;
72 let Constraints = cstr;
76 // *** Must match HexagonBaseInfo.h ***
77 // Instruction type according to the ISA.
78 Type HexagonType = type;
79 let TSFlags{4-0} = HexagonType.Value;
80 // Solo instructions, i.e., those that cannot be in a packet with others.
81 bits<1> isHexagonSolo = 0;
82 let TSFlags{5} = isHexagonSolo;
83 // Predicated instructions.
84 bits<1> isPredicated = 0;
85 let TSFlags{6} = isPredicated;
86 bits<1> isPredicatedNew = 0;
87 let TSFlags{7} = isPredicatedNew;
89 // Stores that can be newified.
90 bits<1> isNVStorable = 0;
91 let TSFlags{8} = isNVStorable;
93 // New-value store instructions.
94 bits<1> isNVStore = 0;
95 let TSFlags{9} = isNVStore;
97 // Immediate extender helper fields.
98 bits<1> isExtendable = 0;
99 let TSFlags{10} = isExtendable; // Insn may be extended.
100 bits<1> isExtended = 0;
101 let TSFlags{11} = isExtended; // Insn must be extended.
102 bits<3> opExtendable = 0;
103 let TSFlags{14-12} = opExtendable; // Which operand may be extended.
104 bits<1> isExtentSigned = 0;
105 let TSFlags{15} = isExtentSigned; // Signed or unsigned range.
106 bits<5> opExtentBits = 0;
107 let TSFlags{20-16} = opExtentBits; //Number of bits of range before extending.
109 // If an instruction is valid on a subtarget (v2-v5), set the corresponding
110 // bit from validSubTargets. v2 is the least significant bit.
111 // By default, instruction is valid on all subtargets.
112 SubTarget validSubTargets = HasV2SubT;
113 let TSFlags{24-21} = validSubTargets.Value;
115 // Addressing mode for load/store instrutions.
116 AddrModeType addrMode = NoAddrMode;
117 let TSFlags{28-25} = addrMode.Value;
119 // Fields used for relation models.
120 string BaseOpcode = "";
121 string CextOpcode = "";
122 string PredSense = "";
123 string PNewValue = "";
124 string InputType = ""; // Input is "imm" or "reg" type.
125 string isMEMri = "false"; // Set to "true" for load/store with MEMri operand.
126 string isFloat = "false"; // Set to "true" for the floating-point load/store.
128 // *** Must match MCTargetDesc/HexagonBaseInfo.h ***
131 //===----------------------------------------------------------------------===//
132 // Intruction Classes Definitions +
133 //===----------------------------------------------------------------------===//
135 // LD Instruction Class in V2/V3/V4.
136 // Definition of the instruction class NOT CHANGED.
137 class LDInst<dag outs, dag ins, string asmstr, list<dag> pattern>
138 : InstHexagon<outs, ins, asmstr, pattern, "", LD, TypeLD> {
144 class LDInst2<dag outs, dag ins, string asmstr, list<dag> pattern>
145 : InstHexagon<outs, ins, asmstr, pattern, "", LD, TypeLD> {
152 // LD Instruction Class in V2/V3/V4.
153 // Definition of the instruction class NOT CHANGED.
154 class LDInstPost<dag outs, dag ins, string asmstr, list<dag> pattern,
156 : InstHexagon<outs, ins, asmstr, pattern, cstr, LD, TypeLD> {
163 // ST Instruction Class in V2/V3 can take SLOT0 only.
164 // ST Instruction Class in V4 can take SLOT0 & SLOT1.
165 // Definition of the instruction class CHANGED from V2/V3 to V4.
166 class STInst<dag outs, dag ins, string asmstr, list<dag> pattern>
167 : InstHexagon<outs, ins, asmstr, pattern, "", ST, TypeST> {
173 class STInst2<dag outs, dag ins, string asmstr, list<dag> pattern>
174 : InstHexagon<outs, ins, asmstr, pattern, "", ST, TypeST> {
181 // SYSTEM Instruction Class in V4 can take SLOT0 only
182 // In V2/V3 we used ST for this but in v4 ST can take SLOT0 or SLOT1.
183 class SYSInst<dag outs, dag ins, string asmstr, list<dag> pattern>
184 : InstHexagon<outs, ins, asmstr, pattern, "", SYS, TypeSYSTEM> {
190 // ST Instruction Class in V2/V3 can take SLOT0 only.
191 // ST Instruction Class in V4 can take SLOT0 & SLOT1.
192 // Definition of the instruction class CHANGED from V2/V3 to V4.
193 class STInstPost<dag outs, dag ins, string asmstr, list<dag> pattern,
195 : InstHexagon<outs, ins, asmstr, pattern, cstr, ST, TypeST> {
202 // ALU32 Instruction Class in V2/V3/V4.
203 // Definition of the instruction class NOT CHANGED.
204 class ALU32Type<dag outs, dag ins, string asmstr, list<dag> pattern>
205 : InstHexagon<outs, ins, asmstr, pattern, "", ALU32, TypeALU32> {
213 // ALU64 Instruction Class in V2/V3.
214 // XTYPE Instruction Class in V4.
215 // Definition of the instruction class NOT CHANGED.
216 // Name of the Instruction Class changed from ALU64 to XTYPE from V2/V3 to V4.
217 class ALU64Type<dag outs, dag ins, string asmstr, list<dag> pattern>
218 : InstHexagon<outs, ins, asmstr, pattern, "", ALU64, TypeXTYPE> {
226 class ALU64_acc<dag outs, dag ins, string asmstr, list<dag> pattern,
228 : InstHexagon<outs, ins, asmstr, pattern, cstr, ALU64, TypeXTYPE> {
236 // M Instruction Class in V2/V3.
237 // XTYPE Instruction Class in V4.
238 // Definition of the instruction class NOT CHANGED.
239 // Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4.
240 class MInst<dag outs, dag ins, string asmstr, list<dag> pattern>
241 : InstHexagon<outs, ins, asmstr, pattern, "", M, TypeXTYPE> {
247 // M Instruction Class in V2/V3.
248 // XTYPE Instruction Class in V4.
249 // Definition of the instruction class NOT CHANGED.
250 // Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4.
251 class MInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern,
253 : InstHexagon<outs, ins, asmstr, pattern, cstr, M, TypeXTYPE> {
259 // S Instruction Class in V2/V3.
260 // XTYPE Instruction Class in V4.
261 // Definition of the instruction class NOT CHANGED.
262 // Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4.
263 class SInst<dag outs, dag ins, string asmstr, list<dag> pattern>
264 : InstHexagon<outs, ins, asmstr, pattern, "", S, TypeXTYPE> {
270 // S Instruction Class in V2/V3.
271 // XTYPE Instruction Class in V4.
272 // Definition of the instruction class NOT CHANGED.
273 // Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4.
274 class SInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern,
276 : InstHexagon<outs, ins, asmstr, pattern, cstr, S, TypeXTYPE> {
277 // : InstHexagon<outs, ins, asmstr, pattern, cstr, S> {
278 // : InstHexagon<outs, ins, asmstr, pattern, cstr, !if(V4T, XTYPE_V4, S)> {
284 // J Instruction Class in V2/V3/V4.
285 // Definition of the instruction class NOT CHANGED.
286 class JType<dag outs, dag ins, string asmstr, list<dag> pattern>
287 : InstHexagon<outs, ins, asmstr, pattern, "", J, TypeJ> {
291 // JR Instruction Class in V2/V3/V4.
292 // Definition of the instruction class NOT CHANGED.
293 class JRType<dag outs, dag ins, string asmstr, list<dag> pattern>
294 : InstHexagon<outs, ins, asmstr, pattern, "", JR, TypeJR> {
296 bits<5> pu; // Predicate register
299 // CR Instruction Class in V2/V3/V4.
300 // Definition of the instruction class NOT CHANGED.
301 class CRInst<dag outs, dag ins, string asmstr, list<dag> pattern>
302 : InstHexagon<outs, ins, asmstr, pattern, "", CR, TypeCR> {
307 class Marker<dag outs, dag ins, string asmstr, list<dag> pattern>
308 : InstHexagon<outs, ins, asmstr, pattern, "", MARKER, TypeMARKER> {
309 let isCodeGenOnly = 1;
313 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
314 : InstHexagon<outs, ins, asmstr, pattern, "", PSEUDO, TypePSEUDO> {
315 let isCodeGenOnly = 1;
319 //===----------------------------------------------------------------------===//
320 // Intruction Classes Definitions -
321 //===----------------------------------------------------------------------===//
327 class ALU32_rr<dag outs, dag ins, string asmstr, list<dag> pattern>
328 : ALU32Type<outs, ins, asmstr, pattern> {
331 class ALU32_ir<dag outs, dag ins, string asmstr, list<dag> pattern>
332 : ALU32Type<outs, ins, asmstr, pattern> {
336 class ALU32_ri<dag outs, dag ins, string asmstr, list<dag> pattern>
337 : ALU32Type<outs, ins, asmstr, pattern> {
341 class ALU32_ii<dag outs, dag ins, string asmstr, list<dag> pattern>
342 : ALU32Type<outs, ins, asmstr, pattern> {
349 class ALU64_rr<dag outs, dag ins, string asmstr, list<dag> pattern>
350 : ALU64Type<outs, ins, asmstr, pattern> {
353 class ALU64_ri<dag outs, dag ins, string asmstr, list<dag> pattern>
354 : ALU64Type<outs, ins, asmstr, pattern> {
358 // J Type Instructions.
359 class JInst<dag outs, dag ins, string asmstr, list<dag> pattern>
360 : JType<outs, ins, asmstr, pattern> {
363 // JR type Instructions.
364 class JRInst<dag outs, dag ins, string asmstr, list<dag> pattern>
365 : JRType<outs, ins, asmstr, pattern> {
369 // Post increment ST Instruction.
370 class STInstPI<dag outs, dag ins, string asmstr, list<dag> pattern,
372 : STInstPost<outs, ins, asmstr, pattern, cstr> {
376 class STInst2PI<dag outs, dag ins, string asmstr, list<dag> pattern,
378 : STInstPost<outs, ins, asmstr, pattern, cstr> {
383 // Post increment LD Instruction.
384 class LDInstPI<dag outs, dag ins, string asmstr, list<dag> pattern,
386 : LDInstPost<outs, ins, asmstr, pattern, cstr> {
390 class LDInst2PI<dag outs, dag ins, string asmstr, list<dag> pattern,
392 : LDInstPost<outs, ins, asmstr, pattern, cstr> {
397 //===----------------------------------------------------------------------===//
398 // V4 Instruction Format Definitions +
399 //===----------------------------------------------------------------------===//
401 include "HexagonInstrFormatsV4.td"
403 //===----------------------------------------------------------------------===//
404 // V4 Instruction Format Definitions +
405 //===----------------------------------------------------------------------===//