1 //===-- HexagonISelLowering.h - Hexagon DAG Lowering Interface --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Hexagon uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
16 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
19 #include "llvm/CodeGen/CallingConvLower.h"
20 #include "llvm/IR/CallingConv.h"
21 #include "llvm/Target/TargetLowering.h"
25 // Return true when the given node fits in a positive half word.
26 bool isPositiveHalfWord(SDNode *N);
28 namespace HexagonISD {
30 FIRST_NUMBER = ISD::BUILTIN_OP_END,
33 CONST32_GP, // For marking data present in GP.
40 CMPICC, // Compare two GPR operands, set icc.
41 CMPFCC, // Compare two FP operands, set fcc.
42 BRICC, // Branch to dest on icc condition
43 BRFCC, // Branch to dest on fcc condition
44 SELECT_ICC, // Select between two values using the current ICC flags.
45 SELECT_FCC, // Select between two values using the current FCC flags.
47 Hi, Lo, // Hi/Lo operations, typically on a global address.
49 FTOI, // FP to Int within a FP register.
50 ITOF, // Int to FP within a FP register.
52 CALL, // A call instruction.
53 RET_FLAG, // Return with a flag operand.
55 BARRIER, // Memory barrier.
76 class HexagonTargetLowering : public TargetLowering {
77 int VarArgsFrameOffset; // Frame offset to start of varargs area.
79 bool CanReturnSmallStruct(const Function* CalleeFn,
80 unsigned& RetSize) const;
83 const TargetMachine &TM;
84 explicit HexagonTargetLowering(const TargetMachine &targetmachine);
86 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
87 /// for tail call optimization. Targets which want to do tail call
88 /// optimization should implement this function.
90 IsEligibleForTailCallOptimization(SDValue Callee,
91 CallingConv::ID CalleeCC,
93 bool isCalleeStructRet,
94 bool isCallerStructRet,
96 SmallVectorImpl<ISD::OutputArg> &Outs,
97 const SmallVectorImpl<SDValue> &OutVals,
98 const SmallVectorImpl<ISD::InputArg> &Ins,
99 SelectionDAG& DAG) const;
101 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
102 bool isTruncateFree(EVT VT1, EVT VT2) const override;
104 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
106 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
108 const char *getTargetNodeName(unsigned Opcode) const override;
109 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
110 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
111 SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
112 SDValue LowerEH_LABEL(SDValue Op, SelectionDAG &DAG) const;
113 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
114 SDValue LowerFormalArguments(SDValue Chain,
115 CallingConv::ID CallConv, bool isVarArg,
116 const SmallVectorImpl<ISD::InputArg> &Ins,
117 SDLoc dl, SelectionDAG &DAG,
118 SmallVectorImpl<SDValue> &InVals) const override;
119 SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const;
120 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
122 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
123 SmallVectorImpl<SDValue> &InVals) const override;
125 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
126 CallingConv::ID CallConv, bool isVarArg,
127 const SmallVectorImpl<ISD::InputArg> &Ins,
128 SDLoc dl, SelectionDAG &DAG,
129 SmallVectorImpl<SDValue> &InVals,
130 const SmallVectorImpl<SDValue> &OutVals,
131 SDValue Callee) const;
133 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
134 SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
135 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
137 SDValue LowerReturn(SDValue Chain,
138 CallingConv::ID CallConv, bool isVarArg,
139 const SmallVectorImpl<ISD::OutputArg> &Outs,
140 const SmallVectorImpl<SDValue> &OutVals,
141 SDLoc dl, SelectionDAG &DAG) const override;
144 EmitInstrWithCustomInserter(MachineInstr *MI,
145 MachineBasicBlock *BB) const override;
147 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
148 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
149 EVT getSetCCResultType(LLVMContext &C, EVT VT) const override {
153 return EVT::getVectorVT(C, MVT::i1, VT.getVectorNumElements());
156 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
157 SDValue &Base, SDValue &Offset,
158 ISD::MemIndexedMode &AM,
159 SelectionDAG &DAG) const override;
161 std::pair<unsigned, const TargetRegisterClass*>
162 getRegForInlineAsmConstraint(const std::string &Constraint,
163 MVT VT) const override;
166 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
167 /// isLegalAddressingMode - Return true if the addressing mode represented
168 /// by AM is legal for this target, for a load/store of the specified type.
169 /// The type may be VoidTy, in which case only return true if the addressing
170 /// mode is legal for a load/store of any legal type.
171 /// TODO: Handle pre/postinc as well.
172 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
173 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
175 /// isLegalICmpImmediate - Return true if the specified immediate is legal
176 /// icmp immediate, that is the target has icmp instructions which can
177 /// compare a register against the immediate without having to materialize
178 /// the immediate into a register.
179 bool isLegalICmpImmediate(int64_t Imm) const override;
181 } // end namespace llvm
183 #endif // Hexagon_ISELLOWERING_H