1 //===-- HexagonISelLowering.h - Hexagon DAG Lowering Interface --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Hexagon uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
16 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
19 #include "llvm/CodeGen/CallingConvLower.h"
20 #include "llvm/IR/CallingConv.h"
21 #include "llvm/Target/TargetLowering.h"
25 // Return true when the given node fits in a positive half word.
26 bool isPositiveHalfWord(SDNode *N);
28 namespace HexagonISD {
30 FIRST_NUMBER = ISD::BUILTIN_OP_END,
33 CONST32_GP, // For marking data present in GP.
40 CMPICC, // Compare two GPR operands, set icc.
41 CMPFCC, // Compare two FP operands, set fcc.
42 BRICC, // Branch to dest on icc condition
43 BRFCC, // Branch to dest on fcc condition
44 SELECT_ICC, // Select between two values using the current ICC flags.
45 SELECT_FCC, // Select between two values using the current FCC flags.
47 Hi, Lo, // Hi/Lo operations, typically on a global address.
49 FTOI, // FP to Int within a FP register.
50 ITOF, // Int to FP within a FP register.
52 CALLv3, // A V3+ call instruction.
53 CALLv3nr, // A V3+ call instruction that doesn't return.
56 RET_FLAG, // Return with a flag operand.
58 BARRIER, // Memory barrier
80 class HexagonTargetLowering : public TargetLowering {
81 int VarArgsFrameOffset; // Frame offset to start of varargs area.
83 bool CanReturnSmallStruct(const Function* CalleeFn,
84 unsigned& RetSize) const;
87 const TargetMachine &TM;
88 explicit HexagonTargetLowering(const TargetMachine &targetmachine);
90 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
91 /// for tail call optimization. Targets which want to do tail call
92 /// optimization should implement this function.
94 IsEligibleForTailCallOptimization(SDValue Callee,
95 CallingConv::ID CalleeCC,
97 bool isCalleeStructRet,
98 bool isCallerStructRet,
100 SmallVectorImpl<ISD::OutputArg> &Outs,
101 const SmallVectorImpl<SDValue> &OutVals,
102 const SmallVectorImpl<ISD::InputArg> &Ins,
103 SelectionDAG& DAG) const;
105 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
106 bool isTruncateFree(EVT VT1, EVT VT2) const override;
108 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
110 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
112 const char *getTargetNodeName(unsigned Opcode) const override;
113 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
114 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
115 SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
116 SDValue LowerEH_LABEL(SDValue Op, SelectionDAG &DAG) const;
117 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
118 SDValue LowerFormalArguments(SDValue Chain,
119 CallingConv::ID CallConv, bool isVarArg,
120 const SmallVectorImpl<ISD::InputArg> &Ins,
121 SDLoc dl, SelectionDAG &DAG,
122 SmallVectorImpl<SDValue> &InVals) const override;
123 SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const;
124 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
126 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
127 SmallVectorImpl<SDValue> &InVals) const override;
129 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
130 CallingConv::ID CallConv, bool isVarArg,
131 const SmallVectorImpl<ISD::InputArg> &Ins,
132 SDLoc dl, SelectionDAG &DAG,
133 SmallVectorImpl<SDValue> &InVals,
134 const SmallVectorImpl<SDValue> &OutVals,
135 SDValue Callee) const;
137 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
138 SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
139 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
141 SDValue LowerReturn(SDValue Chain,
142 CallingConv::ID CallConv, bool isVarArg,
143 const SmallVectorImpl<ISD::OutputArg> &Outs,
144 const SmallVectorImpl<SDValue> &OutVals,
145 SDLoc dl, SelectionDAG &DAG) const override;
148 EmitInstrWithCustomInserter(MachineInstr *MI,
149 MachineBasicBlock *BB) const override;
151 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
152 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
153 EVT getSetCCResultType(LLVMContext &C, EVT VT) const override {
157 return EVT::getVectorVT(C, MVT::i1, VT.getVectorNumElements());
160 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
161 SDValue &Base, SDValue &Offset,
162 ISD::MemIndexedMode &AM,
163 SelectionDAG &DAG) const override;
165 std::pair<unsigned, const TargetRegisterClass*>
166 getRegForInlineAsmConstraint(const std::string &Constraint,
167 MVT VT) const override;
170 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
171 /// isLegalAddressingMode - Return true if the addressing mode represented
172 /// by AM is legal for this target, for a load/store of the specified type.
173 /// The type may be VoidTy, in which case only return true if the addressing
174 /// mode is legal for a load/store of any legal type.
175 /// TODO: Handle pre/postinc as well.
176 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
177 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
179 /// isLegalICmpImmediate - Return true if the specified immediate is legal
180 /// icmp immediate, that is the target has icmp instructions which can
181 /// compare a register against the immediate without having to materialize
182 /// the immediate into a register.
183 bool isLegalICmpImmediate(int64_t Imm) const override;
185 } // end namespace llvm
187 #endif // Hexagon_ISELLOWERING_H