1 //===-- HexagonISelLowering.cpp - Hexagon DAG Lowering Implementation -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the interfaces that Hexagon uses to lower LLVM code
11 // into a selection DAG.
13 //===----------------------------------------------------------------------===//
15 #include "HexagonISelLowering.h"
16 #include "HexagonMachineFunctionInfo.h"
17 #include "HexagonSubtarget.h"
18 #include "HexagonTargetMachine.h"
19 #include "HexagonTargetObjectFile.h"
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineJumpTableInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAGISel.h"
27 #include "llvm/CodeGen/ValueTypes.h"
28 #include "llvm/IR/CallingConv.h"
29 #include "llvm/IR/DerivedTypes.h"
30 #include "llvm/IR/Function.h"
31 #include "llvm/IR/GlobalAlias.h"
32 #include "llvm/IR/GlobalVariable.h"
33 #include "llvm/IR/InlineAsm.h"
34 #include "llvm/IR/Intrinsics.h"
35 #include "llvm/IR/LLVMContext.h"
36 #include "llvm/Support/CommandLine.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/raw_ostream.h"
44 EmitJumpTables("hexagon-emit-jump-tables", cl::init(true), cl::Hidden,
45 cl::desc("Control jump table emission on Hexagon target"));
48 class HexagonCCState : public CCState {
49 int NumNamedVarArgParams;
52 HexagonCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,
53 const TargetMachine &TM, SmallVectorImpl<CCValAssign> &locs,
54 LLVMContext &C, int NumNamedVarArgParams)
55 : CCState(CC, isVarArg, MF, TM, locs, C),
56 NumNamedVarArgParams(NumNamedVarArgParams) {}
58 int getNumNamedVarArgParams() const { return NumNamedVarArgParams; }
62 // Implement calling convention for Hexagon.
64 CC_Hexagon(unsigned ValNo, MVT ValVT,
65 MVT LocVT, CCValAssign::LocInfo LocInfo,
66 ISD::ArgFlagsTy ArgFlags, CCState &State);
69 CC_Hexagon32(unsigned ValNo, MVT ValVT,
70 MVT LocVT, CCValAssign::LocInfo LocInfo,
71 ISD::ArgFlagsTy ArgFlags, CCState &State);
74 CC_Hexagon64(unsigned ValNo, MVT ValVT,
75 MVT LocVT, CCValAssign::LocInfo LocInfo,
76 ISD::ArgFlagsTy ArgFlags, CCState &State);
79 RetCC_Hexagon(unsigned ValNo, MVT ValVT,
80 MVT LocVT, CCValAssign::LocInfo LocInfo,
81 ISD::ArgFlagsTy ArgFlags, CCState &State);
84 RetCC_Hexagon32(unsigned ValNo, MVT ValVT,
85 MVT LocVT, CCValAssign::LocInfo LocInfo,
86 ISD::ArgFlagsTy ArgFlags, CCState &State);
89 RetCC_Hexagon64(unsigned ValNo, MVT ValVT,
90 MVT LocVT, CCValAssign::LocInfo LocInfo,
91 ISD::ArgFlagsTy ArgFlags, CCState &State);
94 CC_Hexagon_VarArg (unsigned ValNo, MVT ValVT,
95 MVT LocVT, CCValAssign::LocInfo LocInfo,
96 ISD::ArgFlagsTy ArgFlags, CCState &State) {
97 HexagonCCState &HState = static_cast<HexagonCCState &>(State);
99 // NumNamedVarArgParams can not be zero for a VarArg function.
100 assert((HState.getNumNamedVarArgParams() > 0) &&
101 "NumNamedVarArgParams is not bigger than zero.");
103 if ((int)ValNo < HState.getNumNamedVarArgParams()) {
104 // Deal with named arguments.
105 return CC_Hexagon(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State);
108 // Deal with un-named arguments.
110 if (ArgFlags.isByVal()) {
111 // If pass-by-value, the size allocated on stack is decided
112 // by ArgFlags.getByValSize(), not by the size of LocVT.
113 assert ((ArgFlags.getByValSize() > 8) &&
114 "ByValSize must be bigger than 8 bytes");
115 ofst = State.AllocateStack(ArgFlags.getByValSize(), 4);
116 State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo));
119 if (LocVT == MVT::i1 || LocVT == MVT::i8 || LocVT == MVT::i16) {
122 if (ArgFlags.isSExt())
123 LocInfo = CCValAssign::SExt;
124 else if (ArgFlags.isZExt())
125 LocInfo = CCValAssign::ZExt;
127 LocInfo = CCValAssign::AExt;
129 if (LocVT == MVT::i32 || LocVT == MVT::f32) {
130 ofst = State.AllocateStack(4, 4);
131 State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo));
134 if (LocVT == MVT::i64 || LocVT == MVT::f64) {
135 ofst = State.AllocateStack(8, 8);
136 State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo));
144 CC_Hexagon (unsigned ValNo, MVT ValVT,
145 MVT LocVT, CCValAssign::LocInfo LocInfo,
146 ISD::ArgFlagsTy ArgFlags, CCState &State) {
148 if (ArgFlags.isByVal()) {
150 assert ((ArgFlags.getByValSize() > 8) &&
151 "ByValSize must be bigger than 8 bytes");
152 unsigned Offset = State.AllocateStack(ArgFlags.getByValSize(), 4);
153 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
157 if (LocVT == MVT::i1 || LocVT == MVT::i8 || LocVT == MVT::i16) {
160 if (ArgFlags.isSExt())
161 LocInfo = CCValAssign::SExt;
162 else if (ArgFlags.isZExt())
163 LocInfo = CCValAssign::ZExt;
165 LocInfo = CCValAssign::AExt;
168 if (LocVT == MVT::i32 || LocVT == MVT::f32) {
169 if (!CC_Hexagon32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
173 if (LocVT == MVT::i64 || LocVT == MVT::f64) {
174 if (!CC_Hexagon64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
178 return true; // CC didn't match.
182 static bool CC_Hexagon32(unsigned ValNo, MVT ValVT,
183 MVT LocVT, CCValAssign::LocInfo LocInfo,
184 ISD::ArgFlagsTy ArgFlags, CCState &State) {
186 static const uint16_t RegList[] = {
187 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
190 if (unsigned Reg = State.AllocateReg(RegList, 6)) {
191 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
195 unsigned Offset = State.AllocateStack(4, 4);
196 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
200 static bool CC_Hexagon64(unsigned ValNo, MVT ValVT,
201 MVT LocVT, CCValAssign::LocInfo LocInfo,
202 ISD::ArgFlagsTy ArgFlags, CCState &State) {
204 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) {
205 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
209 static const uint16_t RegList1[] = {
210 Hexagon::D1, Hexagon::D2
212 static const uint16_t RegList2[] = {
213 Hexagon::R1, Hexagon::R3
215 if (unsigned Reg = State.AllocateReg(RegList1, RegList2, 2)) {
216 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
220 unsigned Offset = State.AllocateStack(8, 8, Hexagon::D2);
221 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
225 static bool RetCC_Hexagon(unsigned ValNo, MVT ValVT,
226 MVT LocVT, CCValAssign::LocInfo LocInfo,
227 ISD::ArgFlagsTy ArgFlags, CCState &State) {
230 if (LocVT == MVT::i1 ||
235 if (ArgFlags.isSExt())
236 LocInfo = CCValAssign::SExt;
237 else if (ArgFlags.isZExt())
238 LocInfo = CCValAssign::ZExt;
240 LocInfo = CCValAssign::AExt;
243 if (LocVT == MVT::i32 || LocVT == MVT::f32) {
244 if (!RetCC_Hexagon32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
248 if (LocVT == MVT::i64 || LocVT == MVT::f64) {
249 if (!RetCC_Hexagon64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
253 return true; // CC didn't match.
256 static bool RetCC_Hexagon32(unsigned ValNo, MVT ValVT,
257 MVT LocVT, CCValAssign::LocInfo LocInfo,
258 ISD::ArgFlagsTy ArgFlags, CCState &State) {
260 if (LocVT == MVT::i32 || LocVT == MVT::f32) {
261 if (unsigned Reg = State.AllocateReg(Hexagon::R0)) {
262 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
267 unsigned Offset = State.AllocateStack(4, 4);
268 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
272 static bool RetCC_Hexagon64(unsigned ValNo, MVT ValVT,
273 MVT LocVT, CCValAssign::LocInfo LocInfo,
274 ISD::ArgFlagsTy ArgFlags, CCState &State) {
275 if (LocVT == MVT::i64 || LocVT == MVT::f64) {
276 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) {
277 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
282 unsigned Offset = State.AllocateStack(8, 8);
283 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
288 HexagonTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG)
293 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
294 /// by "Src" to address "Dst" of size "Size". Alignment information is
295 /// specified by the specific parameter attribute. The copy will be passed as
296 /// a byval function parameter. Sometimes what we are copying is the end of a
297 /// larger object, the part that does not fit in registers.
299 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
300 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
303 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
304 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
305 /*isVolatile=*/false, /*AlwaysInline=*/false,
306 MachinePointerInfo(), MachinePointerInfo());
310 // LowerReturn - Lower ISD::RET. If a struct is larger than 8 bytes and is
311 // passed by value, the function prototype is modified to return void and
312 // the value is stored in memory pointed by a pointer passed by caller.
314 HexagonTargetLowering::LowerReturn(SDValue Chain,
315 CallingConv::ID CallConv, bool isVarArg,
316 const SmallVectorImpl<ISD::OutputArg> &Outs,
317 const SmallVectorImpl<SDValue> &OutVals,
318 SDLoc dl, SelectionDAG &DAG) const {
320 // CCValAssign - represent the assignment of the return value to locations.
321 SmallVector<CCValAssign, 16> RVLocs;
323 // CCState - Info about the registers and stack slot.
324 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
325 getTargetMachine(), RVLocs, *DAG.getContext());
327 // Analyze return values of ISD::RET
328 CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon);
331 SmallVector<SDValue, 4> RetOps(1, Chain);
333 // Copy the result values into the output registers.
334 for (unsigned i = 0; i != RVLocs.size(); ++i) {
335 CCValAssign &VA = RVLocs[i];
337 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
339 // Guarantee that all emitted copies are stuck together with flags.
340 Flag = Chain.getValue(1);
341 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
344 RetOps[0] = Chain; // Update chain.
346 // Add the flag if we have it.
348 RetOps.push_back(Flag);
350 return DAG.getNode(HexagonISD::RET_FLAG, dl, MVT::Other,
351 &RetOps[0], RetOps.size());
357 /// LowerCallResult - Lower the result values of an ISD::CALL into the
358 /// appropriate copies out of appropriate physical registers. This assumes that
359 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
360 /// being lowered. Returns a SDNode with the same number of values as the
363 HexagonTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
364 CallingConv::ID CallConv, bool isVarArg,
366 SmallVectorImpl<ISD::InputArg> &Ins,
367 SDLoc dl, SelectionDAG &DAG,
368 SmallVectorImpl<SDValue> &InVals,
369 const SmallVectorImpl<SDValue> &OutVals,
370 SDValue Callee) const {
372 // Assign locations to each value returned by this call.
373 SmallVector<CCValAssign, 16> RVLocs;
375 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
376 getTargetMachine(), RVLocs, *DAG.getContext());
378 CCInfo.AnalyzeCallResult(Ins, RetCC_Hexagon);
380 // Copy all of the result registers out of their specified physreg.
381 for (unsigned i = 0; i != RVLocs.size(); ++i) {
382 Chain = DAG.getCopyFromReg(Chain, dl,
383 RVLocs[i].getLocReg(),
384 RVLocs[i].getValVT(), InFlag).getValue(1);
385 InFlag = Chain.getValue(2);
386 InVals.push_back(Chain.getValue(0));
392 /// LowerCall - Functions arguments are copied from virtual regs to
393 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
395 HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
396 SmallVectorImpl<SDValue> &InVals) const {
397 SelectionDAG &DAG = CLI.DAG;
399 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
400 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
401 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
402 SDValue Chain = CLI.Chain;
403 SDValue Callee = CLI.Callee;
404 bool &isTailCall = CLI.IsTailCall;
405 CallingConv::ID CallConv = CLI.CallConv;
406 bool isVarArg = CLI.IsVarArg;
408 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
410 // Check for varargs.
411 int NumNamedVarArgParams = -1;
412 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Callee))
414 const Function* CalleeFn = NULL;
415 Callee = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, MVT::i32);
416 if ((CalleeFn = dyn_cast<Function>(GA->getGlobal())))
418 // If a function has zero args and is a vararg function, that's
419 // disallowed so it must be an undeclared function. Do not assume
420 // varargs if the callee is undefined.
421 if (CalleeFn->isVarArg() &&
422 CalleeFn->getFunctionType()->getNumParams() != 0) {
423 NumNamedVarArgParams = CalleeFn->getFunctionType()->getNumParams();
428 // Analyze operands of the call, assigning locations to each operand.
429 SmallVector<CCValAssign, 16> ArgLocs;
430 HexagonCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
431 getTargetMachine(), ArgLocs, *DAG.getContext(),
432 NumNamedVarArgParams);
434 if (NumNamedVarArgParams > 0)
435 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon_VarArg);
437 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon);
441 bool StructAttrFlag =
442 DAG.getMachineFunction().getFunction()->hasStructRetAttr();
443 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
444 isVarArg, IsStructRet,
446 Outs, OutVals, Ins, DAG);
447 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i){
448 CCValAssign &VA = ArgLocs[i];
455 DEBUG(dbgs () << "Eligible for Tail Call\n");
458 "Argument must be passed on stack. Not eligible for Tail Call\n");
461 // Get a count of how many bytes are to be pushed on the stack.
462 unsigned NumBytes = CCInfo.getNextStackOffset();
463 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
464 SmallVector<SDValue, 8> MemOpChains;
467 DAG.getCopyFromReg(Chain, dl, TM.getRegisterInfo()->getStackRegister(),
470 // Walk the register/memloc assignments, inserting copies/loads.
471 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
472 CCValAssign &VA = ArgLocs[i];
473 SDValue Arg = OutVals[i];
474 ISD::ArgFlagsTy Flags = Outs[i].Flags;
476 // Promote the value if needed.
477 switch (VA.getLocInfo()) {
479 // Loc info must be one of Full, SExt, ZExt, or AExt.
480 llvm_unreachable("Unknown loc info!");
481 case CCValAssign::Full:
483 case CCValAssign::SExt:
484 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
486 case CCValAssign::ZExt:
487 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
489 case CCValAssign::AExt:
490 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
495 unsigned LocMemOffset = VA.getLocMemOffset();
496 SDValue PtrOff = DAG.getConstant(LocMemOffset, StackPtr.getValueType());
497 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
499 if (Flags.isByVal()) {
500 // The argument is a struct passed by value. According to LLVM, "Arg"
502 MemOpChains.push_back(CreateCopyOfByValArgument(Arg, PtrOff, Chain,
505 // The argument is not passed by value. "Arg" is a buildin type. It is
507 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
508 MachinePointerInfo(),false, false,
514 // Arguments that can be passed on register must be kept at RegsToPass
517 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
521 // Transform all store nodes into one single node because all store
522 // nodes are independent of each other.
523 if (!MemOpChains.empty()) {
524 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOpChains[0],
529 Chain = DAG.getCALLSEQ_START(Chain, DAG.getConstant(NumBytes,
530 getPointerTy(), true),
533 // Build a sequence of copy-to-reg nodes chained together with token
534 // chain and flag operands which copy the outgoing args into registers.
535 // The InFlag in necessary since all emitted instructions must be
539 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
540 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
541 RegsToPass[i].second, InFlag);
542 InFlag = Chain.getValue(1);
546 // For tail calls lower the arguments to the 'real' stack slot.
548 // Force all the incoming stack arguments to be loaded from the stack
549 // before any new outgoing arguments are stored to the stack, because the
550 // outgoing stack slots may alias the incoming argument stack slots, and
551 // the alias isn't otherwise explicit. This is slightly more conservative
552 // than necessary, because it means that each store effectively depends
553 // on every argument instead of just those arguments it would clobber.
555 // Do not flag preceding copytoreg stuff together with the following stuff.
557 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
558 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
559 RegsToPass[i].second, InFlag);
560 InFlag = Chain.getValue(1);
565 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
566 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
567 // node so that legalize doesn't hack it.
568 if (flag_aligned_memcpy) {
569 const char *MemcpyName =
570 "__hexagon_memcpy_likely_aligned_min32bytes_mult8bytes";
572 DAG.getTargetExternalSymbol(MemcpyName, getPointerTy());
573 flag_aligned_memcpy = false;
574 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
575 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy());
576 } else if (ExternalSymbolSDNode *S =
577 dyn_cast<ExternalSymbolSDNode>(Callee)) {
578 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
581 // Returns a chain & a flag for retval copy to use.
582 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
583 SmallVector<SDValue, 8> Ops;
584 Ops.push_back(Chain);
585 Ops.push_back(Callee);
587 // Add argument registers to the end of the list so that they are
588 // known live into the call.
589 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
590 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
591 RegsToPass[i].second.getValueType()));
594 if (InFlag.getNode()) {
595 Ops.push_back(InFlag);
599 return DAG.getNode(HexagonISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
601 Chain = DAG.getNode(HexagonISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
602 InFlag = Chain.getValue(1);
604 // Create the CALLSEQ_END node.
605 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
606 DAG.getIntPtrConstant(0, true), InFlag, dl);
607 InFlag = Chain.getValue(1);
609 // Handle result values, copying them out of physregs into vregs that we
611 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
612 InVals, OutVals, Callee);
615 static bool getIndexedAddressParts(SDNode *Ptr, EVT VT,
616 bool isSEXTLoad, SDValue &Base,
617 SDValue &Offset, bool &isInc,
619 if (Ptr->getOpcode() != ISD::ADD)
622 if (VT == MVT::i64 || VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
623 isInc = (Ptr->getOpcode() == ISD::ADD);
624 Base = Ptr->getOperand(0);
625 Offset = Ptr->getOperand(1);
626 // Ensure that Offset is a constant.
627 return (isa<ConstantSDNode>(Offset));
633 // TODO: Put this function along with the other isS* functions in
634 // HexagonISelDAGToDAG.cpp into a common file. Or better still, use the
635 // functions defined in HexagonOperands.td.
636 static bool Is_PostInc_S4_Offset(SDNode * S, int ShiftAmount) {
637 ConstantSDNode *N = cast<ConstantSDNode>(S);
639 // immS4 predicate - True if the immediate fits in a 4-bit sign extended.
641 int64_t v = (int64_t)N->getSExtValue();
643 if (ShiftAmount > 0) {
645 v = v >> ShiftAmount;
647 return (v <= 7) && (v >= -8) && (m == 0);
650 /// getPostIndexedAddressParts - returns true by value, base pointer and
651 /// offset pointer and addressing mode by reference if this node can be
652 /// combined with a load / store to form a post-indexed load / store.
653 bool HexagonTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
656 ISD::MemIndexedMode &AM,
657 SelectionDAG &DAG) const
661 bool isSEXTLoad = false;
663 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
664 VT = LD->getMemoryVT();
665 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
666 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
667 VT = ST->getMemoryVT();
668 if (ST->getValue().getValueType() == MVT::i64 && ST->isTruncatingStore()) {
676 bool isLegal = getIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
678 // ShiftAmount = number of left-shifted bits in the Hexagon instruction.
679 int ShiftAmount = VT.getSizeInBits() / 16;
680 if (isLegal && Is_PostInc_S4_Offset(Offset.getNode(), ShiftAmount)) {
681 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
688 SDValue HexagonTargetLowering::LowerINLINEASM(SDValue Op,
689 SelectionDAG &DAG) const {
690 SDNode *Node = Op.getNode();
691 MachineFunction &MF = DAG.getMachineFunction();
692 HexagonMachineFunctionInfo *FuncInfo =
693 MF.getInfo<HexagonMachineFunctionInfo>();
694 switch (Node->getOpcode()) {
695 case ISD::INLINEASM: {
696 unsigned NumOps = Node->getNumOperands();
697 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
698 --NumOps; // Ignore the flag operand.
700 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
701 if (FuncInfo->hasClobberLR())
704 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
705 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
706 ++i; // Skip the ID value.
708 switch (InlineAsm::getKind(Flags)) {
709 default: llvm_unreachable("Bad flags!");
710 case InlineAsm::Kind_RegDef:
711 case InlineAsm::Kind_RegUse:
712 case InlineAsm::Kind_Imm:
713 case InlineAsm::Kind_Clobber:
714 case InlineAsm::Kind_Mem: {
715 for (; NumVals; --NumVals, ++i) {}
718 case InlineAsm::Kind_RegDefEarlyClobber: {
719 for (; NumVals; --NumVals, ++i) {
721 cast<RegisterSDNode>(Node->getOperand(i))->getReg();
724 if (Reg == TM.getRegisterInfo()->getRARegister()) {
725 FuncInfo->setHasClobberLR(true);
740 // Taken from the XCore backend.
742 SDValue HexagonTargetLowering::
743 LowerBR_JT(SDValue Op, SelectionDAG &DAG) const
745 SDValue Chain = Op.getOperand(0);
746 SDValue Table = Op.getOperand(1);
747 SDValue Index = Op.getOperand(2);
749 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
750 unsigned JTI = JT->getIndex();
751 MachineFunction &MF = DAG.getMachineFunction();
752 const MachineJumpTableInfo *MJTI = MF.getJumpTableInfo();
753 SDValue TargetJT = DAG.getTargetJumpTable(JT->getIndex(), MVT::i32);
755 // Mark all jump table targets as address taken.
756 const std::vector<MachineJumpTableEntry> &JTE = MJTI->getJumpTables();
757 const std::vector<MachineBasicBlock*> &JTBBs = JTE[JTI].MBBs;
758 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
759 MachineBasicBlock *MBB = JTBBs[i];
760 MBB->setHasAddressTaken();
761 // This line is needed to set the hasAddressTaken flag on the BasicBlock
763 BlockAddress::get(const_cast<BasicBlock *>(MBB->getBasicBlock()));
766 SDValue JumpTableBase = DAG.getNode(HexagonISD::WrapperJT, dl,
767 getPointerTy(), TargetJT);
768 SDValue ShiftIndex = DAG.getNode(ISD::SHL, dl, MVT::i32, Index,
769 DAG.getConstant(2, MVT::i32));
770 SDValue JTAddress = DAG.getNode(ISD::ADD, dl, MVT::i32, JumpTableBase,
772 SDValue LoadTarget = DAG.getLoad(MVT::i32, dl, Chain, JTAddress,
773 MachinePointerInfo(), false, false, false,
775 return DAG.getNode(HexagonISD::BR_JT, dl, MVT::Other, Chain, LoadTarget);
780 HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
781 SelectionDAG &DAG) const {
782 SDValue Chain = Op.getOperand(0);
783 SDValue Size = Op.getOperand(1);
786 unsigned SPReg = getStackPointerRegisterToSaveRestore();
788 // Get a reference to the stack pointer.
789 SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, SPReg, MVT::i32);
791 // Subtract the dynamic size from the actual stack size to
792 // obtain the new stack size.
793 SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, StackPointer, Size);
796 // For Hexagon, the outgoing memory arguments area should be on top of the
797 // alloca area on the stack i.e., the outgoing memory arguments should be
798 // at a lower address than the alloca area. Move the alloca area down the
799 // stack by adding back the space reserved for outgoing arguments to SP
802 // We do not know what the size of the outgoing args is at this point.
803 // So, we add a pseudo instruction ADJDYNALLOC that will adjust the
804 // stack pointer. We patch this instruction with the correct, known
805 // offset in emitPrologue().
807 // Use a placeholder immediate (zero) for now. This will be patched up
808 // by emitPrologue().
809 SDValue ArgAdjust = DAG.getNode(HexagonISD::ADJDYNALLOC, dl,
812 DAG.getConstant(0, MVT::i32));
814 // The Sub result contains the new stack start address, so it
815 // must be placed in the stack pointer register.
816 SDValue CopyChain = DAG.getCopyToReg(Chain, dl,
817 TM.getRegisterInfo()->getStackRegister(),
820 SDValue Ops[2] = { ArgAdjust, CopyChain };
821 return DAG.getMergeValues(Ops, 2, dl);
825 HexagonTargetLowering::LowerFormalArguments(SDValue Chain,
826 CallingConv::ID CallConv,
829 SmallVectorImpl<ISD::InputArg> &Ins,
830 SDLoc dl, SelectionDAG &DAG,
831 SmallVectorImpl<SDValue> &InVals)
834 MachineFunction &MF = DAG.getMachineFunction();
835 MachineFrameInfo *MFI = MF.getFrameInfo();
836 MachineRegisterInfo &RegInfo = MF.getRegInfo();
837 HexagonMachineFunctionInfo *FuncInfo =
838 MF.getInfo<HexagonMachineFunctionInfo>();
841 // Assign locations to all of the incoming arguments.
842 SmallVector<CCValAssign, 16> ArgLocs;
843 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
844 getTargetMachine(), ArgLocs, *DAG.getContext());
846 CCInfo.AnalyzeFormalArguments(Ins, CC_Hexagon);
848 // For LLVM, in the case when returning a struct by value (>8byte),
849 // the first argument is a pointer that points to the location on caller's
850 // stack where the return value will be stored. For Hexagon, the location on
851 // caller's stack is passed only when the struct size is smaller than (and
852 // equal to) 8 bytes. If not, no address will be passed into callee and
853 // callee return the result direclty through R0/R1.
855 SmallVector<SDValue, 4> MemOps;
857 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
858 CCValAssign &VA = ArgLocs[i];
859 ISD::ArgFlagsTy Flags = Ins[i].Flags;
861 unsigned StackLocation;
864 if ( (VA.isRegLoc() && !Flags.isByVal())
865 || (VA.isRegLoc() && Flags.isByVal() && Flags.getByValSize() > 8)) {
866 // Arguments passed in registers
867 // 1. int, long long, ptr args that get allocated in register.
868 // 2. Large struct that gets an register to put its address in.
869 EVT RegVT = VA.getLocVT();
870 if (RegVT == MVT::i8 || RegVT == MVT::i16 ||
871 RegVT == MVT::i32 || RegVT == MVT::f32) {
873 RegInfo.createVirtualRegister(&Hexagon::IntRegsRegClass);
874 RegInfo.addLiveIn(VA.getLocReg(), VReg);
875 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
876 } else if (RegVT == MVT::i64) {
878 RegInfo.createVirtualRegister(&Hexagon::DoubleRegsRegClass);
879 RegInfo.addLiveIn(VA.getLocReg(), VReg);
880 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
884 } else if (VA.isRegLoc() && Flags.isByVal() && Flags.getByValSize() <= 8) {
885 assert (0 && "ByValSize must be bigger than 8 bytes");
888 assert(VA.isMemLoc());
890 if (Flags.isByVal()) {
891 // If it's a byval parameter, then we need to compute the
892 // "real" size, not the size of the pointer.
893 ObjSize = Flags.getByValSize();
895 ObjSize = VA.getLocVT().getStoreSizeInBits() >> 3;
898 StackLocation = HEXAGON_LRFP_SIZE + VA.getLocMemOffset();
899 // Create the frame index object for this incoming parameter...
900 FI = MFI->CreateFixedObject(ObjSize, StackLocation, true);
902 // Create the SelectionDAG nodes cordl, responding to a load
903 // from this parameter.
904 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
906 if (Flags.isByVal()) {
907 // If it's a pass-by-value aggregate, then do not dereference the stack
908 // location. Instead, we should generate a reference to the stack
910 InVals.push_back(FIN);
912 InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
913 MachinePointerInfo(), false, false,
920 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOps[0],
924 // This will point to the next argument passed via stack.
925 int FrameIndex = MFI->CreateFixedObject(Hexagon_PointerSize,
927 CCInfo.getNextStackOffset(),
929 FuncInfo->setVarArgsFrameIndex(FrameIndex);
936 HexagonTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
937 // VASTART stores the address of the VarArgsFrameIndex slot into the
938 // memory location argument.
939 MachineFunction &MF = DAG.getMachineFunction();
940 HexagonMachineFunctionInfo *QFI = MF.getInfo<HexagonMachineFunctionInfo>();
941 SDValue Addr = DAG.getFrameIndex(QFI->getVarArgsFrameIndex(), MVT::i32);
942 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
943 return DAG.getStore(Op.getOperand(0), SDLoc(Op), Addr,
944 Op.getOperand(1), MachinePointerInfo(SV), false,
949 HexagonTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
950 SDValue LHS = Op.getOperand(0);
951 SDValue RHS = Op.getOperand(1);
952 SDValue CC = Op.getOperand(4);
953 SDValue TrueVal = Op.getOperand(2);
954 SDValue FalseVal = Op.getOperand(3);
956 SDNode* OpNode = Op.getNode();
957 EVT SVT = OpNode->getValueType(0);
959 SDValue Cond = DAG.getNode(ISD::SETCC, dl, MVT::i1, LHS, RHS, CC);
960 return DAG.getNode(ISD::SELECT, dl, SVT, Cond, TrueVal, FalseVal);
964 HexagonTargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
965 EVT ValTy = Op.getValueType();
967 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
969 if (CP->isMachineConstantPoolEntry())
970 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), ValTy,
973 Res = DAG.getTargetConstantPool(CP->getConstVal(), ValTy,
975 return DAG.getNode(HexagonISD::CONST32, dl, ValTy, Res);
979 HexagonTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const {
980 const TargetRegisterInfo *TRI = TM.getRegisterInfo();
981 MachineFunction &MF = DAG.getMachineFunction();
982 MachineFrameInfo *MFI = MF.getFrameInfo();
983 MFI->setReturnAddressIsTaken(true);
985 if (!isa<ConstantSDNode>(Op.getOperand(0))) {
986 DAG.getContext()->emitError("argument to '__builtin_return_address' must "
987 "be a constant integer");
991 EVT VT = Op.getValueType();
993 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
995 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
996 SDValue Offset = DAG.getConstant(4, MVT::i32);
997 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
998 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
999 MachinePointerInfo(), false, false, false, 0);
1002 // Return LR, which contains the return address. Mark it an implicit live-in.
1003 unsigned Reg = MF.addLiveIn(TRI->getRARegister(), getRegClassFor(MVT::i32));
1004 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
1008 HexagonTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
1009 const HexagonRegisterInfo *TRI = TM.getRegisterInfo();
1010 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1011 MFI->setFrameAddressIsTaken(true);
1013 EVT VT = Op.getValueType();
1015 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1016 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
1017 TRI->getFrameRegister(), VT);
1019 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
1020 MachinePointerInfo(),
1021 false, false, false, 0);
1025 SDValue HexagonTargetLowering::LowerATOMIC_FENCE(SDValue Op,
1026 SelectionDAG& DAG) const {
1028 return DAG.getNode(HexagonISD::BARRIER, dl, MVT::Other, Op.getOperand(0));
1032 SDValue HexagonTargetLowering::LowerGLOBALADDRESS(SDValue Op,
1033 SelectionDAG &DAG) const {
1035 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1036 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
1038 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
1040 const HexagonTargetObjectFile &TLOF =
1041 static_cast<const HexagonTargetObjectFile &>(getObjFileLowering());
1042 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) {
1043 return DAG.getNode(HexagonISD::CONST32_GP, dl, getPointerTy(), Result);
1046 return DAG.getNode(HexagonISD::CONST32, dl, getPointerTy(), Result);
1050 HexagonTargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
1051 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1052 SDValue BA_SD = DAG.getTargetBlockAddress(BA, MVT::i32);
1054 return DAG.getNode(HexagonISD::CONST32_GP, dl, getPointerTy(), BA_SD);
1057 //===----------------------------------------------------------------------===//
1058 // TargetLowering Implementation
1059 //===----------------------------------------------------------------------===//
1061 HexagonTargetLowering::HexagonTargetLowering(HexagonTargetMachine
1063 : TargetLowering(targetmachine, new HexagonTargetObjectFile()),
1066 const HexagonRegisterInfo* QRI = TM.getRegisterInfo();
1068 // Set up the register classes.
1069 addRegisterClass(MVT::i32, &Hexagon::IntRegsRegClass);
1070 addRegisterClass(MVT::i64, &Hexagon::DoubleRegsRegClass);
1072 if (QRI->Subtarget.hasV5TOps()) {
1073 addRegisterClass(MVT::f32, &Hexagon::IntRegsRegClass);
1074 addRegisterClass(MVT::f64, &Hexagon::DoubleRegsRegClass);
1077 addRegisterClass(MVT::i1, &Hexagon::PredRegsRegClass);
1079 computeRegisterProperties();
1082 setPrefLoopAlignment(4);
1084 // Limits for inline expansion of memcpy/memmove
1085 MaxStoresPerMemcpy = 6;
1086 MaxStoresPerMemmove = 6;
1089 // Library calls for unsupported operations
1092 setLibcallName(RTLIB::SINTTOFP_I128_F64, "__hexagon_floattidf");
1093 setLibcallName(RTLIB::SINTTOFP_I128_F32, "__hexagon_floattisf");
1095 setLibcallName(RTLIB::FPTOUINT_F32_I128, "__hexagon_fixunssfti");
1096 setLibcallName(RTLIB::FPTOUINT_F64_I128, "__hexagon_fixunsdfti");
1098 setLibcallName(RTLIB::FPTOSINT_F32_I128, "__hexagon_fixsfti");
1099 setLibcallName(RTLIB::FPTOSINT_F64_I128, "__hexagon_fixdfti");
1101 setLibcallName(RTLIB::SDIV_I32, "__hexagon_divsi3");
1102 setOperationAction(ISD::SDIV, MVT::i32, Expand);
1103 setLibcallName(RTLIB::SREM_I32, "__hexagon_umodsi3");
1104 setOperationAction(ISD::SREM, MVT::i32, Expand);
1106 setLibcallName(RTLIB::SDIV_I64, "__hexagon_divdi3");
1107 setOperationAction(ISD::SDIV, MVT::i64, Expand);
1108 setLibcallName(RTLIB::SREM_I64, "__hexagon_moddi3");
1109 setOperationAction(ISD::SREM, MVT::i64, Expand);
1111 setLibcallName(RTLIB::UDIV_I32, "__hexagon_udivsi3");
1112 setOperationAction(ISD::UDIV, MVT::i32, Expand);
1114 setLibcallName(RTLIB::UDIV_I64, "__hexagon_udivdi3");
1115 setOperationAction(ISD::UDIV, MVT::i64, Expand);
1117 setLibcallName(RTLIB::UREM_I32, "__hexagon_umodsi3");
1118 setOperationAction(ISD::UREM, MVT::i32, Expand);
1120 setLibcallName(RTLIB::UREM_I64, "__hexagon_umoddi3");
1121 setOperationAction(ISD::UREM, MVT::i64, Expand);
1123 setLibcallName(RTLIB::DIV_F32, "__hexagon_divsf3");
1124 setOperationAction(ISD::FDIV, MVT::f32, Expand);
1126 setLibcallName(RTLIB::DIV_F64, "__hexagon_divdf3");
1127 setOperationAction(ISD::FDIV, MVT::f64, Expand);
1129 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
1130 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
1131 setOperationAction(ISD::FSIN, MVT::f32, Expand);
1132 setOperationAction(ISD::FSIN, MVT::f64, Expand);
1134 if (QRI->Subtarget.hasV5TOps()) {
1135 // Hexagon V5 Support.
1136 setOperationAction(ISD::FADD, MVT::f32, Legal);
1137 setOperationAction(ISD::FADD, MVT::f64, Legal);
1138 setOperationAction(ISD::FP_EXTEND, MVT::f32, Legal);
1139 setCondCodeAction(ISD::SETOEQ, MVT::f32, Legal);
1140 setCondCodeAction(ISD::SETOEQ, MVT::f64, Legal);
1141 setCondCodeAction(ISD::SETUEQ, MVT::f32, Legal);
1142 setCondCodeAction(ISD::SETUEQ, MVT::f64, Legal);
1144 setCondCodeAction(ISD::SETOGE, MVT::f32, Legal);
1145 setCondCodeAction(ISD::SETOGE, MVT::f64, Legal);
1146 setCondCodeAction(ISD::SETUGE, MVT::f32, Legal);
1147 setCondCodeAction(ISD::SETUGE, MVT::f64, Legal);
1149 setCondCodeAction(ISD::SETOGT, MVT::f32, Legal);
1150 setCondCodeAction(ISD::SETOGT, MVT::f64, Legal);
1151 setCondCodeAction(ISD::SETUGT, MVT::f32, Legal);
1152 setCondCodeAction(ISD::SETUGT, MVT::f64, Legal);
1154 setCondCodeAction(ISD::SETOLE, MVT::f32, Legal);
1155 setCondCodeAction(ISD::SETOLE, MVT::f64, Legal);
1156 setCondCodeAction(ISD::SETOLT, MVT::f32, Legal);
1157 setCondCodeAction(ISD::SETOLT, MVT::f64, Legal);
1159 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
1160 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
1162 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Promote);
1163 setOperationAction(ISD::FP_TO_SINT, MVT::i1, Promote);
1164 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
1165 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
1167 setOperationAction(ISD::FP_TO_UINT, MVT::i8, Promote);
1168 setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote);
1169 setOperationAction(ISD::UINT_TO_FP, MVT::i8, Promote);
1170 setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote);
1172 setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote);
1173 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote);
1174 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Promote);
1175 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote);
1177 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1178 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1179 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1180 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1182 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1183 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1184 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1185 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1187 setOperationAction(ISD::FABS, MVT::f32, Legal);
1188 setOperationAction(ISD::FABS, MVT::f64, Expand);
1190 setOperationAction(ISD::FNEG, MVT::f32, Legal);
1191 setOperationAction(ISD::FNEG, MVT::f64, Expand);
1194 // Expand fp<->uint.
1195 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Expand);
1196 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
1198 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
1199 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
1201 setLibcallName(RTLIB::SINTTOFP_I64_F32, "__hexagon_floatdisf");
1202 setLibcallName(RTLIB::UINTTOFP_I64_F32, "__hexagon_floatundisf");
1204 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__hexagon_floatunsisf");
1205 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__hexagon_floatsisf");
1207 setLibcallName(RTLIB::SINTTOFP_I64_F64, "__hexagon_floatdidf");
1208 setLibcallName(RTLIB::UINTTOFP_I64_F64, "__hexagon_floatundidf");
1210 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__hexagon_floatunsidf");
1211 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__hexagon_floatsidf");
1213 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__hexagon_fixunssfsi");
1214 setLibcallName(RTLIB::FPTOUINT_F32_I64, "__hexagon_fixunssfdi");
1216 setLibcallName(RTLIB::FPTOSINT_F64_I64, "__hexagon_fixdfdi");
1217 setLibcallName(RTLIB::FPTOSINT_F32_I64, "__hexagon_fixsfdi");
1219 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__hexagon_fixunsdfsi");
1220 setLibcallName(RTLIB::FPTOUINT_F64_I64, "__hexagon_fixunsdfdi");
1222 setLibcallName(RTLIB::ADD_F64, "__hexagon_adddf3");
1223 setOperationAction(ISD::FADD, MVT::f64, Expand);
1225 setLibcallName(RTLIB::ADD_F32, "__hexagon_addsf3");
1226 setOperationAction(ISD::FADD, MVT::f32, Expand);
1228 setLibcallName(RTLIB::FPEXT_F32_F64, "__hexagon_extendsfdf2");
1229 setOperationAction(ISD::FP_EXTEND, MVT::f32, Expand);
1231 setLibcallName(RTLIB::OEQ_F32, "__hexagon_eqsf2");
1232 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
1234 setLibcallName(RTLIB::OEQ_F64, "__hexagon_eqdf2");
1235 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
1237 setLibcallName(RTLIB::OGE_F32, "__hexagon_gesf2");
1238 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
1240 setLibcallName(RTLIB::OGE_F64, "__hexagon_gedf2");
1241 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
1243 setLibcallName(RTLIB::OGT_F32, "__hexagon_gtsf2");
1244 setCondCodeAction(ISD::SETOGT, MVT::f32, Expand);
1246 setLibcallName(RTLIB::OGT_F64, "__hexagon_gtdf2");
1247 setCondCodeAction(ISD::SETOGT, MVT::f64, Expand);
1249 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__hexagon_fixdfsi");
1250 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Expand);
1252 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__hexagon_fixsfsi");
1253 setOperationAction(ISD::FP_TO_SINT, MVT::f32, Expand);
1255 setLibcallName(RTLIB::OLE_F64, "__hexagon_ledf2");
1256 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
1258 setLibcallName(RTLIB::OLE_F32, "__hexagon_lesf2");
1259 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
1261 setLibcallName(RTLIB::OLT_F64, "__hexagon_ltdf2");
1262 setCondCodeAction(ISD::SETOLT, MVT::f64, Expand);
1264 setLibcallName(RTLIB::OLT_F32, "__hexagon_ltsf2");
1265 setCondCodeAction(ISD::SETOLT, MVT::f32, Expand);
1267 setLibcallName(RTLIB::MUL_F64, "__hexagon_muldf3");
1268 setOperationAction(ISD::FMUL, MVT::f64, Expand);
1270 setLibcallName(RTLIB::MUL_F32, "__hexagon_mulsf3");
1271 setOperationAction(ISD::MUL, MVT::f32, Expand);
1273 setLibcallName(RTLIB::UNE_F64, "__hexagon_nedf2");
1274 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
1276 setLibcallName(RTLIB::UNE_F32, "__hexagon_nesf2");
1278 setLibcallName(RTLIB::SUB_F64, "__hexagon_subdf3");
1279 setOperationAction(ISD::SUB, MVT::f64, Expand);
1281 setLibcallName(RTLIB::SUB_F32, "__hexagon_subsf3");
1282 setOperationAction(ISD::SUB, MVT::f32, Expand);
1284 setLibcallName(RTLIB::FPROUND_F64_F32, "__hexagon_truncdfsf2");
1285 setOperationAction(ISD::FP_ROUND, MVT::f64, Expand);
1287 setLibcallName(RTLIB::UO_F64, "__hexagon_unorddf2");
1288 setCondCodeAction(ISD::SETUO, MVT::f64, Expand);
1290 setLibcallName(RTLIB::O_F64, "__hexagon_unorddf2");
1291 setCondCodeAction(ISD::SETO, MVT::f64, Expand);
1293 setLibcallName(RTLIB::O_F32, "__hexagon_unordsf2");
1294 setCondCodeAction(ISD::SETO, MVT::f32, Expand);
1296 setLibcallName(RTLIB::UO_F32, "__hexagon_unordsf2");
1297 setCondCodeAction(ISD::SETUO, MVT::f32, Expand);
1299 setOperationAction(ISD::FABS, MVT::f32, Expand);
1300 setOperationAction(ISD::FABS, MVT::f64, Expand);
1301 setOperationAction(ISD::FNEG, MVT::f32, Expand);
1302 setOperationAction(ISD::FNEG, MVT::f64, Expand);
1305 setLibcallName(RTLIB::SREM_I32, "__hexagon_modsi3");
1306 setOperationAction(ISD::SREM, MVT::i32, Expand);
1308 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal);
1309 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal);
1310 setIndexedLoadAction(ISD::POST_INC, MVT::i32, Legal);
1311 setIndexedLoadAction(ISD::POST_INC, MVT::i64, Legal);
1313 setIndexedStoreAction(ISD::POST_INC, MVT::i8, Legal);
1314 setIndexedStoreAction(ISD::POST_INC, MVT::i16, Legal);
1315 setIndexedStoreAction(ISD::POST_INC, MVT::i32, Legal);
1316 setIndexedStoreAction(ISD::POST_INC, MVT::i64, Legal);
1318 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
1320 // Turn FP extload into load/fextend.
1321 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
1322 // Hexagon has a i1 sign extending load.
1323 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Expand);
1324 // Turn FP truncstore into trunc + store.
1325 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1327 // Custom legalize GlobalAddress nodes into CONST32.
1328 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
1329 setOperationAction(ISD::GlobalAddress, MVT::i8, Custom);
1330 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
1332 setOperationAction(ISD::TRUNCATE, MVT::i64, Expand);
1334 // Hexagon doesn't have sext_inreg, replace them with shl/sra.
1335 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
1337 // Hexagon has no REM or DIVREM operations.
1338 setOperationAction(ISD::UREM, MVT::i32, Expand);
1339 setOperationAction(ISD::SREM, MVT::i32, Expand);
1340 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
1341 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
1342 setOperationAction(ISD::SREM, MVT::i64, Expand);
1343 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
1344 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
1346 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
1348 // Lower SELECT_CC to SETCC and SELECT.
1349 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
1350 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
1352 if (QRI->Subtarget.hasV5TOps()) {
1354 // We need to make the operation type of SELECT node to be Custom,
1355 // such that we don't go into the infinite loop of
1356 // select -> setcc -> select_cc -> select loop.
1357 setOperationAction(ISD::SELECT, MVT::f32, Custom);
1358 setOperationAction(ISD::SELECT, MVT::f64, Custom);
1360 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
1361 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
1362 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
1366 // Hexagon has no select or setcc: expand to SELECT_CC.
1367 setOperationAction(ISD::SELECT, MVT::f32, Expand);
1368 setOperationAction(ISD::SELECT, MVT::f64, Expand);
1370 // This is a workaround documented in DAGCombiner.cpp:2892 We don't
1371 // support SELECT_CC on every type.
1372 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
1376 if (EmitJumpTables) {
1377 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
1379 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
1381 // Increase jump tables cutover to 5, was 4.
1382 setMinimumJumpTableEntries(5);
1384 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
1385 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
1386 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1387 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
1388 setOperationAction(ISD::BR_CC, MVT::i64, Expand);
1390 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
1392 setOperationAction(ISD::FSIN , MVT::f64, Expand);
1393 setOperationAction(ISD::FCOS , MVT::f64, Expand);
1394 setOperationAction(ISD::FREM , MVT::f64, Expand);
1395 setOperationAction(ISD::FSIN , MVT::f32, Expand);
1396 setOperationAction(ISD::FCOS , MVT::f32, Expand);
1397 setOperationAction(ISD::FREM , MVT::f32, Expand);
1398 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
1399 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
1401 // In V4, we have double word add/sub with carry. The problem with
1402 // modelling this instruction is that it produces 2 results - Rdd and Px.
1403 // To model update of Px, we will have to use Defs[p0..p3] which will
1404 // cause any predicate live range to spill. So, we pretend we dont't
1405 // have these instructions.
1406 setOperationAction(ISD::ADDE, MVT::i8, Expand);
1407 setOperationAction(ISD::ADDE, MVT::i16, Expand);
1408 setOperationAction(ISD::ADDE, MVT::i32, Expand);
1409 setOperationAction(ISD::ADDE, MVT::i64, Expand);
1410 setOperationAction(ISD::SUBE, MVT::i8, Expand);
1411 setOperationAction(ISD::SUBE, MVT::i16, Expand);
1412 setOperationAction(ISD::SUBE, MVT::i32, Expand);
1413 setOperationAction(ISD::SUBE, MVT::i64, Expand);
1414 setOperationAction(ISD::ADDC, MVT::i8, Expand);
1415 setOperationAction(ISD::ADDC, MVT::i16, Expand);
1416 setOperationAction(ISD::ADDC, MVT::i32, Expand);
1417 setOperationAction(ISD::ADDC, MVT::i64, Expand);
1418 setOperationAction(ISD::SUBC, MVT::i8, Expand);
1419 setOperationAction(ISD::SUBC, MVT::i16, Expand);
1420 setOperationAction(ISD::SUBC, MVT::i32, Expand);
1421 setOperationAction(ISD::SUBC, MVT::i64, Expand);
1423 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
1424 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
1425 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
1426 setOperationAction(ISD::CTTZ , MVT::i64, Expand);
1427 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
1428 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
1429 setOperationAction(ISD::CTLZ , MVT::i32, Expand);
1430 setOperationAction(ISD::CTLZ , MVT::i64, Expand);
1431 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
1432 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
1433 setOperationAction(ISD::ROTL , MVT::i32, Expand);
1434 setOperationAction(ISD::ROTR , MVT::i32, Expand);
1435 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
1436 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
1437 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
1438 setOperationAction(ISD::FPOW , MVT::f64, Expand);
1439 setOperationAction(ISD::FPOW , MVT::f32, Expand);
1441 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
1442 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
1443 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
1445 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
1446 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
1448 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
1449 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
1451 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
1453 if (TM.getSubtargetImpl()->isSubtargetV2()) {
1454 setExceptionPointerRegister(Hexagon::R20);
1455 setExceptionSelectorRegister(Hexagon::R21);
1457 setExceptionPointerRegister(Hexagon::R0);
1458 setExceptionSelectorRegister(Hexagon::R1);
1461 // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
1462 setOperationAction(ISD::VASTART , MVT::Other, Custom);
1464 // Use the default implementation.
1465 setOperationAction(ISD::VAARG , MVT::Other, Expand);
1466 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
1467 setOperationAction(ISD::VAEND , MVT::Other, Expand);
1468 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
1469 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
1472 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
1473 setOperationAction(ISD::INLINEASM , MVT::Other, Custom);
1475 setMinFunctionAlignment(2);
1477 // Needed for DYNAMIC_STACKALLOC expansion.
1478 unsigned StackRegister = TM.getRegisterInfo()->getStackRegister();
1479 setStackPointerRegisterToSaveRestore(StackRegister);
1480 setSchedulingPreference(Sched::VLIW);
1485 HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const {
1488 case HexagonISD::CONST32: return "HexagonISD::CONST32";
1489 case HexagonISD::CONST32_GP: return "HexagonISD::CONST32_GP";
1490 case HexagonISD::CONST32_Int_Real: return "HexagonISD::CONST32_Int_Real";
1491 case HexagonISD::ADJDYNALLOC: return "HexagonISD::ADJDYNALLOC";
1492 case HexagonISD::CMPICC: return "HexagonISD::CMPICC";
1493 case HexagonISD::CMPFCC: return "HexagonISD::CMPFCC";
1494 case HexagonISD::BRICC: return "HexagonISD::BRICC";
1495 case HexagonISD::BRFCC: return "HexagonISD::BRFCC";
1496 case HexagonISD::SELECT_ICC: return "HexagonISD::SELECT_ICC";
1497 case HexagonISD::SELECT_FCC: return "HexagonISD::SELECT_FCC";
1498 case HexagonISD::Hi: return "HexagonISD::Hi";
1499 case HexagonISD::Lo: return "HexagonISD::Lo";
1500 case HexagonISD::FTOI: return "HexagonISD::FTOI";
1501 case HexagonISD::ITOF: return "HexagonISD::ITOF";
1502 case HexagonISD::CALL: return "HexagonISD::CALL";
1503 case HexagonISD::RET_FLAG: return "HexagonISD::RET_FLAG";
1504 case HexagonISD::BR_JT: return "HexagonISD::BR_JT";
1505 case HexagonISD::TC_RETURN: return "HexagonISD::TC_RETURN";
1506 case HexagonISD::EH_RETURN: return "HexagonISD::EH_RETURN";
1511 HexagonTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
1512 EVT MTy1 = EVT::getEVT(Ty1);
1513 EVT MTy2 = EVT::getEVT(Ty2);
1514 if (!MTy1.isSimple() || !MTy2.isSimple()) {
1517 return ((MTy1.getSimpleVT() == MVT::i64) && (MTy2.getSimpleVT() == MVT::i32));
1520 bool HexagonTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
1521 if (!VT1.isSimple() || !VT2.isSimple()) {
1524 return ((VT1.getSimpleVT() == MVT::i64) && (VT2.getSimpleVT() == MVT::i32));
1528 HexagonTargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
1529 // Assuming the caller does not have either a signext or zeroext modifier, and
1530 // only one value is accepted, any reasonable truncation is allowed.
1531 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
1534 // FIXME: in principle up to 64-bit could be made safe, but it would be very
1535 // fragile at the moment: any support for multiple value returns would be
1536 // liable to disallow tail calls involving i64 -> iN truncation in many cases.
1537 return Ty1->getPrimitiveSizeInBits() <= 32;
1541 HexagonTargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
1542 SDValue Chain = Op.getOperand(0);
1543 SDValue Offset = Op.getOperand(1);
1544 SDValue Handler = Op.getOperand(2);
1547 // Mark function as containing a call to EH_RETURN.
1548 HexagonMachineFunctionInfo *FuncInfo =
1549 DAG.getMachineFunction().getInfo<HexagonMachineFunctionInfo>();
1550 FuncInfo->setHasEHReturn();
1552 unsigned OffsetReg = Hexagon::R28;
1554 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(),
1555 DAG.getRegister(Hexagon::R30, getPointerTy()),
1556 DAG.getIntPtrConstant(4));
1557 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
1559 Chain = DAG.getCopyToReg(Chain, dl, OffsetReg, Offset);
1561 // Not needed we already use it as explict input to EH_RETURN.
1562 // MF.getRegInfo().addLiveOut(OffsetReg);
1564 return DAG.getNode(HexagonISD::EH_RETURN, dl, MVT::Other, Chain);
1568 HexagonTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
1569 switch (Op.getOpcode()) {
1570 default: llvm_unreachable("Should not custom lower this!");
1571 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
1572 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
1573 // Frame & Return address. Currently unimplemented.
1574 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
1575 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
1576 case ISD::GlobalTLSAddress:
1577 llvm_unreachable("TLS not implemented for Hexagon.");
1578 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG);
1579 case ISD::GlobalAddress: return LowerGLOBALADDRESS(Op, DAG);
1580 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
1581 case ISD::VASTART: return LowerVASTART(Op, DAG);
1582 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
1584 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
1585 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
1586 case ISD::SELECT: return Op;
1587 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
1588 case ISD::INLINEASM: return LowerINLINEASM(Op, DAG);
1595 //===----------------------------------------------------------------------===//
1596 // Hexagon Scheduler Hooks
1597 //===----------------------------------------------------------------------===//
1599 HexagonTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1600 MachineBasicBlock *BB)
1602 switch (MI->getOpcode()) {
1603 case Hexagon::ADJDYNALLOC: {
1604 MachineFunction *MF = BB->getParent();
1605 HexagonMachineFunctionInfo *FuncInfo =
1606 MF->getInfo<HexagonMachineFunctionInfo>();
1607 FuncInfo->addAllocaAdjustInst(MI);
1610 default: llvm_unreachable("Unexpected instr type to insert");
1614 //===----------------------------------------------------------------------===//
1615 // Inline Assembly Support
1616 //===----------------------------------------------------------------------===//
1618 std::pair<unsigned, const TargetRegisterClass*>
1619 HexagonTargetLowering::getRegForInlineAsmConstraint(const
1620 std::string &Constraint,
1622 if (Constraint.size() == 1) {
1623 switch (Constraint[0]) {
1625 switch (VT.SimpleTy) {
1627 llvm_unreachable("getRegForInlineAsmConstraint Unhandled data type");
1632 return std::make_pair(0U, &Hexagon::IntRegsRegClass);
1635 return std::make_pair(0U, &Hexagon::DoubleRegsRegClass);
1638 llvm_unreachable("Unknown asm register class");
1642 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1645 /// isFPImmLegal - Returns true if the target can instruction select the
1646 /// specified FP immediate natively. If false, the legalizer will
1647 /// materialize the FP immediate as a load from a constant pool.
1648 bool HexagonTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
1649 const HexagonRegisterInfo* QRI = TM.getRegisterInfo();
1650 return QRI->Subtarget.hasV5TOps();
1653 /// isLegalAddressingMode - Return true if the addressing mode represented by
1654 /// AM is legal for this target, for a load/store of the specified type.
1655 bool HexagonTargetLowering::isLegalAddressingMode(const AddrMode &AM,
1657 // Allows a signed-extended 11-bit immediate field.
1658 if (AM.BaseOffs <= -(1LL << 13) || AM.BaseOffs >= (1LL << 13)-1) {
1662 // No global is ever allowed as a base.
1667 int Scale = AM.Scale;
1668 if (Scale < 0) Scale = -Scale;
1670 case 0: // No scale reg, "r+i", "r", or just "i".
1672 default: // No scaled addressing mode.
1678 /// isLegalICmpImmediate - Return true if the specified immediate is legal
1679 /// icmp immediate, that is the target has icmp instructions which can compare
1680 /// a register against the immediate without having to materialize the
1681 /// immediate into a register.
1682 bool HexagonTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
1683 return Imm >= -512 && Imm <= 511;
1686 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
1687 /// for tail call optimization. Targets which want to do tail call
1688 /// optimization should implement this function.
1689 bool HexagonTargetLowering::IsEligibleForTailCallOptimization(
1691 CallingConv::ID CalleeCC,
1693 bool isCalleeStructRet,
1694 bool isCallerStructRet,
1695 const SmallVectorImpl<ISD::OutputArg> &Outs,
1696 const SmallVectorImpl<SDValue> &OutVals,
1697 const SmallVectorImpl<ISD::InputArg> &Ins,
1698 SelectionDAG& DAG) const {
1699 const Function *CallerF = DAG.getMachineFunction().getFunction();
1700 CallingConv::ID CallerCC = CallerF->getCallingConv();
1701 bool CCMatch = CallerCC == CalleeCC;
1703 // ***************************************************************************
1704 // Look for obvious safe cases to perform tail call optimization that do not
1705 // require ABI changes.
1706 // ***************************************************************************
1708 // If this is a tail call via a function pointer, then don't do it!
1709 if (!(dyn_cast<GlobalAddressSDNode>(Callee))
1710 && !(dyn_cast<ExternalSymbolSDNode>(Callee))) {
1714 // Do not optimize if the calling conventions do not match.
1718 // Do not tail call optimize vararg calls.
1722 // Also avoid tail call optimization if either caller or callee uses struct
1723 // return semantics.
1724 if (isCalleeStructRet || isCallerStructRet)
1727 // In addition to the cases above, we also disable Tail Call Optimization if
1728 // the calling convention code that at least one outgoing argument needs to
1729 // go on the stack. We cannot check that here because at this point that
1730 // information is not available.