1 //===-- HexagonISelLowering.cpp - Hexagon DAG Lowering Implementation -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the interfaces that Hexagon uses to lower LLVM code
11 // into a selection DAG.
13 //===----------------------------------------------------------------------===//
15 #include "HexagonISelLowering.h"
16 #include "HexagonMachineFunctionInfo.h"
17 #include "HexagonSubtarget.h"
18 #include "HexagonTargetMachine.h"
19 #include "HexagonTargetObjectFile.h"
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineJumpTableInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAGISel.h"
27 #include "llvm/CodeGen/ValueTypes.h"
28 #include "llvm/IR/CallingConv.h"
29 #include "llvm/IR/DerivedTypes.h"
30 #include "llvm/IR/Function.h"
31 #include "llvm/IR/GlobalAlias.h"
32 #include "llvm/IR/GlobalVariable.h"
33 #include "llvm/IR/InlineAsm.h"
34 #include "llvm/IR/Intrinsics.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/ErrorHandling.h"
38 #include "llvm/Support/raw_ostream.h"
42 #define DEBUG_TYPE "hexagon-lowering"
45 EmitJumpTables("hexagon-emit-jump-tables", cl::init(true), cl::Hidden,
46 cl::desc("Control jump table emission on Hexagon target"));
48 static cl::opt<bool> EnableHexSDNodeSched("enable-hexagon-sdnode-sched",
49 cl::Hidden, cl::ZeroOrMore, cl::init(false),
50 cl::desc("Enable Hexagon SDNode scheduling"));
52 static cl::opt<bool> EnableFastMath("ffast-math",
53 cl::Hidden, cl::ZeroOrMore, cl::init(false),
54 cl::desc("Enable Fast Math processing"));
56 static cl::opt<int> MinimumJumpTables("minimum-jump-tables",
57 cl::Hidden, cl::ZeroOrMore, cl::init(5),
58 cl::desc("Set minimum jump tables"));
60 static cl::opt<int> MaxStoresPerMemcpyCL("max-store-memcpy",
61 cl::Hidden, cl::ZeroOrMore, cl::init(6),
62 cl::desc("Max #stores to inline memcpy"));
64 static cl::opt<int> MaxStoresPerMemcpyOptSizeCL("max-store-memcpy-Os",
65 cl::Hidden, cl::ZeroOrMore, cl::init(4),
66 cl::desc("Max #stores to inline memcpy"));
68 static cl::opt<int> MaxStoresPerMemmoveCL("max-store-memmove",
69 cl::Hidden, cl::ZeroOrMore, cl::init(6),
70 cl::desc("Max #stores to inline memmove"));
72 static cl::opt<int> MaxStoresPerMemmoveOptSizeCL("max-store-memmove-Os",
73 cl::Hidden, cl::ZeroOrMore, cl::init(4),
74 cl::desc("Max #stores to inline memmove"));
76 static cl::opt<int> MaxStoresPerMemsetCL("max-store-memset",
77 cl::Hidden, cl::ZeroOrMore, cl::init(8),
78 cl::desc("Max #stores to inline memset"));
80 static cl::opt<int> MaxStoresPerMemsetOptSizeCL("max-store-memset-Os",
81 cl::Hidden, cl::ZeroOrMore, cl::init(4),
82 cl::desc("Max #stores to inline memset"));
86 class HexagonCCState : public CCState {
87 unsigned NumNamedVarArgParams;
90 HexagonCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,
91 SmallVectorImpl<CCValAssign> &locs, LLVMContext &C,
92 int NumNamedVarArgParams)
93 : CCState(CC, isVarArg, MF, locs, C),
94 NumNamedVarArgParams(NumNamedVarArgParams) {}
96 unsigned getNumNamedVarArgParams() const { return NumNamedVarArgParams; }
100 // Implement calling convention for Hexagon.
102 CC_Hexagon(unsigned ValNo, MVT ValVT,
103 MVT LocVT, CCValAssign::LocInfo LocInfo,
104 ISD::ArgFlagsTy ArgFlags, CCState &State);
107 CC_Hexagon32(unsigned ValNo, MVT ValVT,
108 MVT LocVT, CCValAssign::LocInfo LocInfo,
109 ISD::ArgFlagsTy ArgFlags, CCState &State);
112 CC_Hexagon64(unsigned ValNo, MVT ValVT,
113 MVT LocVT, CCValAssign::LocInfo LocInfo,
114 ISD::ArgFlagsTy ArgFlags, CCState &State);
117 RetCC_Hexagon(unsigned ValNo, MVT ValVT,
118 MVT LocVT, CCValAssign::LocInfo LocInfo,
119 ISD::ArgFlagsTy ArgFlags, CCState &State);
122 RetCC_Hexagon32(unsigned ValNo, MVT ValVT,
123 MVT LocVT, CCValAssign::LocInfo LocInfo,
124 ISD::ArgFlagsTy ArgFlags, CCState &State);
127 RetCC_Hexagon64(unsigned ValNo, MVT ValVT,
128 MVT LocVT, CCValAssign::LocInfo LocInfo,
129 ISD::ArgFlagsTy ArgFlags, CCState &State);
132 CC_Hexagon_VarArg (unsigned ValNo, MVT ValVT,
133 MVT LocVT, CCValAssign::LocInfo LocInfo,
134 ISD::ArgFlagsTy ArgFlags, CCState &State) {
135 HexagonCCState &HState = static_cast<HexagonCCState &>(State);
137 if (ValNo < HState.getNumNamedVarArgParams()) {
138 // Deal with named arguments.
139 return CC_Hexagon(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State);
142 // Deal with un-named arguments.
144 if (ArgFlags.isByVal()) {
145 // If pass-by-value, the size allocated on stack is decided
146 // by ArgFlags.getByValSize(), not by the size of LocVT.
147 ofst = State.AllocateStack(ArgFlags.getByValSize(),
148 ArgFlags.getByValAlign());
149 State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo));
152 if (LocVT == MVT::i1 || LocVT == MVT::i8 || LocVT == MVT::i16) {
155 if (ArgFlags.isSExt())
156 LocInfo = CCValAssign::SExt;
157 else if (ArgFlags.isZExt())
158 LocInfo = CCValAssign::ZExt;
160 LocInfo = CCValAssign::AExt;
162 if (LocVT == MVT::i32 || LocVT == MVT::f32) {
163 ofst = State.AllocateStack(4, 4);
164 State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo));
167 if (LocVT == MVT::i64 || LocVT == MVT::f64) {
168 ofst = State.AllocateStack(8, 8);
169 State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo));
172 llvm_unreachable(nullptr);
177 CC_Hexagon (unsigned ValNo, MVT ValVT,
178 MVT LocVT, CCValAssign::LocInfo LocInfo,
179 ISD::ArgFlagsTy ArgFlags, CCState &State) {
181 if (ArgFlags.isByVal()) {
183 unsigned Offset = State.AllocateStack(ArgFlags.getByValSize(),
184 ArgFlags.getByValAlign());
185 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
189 if (LocVT == MVT::i1 || LocVT == MVT::i8 || LocVT == MVT::i16) {
192 if (ArgFlags.isSExt())
193 LocInfo = CCValAssign::SExt;
194 else if (ArgFlags.isZExt())
195 LocInfo = CCValAssign::ZExt;
197 LocInfo = CCValAssign::AExt;
198 } else if (LocVT == MVT::v4i8 || LocVT == MVT::v2i16) {
200 LocInfo = CCValAssign::BCvt;
201 } else if (LocVT == MVT::v8i8 || LocVT == MVT::v4i16 || LocVT == MVT::v2i32) {
203 LocInfo = CCValAssign::BCvt;
206 if (LocVT == MVT::i32 || LocVT == MVT::f32) {
207 if (!CC_Hexagon32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
211 if (LocVT == MVT::i64 || LocVT == MVT::f64) {
212 if (!CC_Hexagon64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
216 return true; // CC didn't match.
220 static bool CC_Hexagon32(unsigned ValNo, MVT ValVT,
221 MVT LocVT, CCValAssign::LocInfo LocInfo,
222 ISD::ArgFlagsTy ArgFlags, CCState &State) {
224 static const MCPhysReg RegList[] = {
225 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
228 if (unsigned Reg = State.AllocateReg(RegList)) {
229 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
233 unsigned Offset = State.AllocateStack(4, 4);
234 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
238 static bool CC_Hexagon64(unsigned ValNo, MVT ValVT,
239 MVT LocVT, CCValAssign::LocInfo LocInfo,
240 ISD::ArgFlagsTy ArgFlags, CCState &State) {
242 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) {
243 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
247 static const MCPhysReg RegList1[] = {
248 Hexagon::D1, Hexagon::D2
250 static const MCPhysReg RegList2[] = {
251 Hexagon::R1, Hexagon::R3
253 if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
254 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
258 unsigned Offset = State.AllocateStack(8, 8, Hexagon::D2);
259 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
263 static bool RetCC_Hexagon(unsigned ValNo, MVT ValVT,
264 MVT LocVT, CCValAssign::LocInfo LocInfo,
265 ISD::ArgFlagsTy ArgFlags, CCState &State) {
268 if (LocVT == MVT::i1 ||
273 if (ArgFlags.isSExt())
274 LocInfo = CCValAssign::SExt;
275 else if (ArgFlags.isZExt())
276 LocInfo = CCValAssign::ZExt;
278 LocInfo = CCValAssign::AExt;
279 } else if (LocVT == MVT::v4i8 || LocVT == MVT::v2i16) {
281 LocInfo = CCValAssign::BCvt;
282 } else if (LocVT == MVT::v8i8 || LocVT == MVT::v4i16 || LocVT == MVT::v2i32) {
284 LocInfo = CCValAssign::BCvt;
287 if (LocVT == MVT::i32 || LocVT == MVT::f32) {
288 if (!RetCC_Hexagon32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
292 if (LocVT == MVT::i64 || LocVT == MVT::f64) {
293 if (!RetCC_Hexagon64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
297 return true; // CC didn't match.
300 static bool RetCC_Hexagon32(unsigned ValNo, MVT ValVT,
301 MVT LocVT, CCValAssign::LocInfo LocInfo,
302 ISD::ArgFlagsTy ArgFlags, CCState &State) {
304 if (LocVT == MVT::i32 || LocVT == MVT::f32) {
305 if (unsigned Reg = State.AllocateReg(Hexagon::R0)) {
306 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
311 unsigned Offset = State.AllocateStack(4, 4);
312 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
316 static bool RetCC_Hexagon64(unsigned ValNo, MVT ValVT,
317 MVT LocVT, CCValAssign::LocInfo LocInfo,
318 ISD::ArgFlagsTy ArgFlags, CCState &State) {
319 if (LocVT == MVT::i64 || LocVT == MVT::f64) {
320 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) {
321 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
326 unsigned Offset = State.AllocateStack(8, 8);
327 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
332 HexagonTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG)
337 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
338 /// by "Src" to address "Dst" of size "Size". Alignment information is
339 /// specified by the specific parameter attribute. The copy will be passed as
340 /// a byval function parameter. Sometimes what we are copying is the end of a
341 /// larger object, the part that does not fit in registers.
343 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
344 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
347 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
348 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
349 /*isVolatile=*/false, /*AlwaysInline=*/false,
350 /*isTailCall=*/false,
351 MachinePointerInfo(), MachinePointerInfo());
355 // LowerReturn - Lower ISD::RET. If a struct is larger than 8 bytes and is
356 // passed by value, the function prototype is modified to return void and
357 // the value is stored in memory pointed by a pointer passed by caller.
359 HexagonTargetLowering::LowerReturn(SDValue Chain,
360 CallingConv::ID CallConv, bool isVarArg,
361 const SmallVectorImpl<ISD::OutputArg> &Outs,
362 const SmallVectorImpl<SDValue> &OutVals,
363 SDLoc dl, SelectionDAG &DAG) const {
365 // CCValAssign - represent the assignment of the return value to locations.
366 SmallVector<CCValAssign, 16> RVLocs;
368 // CCState - Info about the registers and stack slot.
369 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
372 // Analyze return values of ISD::RET
373 CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon);
376 SmallVector<SDValue, 4> RetOps(1, Chain);
378 // Copy the result values into the output registers.
379 for (unsigned i = 0; i != RVLocs.size(); ++i) {
380 CCValAssign &VA = RVLocs[i];
382 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
384 // Guarantee that all emitted copies are stuck together with flags.
385 Flag = Chain.getValue(1);
386 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
389 RetOps[0] = Chain; // Update chain.
391 // Add the flag if we have it.
393 RetOps.push_back(Flag);
395 return DAG.getNode(HexagonISD::RET_FLAG, dl, MVT::Other, RetOps);
398 bool HexagonTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
399 // If either no tail call or told not to tail call at all, don't.
400 if (!CI->isTailCall() || HTM.Options.DisableTailCalls)
406 /// LowerCallResult - Lower the result values of an ISD::CALL into the
407 /// appropriate copies out of appropriate physical registers. This assumes that
408 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
409 /// being lowered. Returns a SDNode with the same number of values as the
412 HexagonTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
413 CallingConv::ID CallConv, bool isVarArg,
415 SmallVectorImpl<ISD::InputArg> &Ins,
416 SDLoc dl, SelectionDAG &DAG,
417 SmallVectorImpl<SDValue> &InVals,
418 const SmallVectorImpl<SDValue> &OutVals,
419 SDValue Callee) const {
421 // Assign locations to each value returned by this call.
422 SmallVector<CCValAssign, 16> RVLocs;
424 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
427 CCInfo.AnalyzeCallResult(Ins, RetCC_Hexagon);
429 // Copy all of the result registers out of their specified physreg.
430 for (unsigned i = 0; i != RVLocs.size(); ++i) {
431 Chain = DAG.getCopyFromReg(Chain, dl,
432 RVLocs[i].getLocReg(),
433 RVLocs[i].getValVT(), InFlag).getValue(1);
434 InFlag = Chain.getValue(2);
435 InVals.push_back(Chain.getValue(0));
441 /// LowerCall - Functions arguments are copied from virtual regs to
442 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
444 HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
445 SmallVectorImpl<SDValue> &InVals) const {
446 SelectionDAG &DAG = CLI.DAG;
448 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
449 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
450 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
451 SDValue Chain = CLI.Chain;
452 SDValue Callee = CLI.Callee;
453 bool &isTailCall = CLI.IsTailCall;
454 CallingConv::ID CallConv = CLI.CallConv;
455 bool isVarArg = CLI.IsVarArg;
456 bool doesNotReturn = CLI.DoesNotReturn;
458 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
459 MachineFunction &MF = DAG.getMachineFunction();
461 // Check for varargs.
462 int NumNamedVarArgParams = -1;
463 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Callee))
465 const Function* CalleeFn = nullptr;
466 Callee = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, MVT::i32);
467 if ((CalleeFn = dyn_cast<Function>(GA->getGlobal())))
469 // If a function has zero args and is a vararg function, that's
470 // disallowed so it must be an undeclared function. Do not assume
471 // varargs if the callee is undefined.
472 if (CalleeFn->isVarArg() &&
473 CalleeFn->getFunctionType()->getNumParams() != 0) {
474 NumNamedVarArgParams = CalleeFn->getFunctionType()->getNumParams();
479 // Analyze operands of the call, assigning locations to each operand.
480 SmallVector<CCValAssign, 16> ArgLocs;
481 HexagonCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
482 *DAG.getContext(), NumNamedVarArgParams);
485 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon_VarArg);
487 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon);
489 if (DAG.getTarget().Options.DisableTailCalls)
493 bool StructAttrFlag = MF.getFunction()->hasStructRetAttr();
494 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
495 isVarArg, IsStructRet,
497 Outs, OutVals, Ins, DAG);
498 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
499 CCValAssign &VA = ArgLocs[i];
505 DEBUG(dbgs() << (isTailCall ? "Eligible for Tail Call\n"
506 : "Argument must be passed on stack. "
507 "Not eligible for Tail Call\n"));
509 // Get a count of how many bytes are to be pushed on the stack.
510 unsigned NumBytes = CCInfo.getNextStackOffset();
511 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
512 SmallVector<SDValue, 8> MemOpChains;
514 auto &HRI = *Subtarget.getRegisterInfo();
515 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, HRI.getStackRegister(),
518 // Walk the register/memloc assignments, inserting copies/loads.
519 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
520 CCValAssign &VA = ArgLocs[i];
521 SDValue Arg = OutVals[i];
522 ISD::ArgFlagsTy Flags = Outs[i].Flags;
524 // Promote the value if needed.
525 switch (VA.getLocInfo()) {
527 // Loc info must be one of Full, SExt, ZExt, or AExt.
528 llvm_unreachable("Unknown loc info!");
529 case CCValAssign::BCvt:
530 case CCValAssign::Full:
532 case CCValAssign::SExt:
533 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
535 case CCValAssign::ZExt:
536 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
538 case CCValAssign::AExt:
539 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
544 unsigned LocMemOffset = VA.getLocMemOffset();
545 SDValue MemAddr = DAG.getConstant(LocMemOffset, dl,
546 StackPtr.getValueType());
547 MemAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, MemAddr);
548 if (Flags.isByVal()) {
549 // The argument is a struct passed by value. According to LLVM, "Arg"
551 MemOpChains.push_back(CreateCopyOfByValArgument(Arg, MemAddr, Chain,
554 MachinePointerInfo LocPI = MachinePointerInfo::getStack(LocMemOffset);
555 SDValue S = DAG.getStore(Chain, dl, Arg, MemAddr, LocPI, false,
557 MemOpChains.push_back(S);
562 // Arguments that can be passed on register must be kept at RegsToPass
565 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
568 // Transform all store nodes into one single node because all store
569 // nodes are independent of each other.
570 if (!MemOpChains.empty())
571 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
574 SDValue C = DAG.getConstant(NumBytes, dl, getPointerTy(), true);
575 Chain = DAG.getCALLSEQ_START(Chain, C, dl);
578 // Build a sequence of copy-to-reg nodes chained together with token
579 // chain and flag operands which copy the outgoing args into registers.
580 // The InFlag in necessary since all emitted instructions must be
584 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
585 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
586 RegsToPass[i].second, InFlag);
587 InFlag = Chain.getValue(1);
590 // For tail calls lower the arguments to the 'real' stack slot.
592 // Force all the incoming stack arguments to be loaded from the stack
593 // before any new outgoing arguments are stored to the stack, because the
594 // outgoing stack slots may alias the incoming argument stack slots, and
595 // the alias isn't otherwise explicit. This is slightly more conservative
596 // than necessary, because it means that each store effectively depends
597 // on every argument instead of just those arguments it would clobber.
599 // Do not flag preceding copytoreg stuff together with the following stuff.
601 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
602 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
603 RegsToPass[i].second, InFlag);
604 InFlag = Chain.getValue(1);
609 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
610 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
611 // node so that legalize doesn't hack it.
612 if (flag_aligned_memcpy) {
613 const char *MemcpyName =
614 "__hexagon_memcpy_likely_aligned_min32bytes_mult8bytes";
615 Callee = DAG.getTargetExternalSymbol(MemcpyName, getPointerTy());
616 flag_aligned_memcpy = false;
617 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
618 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy());
619 } else if (ExternalSymbolSDNode *S =
620 dyn_cast<ExternalSymbolSDNode>(Callee)) {
621 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
624 // Returns a chain & a flag for retval copy to use.
625 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
626 SmallVector<SDValue, 8> Ops;
627 Ops.push_back(Chain);
628 Ops.push_back(Callee);
630 // Add argument registers to the end of the list so that they are
631 // known live into the call.
632 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
633 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
634 RegsToPass[i].second.getValueType()));
637 if (InFlag.getNode())
638 Ops.push_back(InFlag);
641 return DAG.getNode(HexagonISD::TC_RETURN, dl, NodeTys, Ops);
643 int OpCode = doesNotReturn ? HexagonISD::CALLv3nr : HexagonISD::CALLv3;
644 Chain = DAG.getNode(OpCode, dl, NodeTys, Ops);
645 InFlag = Chain.getValue(1);
647 // Create the CALLSEQ_END node.
648 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
649 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
650 InFlag = Chain.getValue(1);
652 // Handle result values, copying them out of physregs into vregs that we
654 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
655 InVals, OutVals, Callee);
658 static bool getIndexedAddressParts(SDNode *Ptr, EVT VT,
659 bool isSEXTLoad, SDValue &Base,
660 SDValue &Offset, bool &isInc,
662 if (Ptr->getOpcode() != ISD::ADD)
665 if (VT == MVT::i64 || VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
666 isInc = (Ptr->getOpcode() == ISD::ADD);
667 Base = Ptr->getOperand(0);
668 Offset = Ptr->getOperand(1);
669 // Ensure that Offset is a constant.
670 return (isa<ConstantSDNode>(Offset));
676 // TODO: Put this function along with the other isS* functions in
677 // HexagonISelDAGToDAG.cpp into a common file. Or better still, use the
678 // functions defined in HexagonOperands.td.
679 static bool Is_PostInc_S4_Offset(SDNode * S, int ShiftAmount) {
680 ConstantSDNode *N = cast<ConstantSDNode>(S);
682 // immS4 predicate - True if the immediate fits in a 4-bit sign extended.
684 int64_t v = (int64_t)N->getSExtValue();
686 if (ShiftAmount > 0) {
688 v = v >> ShiftAmount;
690 return (v <= 7) && (v >= -8) && (m == 0);
693 /// getPostIndexedAddressParts - returns true by value, base pointer and
694 /// offset pointer and addressing mode by reference if this node can be
695 /// combined with a load / store to form a post-indexed load / store.
696 bool HexagonTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
699 ISD::MemIndexedMode &AM,
700 SelectionDAG &DAG) const
704 bool isSEXTLoad = false;
706 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
707 VT = LD->getMemoryVT();
708 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
709 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
710 VT = ST->getMemoryVT();
711 if (ST->getValue().getValueType() == MVT::i64 && ST->isTruncatingStore()) {
719 bool isLegal = getIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
721 // ShiftAmount = number of left-shifted bits in the Hexagon instruction.
722 int ShiftAmount = VT.getSizeInBits() / 16;
723 if (isLegal && Is_PostInc_S4_Offset(Offset.getNode(), ShiftAmount)) {
724 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
731 SDValue HexagonTargetLowering::LowerINLINEASM(SDValue Op,
732 SelectionDAG &DAG) const {
733 SDNode *Node = Op.getNode();
734 MachineFunction &MF = DAG.getMachineFunction();
735 auto &FuncInfo = *MF.getInfo<HexagonMachineFunctionInfo>();
736 switch (Node->getOpcode()) {
737 case ISD::INLINEASM: {
738 unsigned NumOps = Node->getNumOperands();
739 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
740 --NumOps; // Ignore the flag operand.
742 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
743 if (FuncInfo.hasClobberLR())
746 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
747 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
748 ++i; // Skip the ID value.
750 switch (InlineAsm::getKind(Flags)) {
751 default: llvm_unreachable("Bad flags!");
752 case InlineAsm::Kind_RegDef:
753 case InlineAsm::Kind_RegUse:
754 case InlineAsm::Kind_Imm:
755 case InlineAsm::Kind_Clobber:
756 case InlineAsm::Kind_Mem: {
757 for (; NumVals; --NumVals, ++i) {}
760 case InlineAsm::Kind_RegDefEarlyClobber: {
761 for (; NumVals; --NumVals, ++i) {
763 cast<RegisterSDNode>(Node->getOperand(i))->getReg();
766 const HexagonRegisterInfo *QRI = Subtarget.getRegisterInfo();
767 if (Reg == QRI->getRARegister()) {
768 FuncInfo.setHasClobberLR(true);
783 // Taken from the XCore backend.
785 SDValue HexagonTargetLowering::
786 LowerBR_JT(SDValue Op, SelectionDAG &DAG) const
788 SDValue Chain = Op.getOperand(0);
789 SDValue Table = Op.getOperand(1);
790 SDValue Index = Op.getOperand(2);
792 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
793 unsigned JTI = JT->getIndex();
794 MachineFunction &MF = DAG.getMachineFunction();
795 const MachineJumpTableInfo *MJTI = MF.getJumpTableInfo();
796 SDValue TargetJT = DAG.getTargetJumpTable(JT->getIndex(), MVT::i32);
798 // Mark all jump table targets as address taken.
799 const std::vector<MachineJumpTableEntry> &JTE = MJTI->getJumpTables();
800 const std::vector<MachineBasicBlock*> &JTBBs = JTE[JTI].MBBs;
801 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
802 MachineBasicBlock *MBB = JTBBs[i];
803 MBB->setHasAddressTaken();
804 // This line is needed to set the hasAddressTaken flag on the BasicBlock
806 BlockAddress::get(const_cast<BasicBlock *>(MBB->getBasicBlock()));
809 SDValue JumpTableBase = DAG.getNode(HexagonISD::JT, dl,
810 getPointerTy(), TargetJT);
811 SDValue ShiftIndex = DAG.getNode(ISD::SHL, dl, MVT::i32, Index,
812 DAG.getConstant(2, dl, MVT::i32));
813 SDValue JTAddress = DAG.getNode(ISD::ADD, dl, MVT::i32, JumpTableBase,
815 SDValue LoadTarget = DAG.getLoad(MVT::i32, dl, Chain, JTAddress,
816 MachinePointerInfo(), false, false, false,
818 return DAG.getNode(HexagonISD::BR_JT, dl, MVT::Other, Chain, LoadTarget);
823 HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
824 SelectionDAG &DAG) const {
825 SDValue Chain = Op.getOperand(0);
826 SDValue Size = Op.getOperand(1);
827 SDValue Align = Op.getOperand(2);
830 ConstantSDNode *AlignConst = dyn_cast<ConstantSDNode>(Align);
831 assert(AlignConst && "Non-constant Align in LowerDYNAMIC_STACKALLOC");
833 unsigned A = AlignConst->getSExtValue();
834 auto &HFI = *Subtarget.getFrameLowering();
835 // "Zero" means natural stack alignment.
837 A = HFI.getStackAlignment();
840 dbgs () << LLVM_FUNCTION_NAME << " Align: " << A << " Size: ";
841 Size.getNode()->dump(&DAG);
845 SDValue AC = DAG.getConstant(A, dl, MVT::i32);
846 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other);
847 return DAG.getNode(HexagonISD::ALLOCA, dl, VTs, Chain, Size, AC);
851 HexagonTargetLowering::LowerFormalArguments(SDValue Chain,
852 CallingConv::ID CallConv,
855 SmallVectorImpl<ISD::InputArg> &Ins,
856 SDLoc dl, SelectionDAG &DAG,
857 SmallVectorImpl<SDValue> &InVals)
860 MachineFunction &MF = DAG.getMachineFunction();
861 MachineFrameInfo *MFI = MF.getFrameInfo();
862 MachineRegisterInfo &RegInfo = MF.getRegInfo();
863 auto &FuncInfo = *MF.getInfo<HexagonMachineFunctionInfo>();
865 // Assign locations to all of the incoming arguments.
866 SmallVector<CCValAssign, 16> ArgLocs;
867 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
870 CCInfo.AnalyzeFormalArguments(Ins, CC_Hexagon);
872 // For LLVM, in the case when returning a struct by value (>8byte),
873 // the first argument is a pointer that points to the location on caller's
874 // stack where the return value will be stored. For Hexagon, the location on
875 // caller's stack is passed only when the struct size is smaller than (and
876 // equal to) 8 bytes. If not, no address will be passed into callee and
877 // callee return the result direclty through R0/R1.
879 SmallVector<SDValue, 4> MemOps;
881 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
882 CCValAssign &VA = ArgLocs[i];
883 ISD::ArgFlagsTy Flags = Ins[i].Flags;
885 unsigned StackLocation;
888 if ( (VA.isRegLoc() && !Flags.isByVal())
889 || (VA.isRegLoc() && Flags.isByVal() && Flags.getByValSize() > 8)) {
890 // Arguments passed in registers
891 // 1. int, long long, ptr args that get allocated in register.
892 // 2. Large struct that gets an register to put its address in.
893 EVT RegVT = VA.getLocVT();
894 if (RegVT == MVT::i8 || RegVT == MVT::i16 ||
895 RegVT == MVT::i32 || RegVT == MVT::f32) {
897 RegInfo.createVirtualRegister(&Hexagon::IntRegsRegClass);
898 RegInfo.addLiveIn(VA.getLocReg(), VReg);
899 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
900 } else if (RegVT == MVT::i64 || RegVT == MVT::f64) {
902 RegInfo.createVirtualRegister(&Hexagon::DoubleRegsRegClass);
903 RegInfo.addLiveIn(VA.getLocReg(), VReg);
904 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
908 } else if (VA.isRegLoc() && Flags.isByVal() && Flags.getByValSize() <= 8) {
909 assert (0 && "ByValSize must be bigger than 8 bytes");
912 assert(VA.isMemLoc());
914 if (Flags.isByVal()) {
915 // If it's a byval parameter, then we need to compute the
916 // "real" size, not the size of the pointer.
917 ObjSize = Flags.getByValSize();
919 ObjSize = VA.getLocVT().getStoreSizeInBits() >> 3;
922 StackLocation = HEXAGON_LRFP_SIZE + VA.getLocMemOffset();
923 // Create the frame index object for this incoming parameter...
924 FI = MFI->CreateFixedObject(ObjSize, StackLocation, true);
926 // Create the SelectionDAG nodes cordl, responding to a load
927 // from this parameter.
928 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
930 if (Flags.isByVal()) {
931 // If it's a pass-by-value aggregate, then do not dereference the stack
932 // location. Instead, we should generate a reference to the stack
934 InVals.push_back(FIN);
936 InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
937 MachinePointerInfo(), false, false,
944 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
947 // This will point to the next argument passed via stack.
948 int FrameIndex = MFI->CreateFixedObject(Hexagon_PointerSize,
950 CCInfo.getNextStackOffset(),
952 FuncInfo.setVarArgsFrameIndex(FrameIndex);
959 HexagonTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
960 // VASTART stores the address of the VarArgsFrameIndex slot into the
961 // memory location argument.
962 MachineFunction &MF = DAG.getMachineFunction();
963 HexagonMachineFunctionInfo *QFI = MF.getInfo<HexagonMachineFunctionInfo>();
964 SDValue Addr = DAG.getFrameIndex(QFI->getVarArgsFrameIndex(), MVT::i32);
965 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
966 return DAG.getStore(Op.getOperand(0), SDLoc(Op), Addr,
967 Op.getOperand(1), MachinePointerInfo(SV), false,
971 // Creates a SPLAT instruction for a constant value VAL.
972 static SDValue createSplat(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue Val) {
973 if (VT.getSimpleVT() == MVT::v4i8)
974 return DAG.getNode(HexagonISD::VSPLATB, dl, VT, Val);
976 if (VT.getSimpleVT() == MVT::v4i16)
977 return DAG.getNode(HexagonISD::VSPLATH, dl, VT, Val);
982 static bool isSExtFree(SDValue N) {
983 // A sign-extend of a truncate of a sign-extend is free.
984 if (N.getOpcode() == ISD::TRUNCATE &&
985 N.getOperand(0).getOpcode() == ISD::AssertSext)
987 // We have sign-extended loads.
988 if (N.getOpcode() == ISD::LOAD)
993 SDValue HexagonTargetLowering::LowerCTPOP(SDValue Op, SelectionDAG &DAG) const {
995 SDValue InpVal = Op.getOperand(0);
996 if (isa<ConstantSDNode>(InpVal)) {
997 uint64_t V = cast<ConstantSDNode>(InpVal)->getZExtValue();
998 return DAG.getTargetConstant(countPopulation(V), dl, MVT::i64);
1000 SDValue PopOut = DAG.getNode(HexagonISD::POPCOUNT, dl, MVT::i32, InpVal);
1001 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, PopOut);
1004 SDValue HexagonTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1007 SDValue LHS = Op.getOperand(0);
1008 SDValue RHS = Op.getOperand(1);
1009 SDValue Cmp = Op.getOperand(2);
1010 ISD::CondCode CC = cast<CondCodeSDNode>(Cmp)->get();
1012 EVT VT = Op.getValueType();
1013 EVT LHSVT = LHS.getValueType();
1014 EVT RHSVT = RHS.getValueType();
1016 if (LHSVT == MVT::v2i16) {
1017 assert(ISD::isSignedIntSetCC(CC) || ISD::isUnsignedIntSetCC(CC));
1018 unsigned ExtOpc = ISD::isSignedIntSetCC(CC) ? ISD::SIGN_EXTEND
1020 SDValue LX = DAG.getNode(ExtOpc, dl, MVT::v2i32, LHS);
1021 SDValue RX = DAG.getNode(ExtOpc, dl, MVT::v2i32, RHS);
1022 SDValue SC = DAG.getNode(ISD::SETCC, dl, MVT::v2i1, LX, RX, Cmp);
1026 // Treat all other vector types as legal.
1030 // Equals and not equals should use sign-extend, not zero-extend, since
1031 // we can represent small negative values in the compare instructions.
1032 // The LLVM default is to use zero-extend arbitrarily in these cases.
1033 if ((CC == ISD::SETEQ || CC == ISD::SETNE) &&
1034 (RHSVT == MVT::i8 || RHSVT == MVT::i16) &&
1035 (LHSVT == MVT::i8 || LHSVT == MVT::i16)) {
1036 ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS);
1037 if (C && C->getAPIntValue().isNegative()) {
1038 LHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, LHS);
1039 RHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, RHS);
1040 return DAG.getNode(ISD::SETCC, dl, Op.getValueType(),
1041 LHS, RHS, Op.getOperand(2));
1043 if (isSExtFree(LHS) || isSExtFree(RHS)) {
1044 LHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, LHS);
1045 RHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, RHS);
1046 return DAG.getNode(ISD::SETCC, dl, Op.getValueType(),
1047 LHS, RHS, Op.getOperand(2));
1053 SDValue HexagonTargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG)
1055 SDValue PredOp = Op.getOperand(0);
1056 SDValue Op1 = Op.getOperand(1), Op2 = Op.getOperand(2);
1057 EVT OpVT = Op1.getValueType();
1060 if (OpVT == MVT::v2i16) {
1061 SDValue X1 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v2i32, Op1);
1062 SDValue X2 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v2i32, Op2);
1063 SDValue SL = DAG.getNode(ISD::VSELECT, DL, MVT::v2i32, PredOp, X1, X2);
1064 SDValue TR = DAG.getNode(ISD::TRUNCATE, DL, MVT::v2i16, SL);
1071 // Handle only specific vector loads.
1072 SDValue HexagonTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1073 EVT VT = Op.getValueType();
1075 LoadSDNode *LoadNode = cast<LoadSDNode>(Op);
1076 SDValue Chain = LoadNode->getChain();
1077 SDValue Ptr = Op.getOperand(1);
1078 SDValue LoweredLoad;
1080 SDValue Base = LoadNode->getBasePtr();
1081 ISD::LoadExtType Ext = LoadNode->getExtensionType();
1082 unsigned Alignment = LoadNode->getAlignment();
1085 if(Ext == ISD::NON_EXTLOAD)
1086 Ext = ISD::ZEXTLOAD;
1088 if (VT == MVT::v4i16) {
1089 if (Alignment == 2) {
1092 Loads[0] = DAG.getExtLoad(Ext, DL, MVT::i32, Chain, Base,
1093 LoadNode->getPointerInfo(), MVT::i16,
1094 LoadNode->isVolatile(),
1095 LoadNode->isNonTemporal(),
1096 LoadNode->isInvariant(),
1099 SDValue Increment = DAG.getConstant(2, DL, MVT::i32);
1100 Ptr = DAG.getNode(ISD::ADD, DL, Base.getValueType(), Base, Increment);
1101 Loads[1] = DAG.getExtLoad(Ext, DL, MVT::i32, Chain, Ptr,
1102 LoadNode->getPointerInfo(), MVT::i16,
1103 LoadNode->isVolatile(),
1104 LoadNode->isNonTemporal(),
1105 LoadNode->isInvariant(),
1107 // SHL 16, then OR base and base+2.
1108 SDValue ShiftAmount = DAG.getConstant(16, DL, MVT::i32);
1109 SDValue Tmp1 = DAG.getNode(ISD::SHL, DL, MVT::i32, Loads[1], ShiftAmount);
1110 SDValue Tmp2 = DAG.getNode(ISD::OR, DL, MVT::i32, Tmp1, Loads[0]);
1112 Increment = DAG.getConstant(4, DL, MVT::i32);
1113 Ptr = DAG.getNode(ISD::ADD, DL, Base.getValueType(), Base, Increment);
1114 Loads[2] = DAG.getExtLoad(Ext, DL, MVT::i32, Chain, Ptr,
1115 LoadNode->getPointerInfo(), MVT::i16,
1116 LoadNode->isVolatile(),
1117 LoadNode->isNonTemporal(),
1118 LoadNode->isInvariant(),
1121 Increment = DAG.getConstant(6, DL, MVT::i32);
1122 Ptr = DAG.getNode(ISD::ADD, DL, Base.getValueType(), Base, Increment);
1123 Loads[3] = DAG.getExtLoad(Ext, DL, MVT::i32, Chain, Ptr,
1124 LoadNode->getPointerInfo(), MVT::i16,
1125 LoadNode->isVolatile(),
1126 LoadNode->isNonTemporal(),
1127 LoadNode->isInvariant(),
1129 // SHL 16, then OR base+4 and base+6.
1130 Tmp1 = DAG.getNode(ISD::SHL, DL, MVT::i32, Loads[3], ShiftAmount);
1131 SDValue Tmp4 = DAG.getNode(ISD::OR, DL, MVT::i32, Tmp1, Loads[2]);
1132 // Combine to i64. This could be optimised out later if we can
1133 // affect reg allocation of this code.
1134 Result = DAG.getNode(HexagonISD::COMBINE, DL, MVT::i64, Tmp4, Tmp2);
1135 LoadChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
1136 Loads[0].getValue(1), Loads[1].getValue(1),
1137 Loads[2].getValue(1), Loads[3].getValue(1));
1139 // Perform default type expansion.
1140 Result = DAG.getLoad(MVT::i64, DL, Chain, Ptr, LoadNode->getPointerInfo(),
1141 LoadNode->isVolatile(), LoadNode->isNonTemporal(),
1142 LoadNode->isInvariant(), LoadNode->getAlignment());
1143 LoadChain = Result.getValue(1);
1146 llvm_unreachable("Custom lowering unsupported load");
1148 Result = DAG.getNode(ISD::BITCAST, DL, VT, Result);
1149 // Since we pretend to lower a load, we need the original chain
1150 // info attached to the result.
1151 SDValue Ops[] = { Result, LoadChain };
1153 return DAG.getMergeValues(Ops, DL);
1158 HexagonTargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
1159 EVT ValTy = Op.getValueType();
1161 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1163 if (CP->isMachineConstantPoolEntry())
1164 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), ValTy,
1165 CP->getAlignment());
1167 Res = DAG.getTargetConstantPool(CP->getConstVal(), ValTy,
1168 CP->getAlignment());
1169 return DAG.getNode(HexagonISD::CP, dl, ValTy, Res);
1173 HexagonTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const {
1174 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1175 MachineFunction &MF = DAG.getMachineFunction();
1176 MachineFrameInfo &MFI = *MF.getFrameInfo();
1177 MFI.setReturnAddressIsTaken(true);
1179 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
1182 EVT VT = Op.getValueType();
1184 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1186 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
1187 SDValue Offset = DAG.getConstant(4, dl, MVT::i32);
1188 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
1189 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
1190 MachinePointerInfo(), false, false, false, 0);
1193 // Return LR, which contains the return address. Mark it an implicit live-in.
1194 unsigned Reg = MF.addLiveIn(HRI.getRARegister(), getRegClassFor(MVT::i32));
1195 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
1199 HexagonTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
1200 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1201 MachineFrameInfo &MFI = *DAG.getMachineFunction().getFrameInfo();
1202 MFI.setFrameAddressIsTaken(true);
1204 EVT VT = Op.getValueType();
1206 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1207 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
1208 HRI.getFrameRegister(), VT);
1210 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
1211 MachinePointerInfo(),
1212 false, false, false, 0);
1216 SDValue HexagonTargetLowering::LowerATOMIC_FENCE(SDValue Op,
1217 SelectionDAG& DAG) const {
1219 return DAG.getNode(HexagonISD::BARRIER, dl, MVT::Other, Op.getOperand(0));
1223 SDValue HexagonTargetLowering::LowerGLOBALADDRESS(SDValue Op,
1224 SelectionDAG &DAG) const {
1226 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1227 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
1229 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
1231 const HexagonTargetObjectFile *TLOF =
1232 static_cast<const HexagonTargetObjectFile *>(
1233 getTargetMachine().getObjFileLowering());
1234 if (TLOF->IsGlobalInSmallSection(GV, getTargetMachine())) {
1235 return DAG.getNode(HexagonISD::CONST32_GP, dl, getPointerTy(), Result);
1238 return DAG.getNode(HexagonISD::CONST32, dl, getPointerTy(), Result);
1241 // Specifies that for loads and stores VT can be promoted to PromotedLdStVT.
1242 void HexagonTargetLowering::promoteLdStType(EVT VT, EVT PromotedLdStVT) {
1243 if (VT != PromotedLdStVT) {
1244 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
1245 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(),
1246 PromotedLdStVT.getSimpleVT());
1248 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
1249 AddPromotedToType(ISD::STORE, VT.getSimpleVT(),
1250 PromotedLdStVT.getSimpleVT());
1255 HexagonTargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
1256 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1257 SDValue BA_SD = DAG.getTargetBlockAddress(BA, MVT::i32);
1259 return DAG.getNode(HexagonISD::CONST32_GP, dl, getPointerTy(), BA_SD);
1262 //===----------------------------------------------------------------------===//
1263 // TargetLowering Implementation
1264 //===----------------------------------------------------------------------===//
1266 HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
1267 const HexagonSubtarget &STI)
1268 : TargetLowering(TM), HTM(static_cast<const HexagonTargetMachine&>(TM)),
1270 bool IsV4 = !Subtarget.hasV5TOps();
1271 auto &HRI = *Subtarget.getRegisterInfo();
1273 setPrefLoopAlignment(4);
1274 setPrefFunctionAlignment(4);
1275 setMinFunctionAlignment(2);
1276 setInsertFencesForAtomic(false);
1277 setExceptionPointerRegister(Hexagon::R0);
1278 setExceptionSelectorRegister(Hexagon::R1);
1279 setStackPointerRegisterToSaveRestore(HRI.getStackRegister());
1281 if (EnableHexSDNodeSched)
1282 setSchedulingPreference(Sched::VLIW);
1284 setSchedulingPreference(Sched::Source);
1286 // Limits for inline expansion of memcpy/memmove
1287 MaxStoresPerMemcpy = MaxStoresPerMemcpyCL;
1288 MaxStoresPerMemcpyOptSize = MaxStoresPerMemcpyOptSizeCL;
1289 MaxStoresPerMemmove = MaxStoresPerMemmoveCL;
1290 MaxStoresPerMemmoveOptSize = MaxStoresPerMemmoveOptSizeCL;
1291 MaxStoresPerMemset = MaxStoresPerMemsetCL;
1292 MaxStoresPerMemsetOptSize = MaxStoresPerMemsetOptSizeCL;
1295 // Set up register classes.
1298 addRegisterClass(MVT::i1, &Hexagon::PredRegsRegClass);
1299 addRegisterClass(MVT::v2i1, &Hexagon::PredRegsRegClass); // bbbbaaaa
1300 addRegisterClass(MVT::v4i1, &Hexagon::PredRegsRegClass); // ddccbbaa
1301 addRegisterClass(MVT::v8i1, &Hexagon::PredRegsRegClass); // hgfedcba
1302 addRegisterClass(MVT::i32, &Hexagon::IntRegsRegClass);
1303 addRegisterClass(MVT::v4i8, &Hexagon::IntRegsRegClass);
1304 addRegisterClass(MVT::v2i16, &Hexagon::IntRegsRegClass);
1305 addRegisterClass(MVT::i64, &Hexagon::DoubleRegsRegClass);
1306 addRegisterClass(MVT::v8i8, &Hexagon::DoubleRegsRegClass);
1307 addRegisterClass(MVT::v4i16, &Hexagon::DoubleRegsRegClass);
1308 addRegisterClass(MVT::v2i32, &Hexagon::DoubleRegsRegClass);
1310 if (Subtarget.hasV5TOps()) {
1311 addRegisterClass(MVT::f32, &Hexagon::IntRegsRegClass);
1312 addRegisterClass(MVT::f64, &Hexagon::DoubleRegsRegClass);
1316 // Handling of scalar operations.
1318 // All operations default to "legal", except:
1319 // - indexed loads and stores (pre-/post-incremented),
1320 // - ANY_EXTEND_VECTOR_INREG, ATOMIC_CMP_SWAP_WITH_SUCCESS, CONCAT_VECTORS,
1321 // ConstantFP, DEBUGTRAP, FCEIL, FCOPYSIGN, FEXP, FEXP2, FFLOOR, FGETSIGN,
1322 // FLOG, FLOG2, FLOG10, FMAXNUM, FMINNUM, FNEARBYINT, FRINT, FROUND, TRAP,
1323 // FTRUNC, PREFETCH, SIGN_EXTEND_VECTOR_INREG, ZERO_EXTEND_VECTOR_INREG,
1324 // which default to "expand" for at least one type.
1327 setOperationAction(ISD::ConstantFP, MVT::f32, Legal); // Default: expand
1328 setOperationAction(ISD::ConstantFP, MVT::f64, Legal); // Default: expand
1330 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
1331 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
1332 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
1333 setOperationAction(ISD::INLINEASM, MVT::Other, Custom);
1334 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
1335 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
1337 // Custom legalize GlobalAddress nodes into CONST32.
1338 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
1339 setOperationAction(ISD::GlobalAddress, MVT::i8, Custom);
1340 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
1342 // Hexagon needs to optimize cases with negative constants.
1343 setOperationAction(ISD::SETCC, MVT::i8, Custom);
1344 setOperationAction(ISD::SETCC, MVT::i16, Custom);
1346 // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
1347 setOperationAction(ISD::VASTART, MVT::Other, Custom);
1348 setOperationAction(ISD::VAEND, MVT::Other, Expand);
1349 setOperationAction(ISD::VAARG, MVT::Other, Expand);
1351 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
1352 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
1353 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
1356 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
1358 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
1359 // Increase jump tables cutover to 5, was 4.
1360 setMinimumJumpTableEntries(MinimumJumpTables);
1362 // Hexagon has instructions for add/sub with carry. The problem with
1363 // modeling these instructions is that they produce 2 results: Rdd and Px.
1364 // To model the update of Px, we will have to use Defs[p0..p3] which will
1365 // cause any predicate live range to spill. So, we pretend we dont't have
1366 // these instructions.
1367 setOperationAction(ISD::ADDE, MVT::i8, Expand);
1368 setOperationAction(ISD::ADDE, MVT::i16, Expand);
1369 setOperationAction(ISD::ADDE, MVT::i32, Expand);
1370 setOperationAction(ISD::ADDE, MVT::i64, Expand);
1371 setOperationAction(ISD::SUBE, MVT::i8, Expand);
1372 setOperationAction(ISD::SUBE, MVT::i16, Expand);
1373 setOperationAction(ISD::SUBE, MVT::i32, Expand);
1374 setOperationAction(ISD::SUBE, MVT::i64, Expand);
1375 setOperationAction(ISD::ADDC, MVT::i8, Expand);
1376 setOperationAction(ISD::ADDC, MVT::i16, Expand);
1377 setOperationAction(ISD::ADDC, MVT::i32, Expand);
1378 setOperationAction(ISD::ADDC, MVT::i64, Expand);
1379 setOperationAction(ISD::SUBC, MVT::i8, Expand);
1380 setOperationAction(ISD::SUBC, MVT::i16, Expand);
1381 setOperationAction(ISD::SUBC, MVT::i32, Expand);
1382 setOperationAction(ISD::SUBC, MVT::i64, Expand);
1384 // Only add and sub that detect overflow are the saturating ones.
1385 for (MVT VT : MVT::integer_valuetypes()) {
1386 setOperationAction(ISD::UADDO, VT, Expand);
1387 setOperationAction(ISD::SADDO, VT, Expand);
1388 setOperationAction(ISD::USUBO, VT, Expand);
1389 setOperationAction(ISD::SSUBO, VT, Expand);
1392 setOperationAction(ISD::CTLZ, MVT::i8, Promote);
1393 setOperationAction(ISD::CTLZ, MVT::i16, Promote);
1394 setOperationAction(ISD::CTTZ, MVT::i8, Promote);
1395 setOperationAction(ISD::CTTZ, MVT::i16, Promote);
1396 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8, Promote);
1397 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16, Promote);
1398 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i8, Promote);
1399 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16, Promote);
1401 // In V5, popcount can count # of 1s in i64 but returns i32.
1402 // On V4 it will be expanded (set later).
1403 setOperationAction(ISD::CTPOP, MVT::i8, Promote);
1404 setOperationAction(ISD::CTPOP, MVT::i16, Promote);
1405 setOperationAction(ISD::CTPOP, MVT::i32, Promote);
1406 setOperationAction(ISD::CTPOP, MVT::i64, Custom);
1408 // We custom lower i64 to i64 mul, so that it is not considered as a legal
1409 // operation. There is a pattern that will match i64 mul and transform it
1410 // to a series of instructions.
1411 setOperationAction(ISD::MUL, MVT::i64, Expand);
1412 setOperationAction(ISD::MULHS, MVT::i64, Expand);
1414 for (unsigned IntExpOp :
1415 {ISD::SDIV, ISD::UDIV, ISD::SREM, ISD::UREM, ISD::SDIVREM, ISD::UDIVREM,
1416 ISD::ROTL, ISD::ROTR, ISD::BSWAP, ISD::SHL_PARTS, ISD::SRA_PARTS,
1417 ISD::SRL_PARTS, ISD::SMUL_LOHI, ISD::UMUL_LOHI}) {
1418 setOperationAction(IntExpOp, MVT::i32, Expand);
1419 setOperationAction(IntExpOp, MVT::i64, Expand);
1422 for (unsigned FPExpOp :
1423 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS,
1424 ISD::FPOW, ISD::FCOPYSIGN}) {
1425 setOperationAction(FPExpOp, MVT::f32, Expand);
1426 setOperationAction(FPExpOp, MVT::f64, Expand);
1429 // No extending loads from i32.
1430 for (MVT VT : MVT::integer_valuetypes()) {
1431 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand);
1432 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand);
1433 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i32, Expand);
1435 // Turn FP truncstore into trunc + store.
1436 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1437 // Turn FP extload into load/fextend.
1438 for (MVT VT : MVT::fp_valuetypes())
1439 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
1441 // Expand BR_CC and SELECT_CC for all integer and fp types.
1442 for (MVT VT : MVT::integer_valuetypes()) {
1443 setOperationAction(ISD::BR_CC, VT, Expand);
1444 setOperationAction(ISD::SELECT_CC, VT, Expand);
1446 for (MVT VT : MVT::fp_valuetypes()) {
1447 setOperationAction(ISD::BR_CC, VT, Expand);
1448 setOperationAction(ISD::SELECT_CC, VT, Expand);
1450 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
1453 // Handling of vector operations.
1456 // Custom lower v4i16 load only. Let v4i16 store to be
1457 // promoted for now.
1458 promoteLdStType(MVT::v4i8, MVT::i32);
1459 promoteLdStType(MVT::v2i16, MVT::i32);
1460 promoteLdStType(MVT::v8i8, MVT::i64);
1461 promoteLdStType(MVT::v2i32, MVT::i64);
1463 setOperationAction(ISD::LOAD, MVT::v4i16, Custom);
1464 setOperationAction(ISD::STORE, MVT::v4i16, Promote);
1465 AddPromotedToType(ISD::LOAD, MVT::v4i16, MVT::i64);
1466 AddPromotedToType(ISD::STORE, MVT::v4i16, MVT::i64);
1468 // Set the action for vector operations to "expand", then override it with
1469 // either "custom" or "legal" for specific cases.
1470 static unsigned VectExpOps[] = {
1471 // Integer arithmetic:
1472 ISD::ADD, ISD::SUB, ISD::MUL, ISD::SDIV, ISD::UDIV,
1473 ISD::SREM, ISD::UREM, ISD::SDIVREM, ISD::UDIVREM, ISD::ADDC,
1474 ISD::SUBC, ISD::SADDO, ISD::UADDO, ISD::SSUBO, ISD::USUBO,
1475 ISD::SMUL_LOHI, ISD::UMUL_LOHI,
1477 ISD::AND, ISD::OR, ISD::XOR, ISD::ROTL, ISD::ROTR,
1478 ISD::CTPOP, ISD::CTLZ, ISD::CTTZ, ISD::CTLZ_ZERO_UNDEF,
1479 ISD::CTTZ_ZERO_UNDEF,
1480 // Floating point arithmetic/math functions:
1481 ISD::FADD, ISD::FSUB, ISD::FMUL, ISD::FMA, ISD::FDIV,
1482 ISD::FREM, ISD::FNEG, ISD::FABS, ISD::FSQRT, ISD::FSIN,
1483 ISD::FCOS, ISD::FPOWI, ISD::FPOW, ISD::FLOG, ISD::FLOG2,
1484 ISD::FLOG10, ISD::FEXP, ISD::FEXP2, ISD::FCEIL, ISD::FTRUNC,
1485 ISD::FRINT, ISD::FNEARBYINT, ISD::FROUND, ISD::FFLOOR,
1486 ISD::FMINNUM, ISD::FMAXNUM, ISD::FSINCOS,
1488 ISD::SELECT, ISD::ConstantPool,
1490 ISD::BUILD_VECTOR, ISD::SCALAR_TO_VECTOR,
1491 ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT,
1492 ISD::EXTRACT_SUBVECTOR, ISD::INSERT_SUBVECTOR,
1493 ISD::CONCAT_VECTORS, ISD::VECTOR_SHUFFLE
1496 for (MVT VT : MVT::vector_valuetypes()) {
1497 for (unsigned VectExpOp : VectExpOps)
1498 setOperationAction(VectExpOp, VT, Expand);
1500 // Expand all extended loads and truncating stores:
1501 for (MVT TargetVT : MVT::vector_valuetypes()) {
1502 setLoadExtAction(ISD::EXTLOAD, TargetVT, VT, Expand);
1503 setTruncStoreAction(VT, TargetVT, Expand);
1506 setOperationAction(ISD::SRA, VT, Custom);
1507 setOperationAction(ISD::SHL, VT, Custom);
1508 setOperationAction(ISD::SRL, VT, Custom);
1511 // Types natively supported:
1512 for (MVT NativeVT : {MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v32i1, MVT::v64i1,
1513 MVT::v4i8, MVT::v8i8, MVT::v2i16, MVT::v4i16, MVT::v1i32,
1514 MVT::v2i32, MVT::v1i64}) {
1515 setOperationAction(ISD::BUILD_VECTOR, NativeVT, Custom);
1516 setOperationAction(ISD::EXTRACT_VECTOR_ELT, NativeVT, Custom);
1517 setOperationAction(ISD::INSERT_VECTOR_ELT, NativeVT, Custom);
1518 setOperationAction(ISD::EXTRACT_SUBVECTOR, NativeVT, Custom);
1519 setOperationAction(ISD::INSERT_SUBVECTOR, NativeVT, Custom);
1520 setOperationAction(ISD::CONCAT_VECTORS, NativeVT, Custom);
1522 setOperationAction(ISD::ADD, NativeVT, Legal);
1523 setOperationAction(ISD::SUB, NativeVT, Legal);
1524 setOperationAction(ISD::MUL, NativeVT, Legal);
1525 setOperationAction(ISD::AND, NativeVT, Legal);
1526 setOperationAction(ISD::OR, NativeVT, Legal);
1527 setOperationAction(ISD::XOR, NativeVT, Legal);
1530 setOperationAction(ISD::SETCC, MVT::v2i16, Custom);
1531 setOperationAction(ISD::VSELECT, MVT::v2i16, Custom);
1532 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
1533 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
1535 // Subtarget-specific operation actions.
1537 if (Subtarget.hasV5TOps()) {
1538 setOperationAction(ISD::FMA, MVT::f64, Expand);
1539 setOperationAction(ISD::FADD, MVT::f64, Expand);
1540 setOperationAction(ISD::FSUB, MVT::f64, Expand);
1541 setOperationAction(ISD::FMUL, MVT::f64, Expand);
1543 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Promote);
1544 setOperationAction(ISD::FP_TO_UINT, MVT::i8, Promote);
1545 setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote);
1546 setOperationAction(ISD::FP_TO_SINT, MVT::i1, Promote);
1547 setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote);
1548 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote);
1549 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
1550 setOperationAction(ISD::UINT_TO_FP, MVT::i8, Promote);
1551 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Promote);
1552 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
1553 setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote);
1554 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote);
1557 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
1558 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Expand);
1559 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
1560 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
1561 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Expand);
1562 setOperationAction(ISD::FP_TO_SINT, MVT::f32, Expand);
1563 setOperationAction(ISD::FP_EXTEND, MVT::f32, Expand);
1564 setOperationAction(ISD::FP_ROUND, MVT::f64, Expand);
1565 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
1567 setOperationAction(ISD::CTPOP, MVT::i8, Expand);
1568 setOperationAction(ISD::CTPOP, MVT::i16, Expand);
1569 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
1570 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
1572 // Expand these operations for both f32 and f64:
1573 for (unsigned FPExpOpV4 :
1574 {ISD::FADD, ISD::FSUB, ISD::FMUL, ISD::FABS, ISD::FNEG, ISD::FMA}) {
1575 setOperationAction(FPExpOpV4, MVT::f32, Expand);
1576 setOperationAction(FPExpOpV4, MVT::f64, Expand);
1579 for (ISD::CondCode FPExpCCV4 :
1580 {ISD::SETOEQ, ISD::SETOGT, ISD::SETOLT, ISD::SETOGE, ISD::SETOLE,
1581 ISD::SETUO, ISD::SETO}) {
1582 setCondCodeAction(FPExpCCV4, MVT::f32, Expand);
1583 setCondCodeAction(FPExpCCV4, MVT::f64, Expand);
1587 // Handling of indexed loads/stores: default is "expand".
1589 for (MVT LSXTy : {MVT::i8, MVT::i16, MVT::i32, MVT::i64}) {
1590 setIndexedLoadAction(ISD::POST_INC, LSXTy, Legal);
1591 setIndexedStoreAction(ISD::POST_INC, LSXTy, Legal);
1594 computeRegisterProperties(&HRI);
1597 // Library calls for unsupported operations
1599 bool FastMath = EnableFastMath;
1601 setLibcallName(RTLIB::SDIV_I32, "__hexagon_divsi3");
1602 setLibcallName(RTLIB::SDIV_I64, "__hexagon_divdi3");
1603 setLibcallName(RTLIB::UDIV_I32, "__hexagon_udivsi3");
1604 setLibcallName(RTLIB::UDIV_I64, "__hexagon_udivdi3");
1605 setLibcallName(RTLIB::SREM_I32, "__hexagon_modsi3");
1606 setLibcallName(RTLIB::SREM_I64, "__hexagon_moddi3");
1607 setLibcallName(RTLIB::UREM_I32, "__hexagon_umodsi3");
1608 setLibcallName(RTLIB::UREM_I64, "__hexagon_umoddi3");
1610 setLibcallName(RTLIB::SINTTOFP_I128_F64, "__hexagon_floattidf");
1611 setLibcallName(RTLIB::SINTTOFP_I128_F32, "__hexagon_floattisf");
1612 setLibcallName(RTLIB::FPTOUINT_F32_I128, "__hexagon_fixunssfti");
1613 setLibcallName(RTLIB::FPTOUINT_F64_I128, "__hexagon_fixunsdfti");
1614 setLibcallName(RTLIB::FPTOSINT_F32_I128, "__hexagon_fixsfti");
1615 setLibcallName(RTLIB::FPTOSINT_F64_I128, "__hexagon_fixdfti");
1618 // Handle single-precision floating point operations on V4.
1620 setLibcallName(RTLIB::ADD_F32, "__hexagon_fast_addsf3");
1621 setLibcallName(RTLIB::SUB_F32, "__hexagon_fast_subsf3");
1622 setLibcallName(RTLIB::MUL_F32, "__hexagon_fast_mulsf3");
1623 setLibcallName(RTLIB::OGT_F32, "__hexagon_fast_gtsf2");
1624 setLibcallName(RTLIB::OLT_F32, "__hexagon_fast_ltsf2");
1625 // Double-precision compares.
1626 setLibcallName(RTLIB::OGT_F64, "__hexagon_fast_gtdf2");
1627 setLibcallName(RTLIB::OLT_F64, "__hexagon_fast_ltdf2");
1629 setLibcallName(RTLIB::ADD_F32, "__hexagon_addsf3");
1630 setLibcallName(RTLIB::SUB_F32, "__hexagon_subsf3");
1631 setLibcallName(RTLIB::MUL_F32, "__hexagon_mulsf3");
1632 setLibcallName(RTLIB::OGT_F32, "__hexagon_gtsf2");
1633 setLibcallName(RTLIB::OLT_F32, "__hexagon_ltsf2");
1634 // Double-precision compares.
1635 setLibcallName(RTLIB::OGT_F64, "__hexagon_gtdf2");
1636 setLibcallName(RTLIB::OLT_F64, "__hexagon_ltdf2");
1640 // This is the only fast library function for sqrtd.
1642 setLibcallName(RTLIB::SQRT_F64, "__hexagon_fast2_sqrtdf2");
1644 // Prefix is: nothing for "slow-math",
1645 // "fast2_" for V4 fast-math and V5+ fast-math double-precision
1646 // (actually, keep fast-math and fast-math2 separate for now)
1648 setLibcallName(RTLIB::ADD_F64, "__hexagon_fast_adddf3");
1649 setLibcallName(RTLIB::SUB_F64, "__hexagon_fast_subdf3");
1650 setLibcallName(RTLIB::MUL_F64, "__hexagon_fast_muldf3");
1651 setLibcallName(RTLIB::DIV_F64, "__hexagon_fast_divdf3");
1652 // Calling __hexagon_fast2_divsf3 with fast-math on V5 (ok).
1653 setLibcallName(RTLIB::DIV_F32, "__hexagon_fast_divsf3");
1655 setLibcallName(RTLIB::ADD_F64, "__hexagon_adddf3");
1656 setLibcallName(RTLIB::SUB_F64, "__hexagon_subdf3");
1657 setLibcallName(RTLIB::MUL_F64, "__hexagon_muldf3");
1658 setLibcallName(RTLIB::DIV_F64, "__hexagon_divdf3");
1659 setLibcallName(RTLIB::DIV_F32, "__hexagon_divsf3");
1662 if (Subtarget.hasV5TOps()) {
1664 setLibcallName(RTLIB::SQRT_F32, "__hexagon_fast2_sqrtf");
1666 setLibcallName(RTLIB::SQRT_F32, "__hexagon_sqrtf");
1669 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__hexagon_floatsisf");
1670 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__hexagon_floatsidf");
1671 setLibcallName(RTLIB::SINTTOFP_I64_F32, "__hexagon_floatdisf");
1672 setLibcallName(RTLIB::SINTTOFP_I64_F64, "__hexagon_floatdidf");
1673 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__hexagon_floatunsisf");
1674 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__hexagon_floatunsidf");
1675 setLibcallName(RTLIB::UINTTOFP_I64_F32, "__hexagon_floatundisf");
1676 setLibcallName(RTLIB::UINTTOFP_I64_F64, "__hexagon_floatundidf");
1677 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__hexagon_fixunssfsi");
1678 setLibcallName(RTLIB::FPTOUINT_F32_I64, "__hexagon_fixunssfdi");
1679 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__hexagon_fixunsdfsi");
1680 setLibcallName(RTLIB::FPTOUINT_F64_I64, "__hexagon_fixunsdfdi");
1681 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__hexagon_fixsfsi");
1682 setLibcallName(RTLIB::FPTOSINT_F32_I64, "__hexagon_fixsfdi");
1683 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__hexagon_fixdfsi");
1684 setLibcallName(RTLIB::FPTOSINT_F64_I64, "__hexagon_fixdfdi");
1685 setLibcallName(RTLIB::FPEXT_F32_F64, "__hexagon_extendsfdf2");
1686 setLibcallName(RTLIB::FPROUND_F64_F32, "__hexagon_truncdfsf2");
1687 setLibcallName(RTLIB::OEQ_F32, "__hexagon_eqsf2");
1688 setLibcallName(RTLIB::OEQ_F64, "__hexagon_eqdf2");
1689 setLibcallName(RTLIB::OGE_F32, "__hexagon_gesf2");
1690 setLibcallName(RTLIB::OGE_F64, "__hexagon_gedf2");
1691 setLibcallName(RTLIB::OLE_F32, "__hexagon_lesf2");
1692 setLibcallName(RTLIB::OLE_F64, "__hexagon_ledf2");
1693 setLibcallName(RTLIB::UNE_F32, "__hexagon_nesf2");
1694 setLibcallName(RTLIB::UNE_F64, "__hexagon_nedf2");
1695 setLibcallName(RTLIB::UO_F32, "__hexagon_unordsf2");
1696 setLibcallName(RTLIB::UO_F64, "__hexagon_unorddf2");
1697 setLibcallName(RTLIB::O_F32, "__hexagon_unordsf2");
1698 setLibcallName(RTLIB::O_F64, "__hexagon_unorddf2");
1701 // These cause problems when the shift amount is non-constant.
1702 setLibcallName(RTLIB::SHL_I128, nullptr);
1703 setLibcallName(RTLIB::SRL_I128, nullptr);
1704 setLibcallName(RTLIB::SRA_I128, nullptr);
1708 const char* HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const {
1710 default: return nullptr;
1711 case HexagonISD::ALLOCA: return "HexagonISD::ALLOCA";
1712 case HexagonISD::ARGEXTEND: return "HexagonISD::ARGEXTEND";
1713 case HexagonISD::AT_GOT: return "HexagonISD::AT_GOT";
1714 case HexagonISD::AT_PCREL: return "HexagonISD::AT_PCREL";
1715 case HexagonISD::BARRIER: return "HexagonISD::BARRIER";
1716 case HexagonISD::BR_JT: return "HexagonISD::BR_JT";
1717 case HexagonISD::CALLR: return "HexagonISD::CALLR";
1718 case HexagonISD::CALLv3nr: return "HexagonISD::CALLv3nr";
1719 case HexagonISD::CALLv3: return "HexagonISD::CALLv3";
1720 case HexagonISD::COMBINE: return "HexagonISD::COMBINE";
1721 case HexagonISD::CONST32_GP: return "HexagonISD::CONST32_GP";
1722 case HexagonISD::CONST32: return "HexagonISD::CONST32";
1723 case HexagonISD::CP: return "HexagonISD::CP";
1724 case HexagonISD::DCFETCH: return "HexagonISD::DCFETCH";
1725 case HexagonISD::EH_RETURN: return "HexagonISD::EH_RETURN";
1726 case HexagonISD::EXTRACTU: return "HexagonISD::EXTRACTU";
1727 case HexagonISD::EXTRACTURP: return "HexagonISD::EXTRACTURP";
1728 case HexagonISD::FCONST32: return "HexagonISD::FCONST32";
1729 case HexagonISD::INSERT: return "HexagonISD::INSERT";
1730 case HexagonISD::INSERTRP: return "HexagonISD::INSERTRP";
1731 case HexagonISD::JT: return "HexagonISD::JT";
1732 case HexagonISD::PACKHL: return "HexagonISD::PACKHL";
1733 case HexagonISD::PIC_ADD: return "HexagonISD::PIC_ADD";
1734 case HexagonISD::POPCOUNT: return "HexagonISD::POPCOUNT";
1735 case HexagonISD::RET_FLAG: return "HexagonISD::RET_FLAG";
1736 case HexagonISD::SHUFFEB: return "HexagonISD::SHUFFEB";
1737 case HexagonISD::SHUFFEH: return "HexagonISD::SHUFFEH";
1738 case HexagonISD::SHUFFOB: return "HexagonISD::SHUFFOB";
1739 case HexagonISD::SHUFFOH: return "HexagonISD::SHUFFOH";
1740 case HexagonISD::TC_RETURN: return "HexagonISD::TC_RETURN";
1741 case HexagonISD::VCMPBEQ: return "HexagonISD::VCMPBEQ";
1742 case HexagonISD::VCMPBGT: return "HexagonISD::VCMPBGT";
1743 case HexagonISD::VCMPBGTU: return "HexagonISD::VCMPBGTU";
1744 case HexagonISD::VCMPHEQ: return "HexagonISD::VCMPHEQ";
1745 case HexagonISD::VCMPHGT: return "HexagonISD::VCMPHGT";
1746 case HexagonISD::VCMPHGTU: return "HexagonISD::VCMPHGTU";
1747 case HexagonISD::VCMPWEQ: return "HexagonISD::VCMPWEQ";
1748 case HexagonISD::VCMPWGT: return "HexagonISD::VCMPWGT";
1749 case HexagonISD::VCMPWGTU: return "HexagonISD::VCMPWGTU";
1750 case HexagonISD::VSHLH: return "HexagonISD::VSHLH";
1751 case HexagonISD::VSHLW: return "HexagonISD::VSHLW";
1752 case HexagonISD::VSPLATB: return "HexagonISD::VSPLTB";
1753 case HexagonISD::VSPLATH: return "HexagonISD::VSPLATH";
1754 case HexagonISD::VSRAH: return "HexagonISD::VSRAH";
1755 case HexagonISD::VSRAW: return "HexagonISD::VSRAW";
1756 case HexagonISD::VSRLH: return "HexagonISD::VSRLH";
1757 case HexagonISD::VSRLW: return "HexagonISD::VSRLW";
1758 case HexagonISD::VSXTBH: return "HexagonISD::VSXTBH";
1759 case HexagonISD::VSXTBW: return "HexagonISD::VSXTBW";
1763 bool HexagonTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
1764 EVT MTy1 = EVT::getEVT(Ty1);
1765 EVT MTy2 = EVT::getEVT(Ty2);
1766 if (!MTy1.isSimple() || !MTy2.isSimple())
1768 return (MTy1.getSimpleVT() == MVT::i64) && (MTy2.getSimpleVT() == MVT::i32);
1771 bool HexagonTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
1772 if (!VT1.isSimple() || !VT2.isSimple())
1774 return (VT1.getSimpleVT() == MVT::i64) && (VT2.getSimpleVT() == MVT::i32);
1777 // shouldExpandBuildVectorWithShuffles
1778 // Should we expand the build vector with shuffles?
1780 HexagonTargetLowering::shouldExpandBuildVectorWithShuffles(EVT VT,
1781 unsigned DefinedValues) const {
1783 // Hexagon vector shuffle operates on element sizes of bytes or halfwords
1784 EVT EltVT = VT.getVectorElementType();
1785 int EltBits = EltVT.getSizeInBits();
1786 if ((EltBits != 8) && (EltBits != 16))
1789 return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
1792 // LowerVECTOR_SHUFFLE - Lower a vector shuffle (V1, V2, V3). V1 and
1793 // V2 are the two vectors to select data from, V3 is the permutation.
1794 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
1795 const ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op);
1796 SDValue V1 = Op.getOperand(0);
1797 SDValue V2 = Op.getOperand(1);
1799 EVT VT = Op.getValueType();
1801 if (V2.getOpcode() == ISD::UNDEF)
1804 if (SVN->isSplat()) {
1805 int Lane = SVN->getSplatIndex();
1806 if (Lane == -1) Lane = 0;
1808 // Test if V1 is a SCALAR_TO_VECTOR.
1809 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR)
1810 return createSplat(DAG, dl, VT, V1.getOperand(0));
1812 // Test if V1 is a BUILD_VECTOR which is equivalent to a SCALAR_TO_VECTOR
1813 // (and probably will turn into a SCALAR_TO_VECTOR once legalization
1815 if (Lane == 0 && V1.getOpcode() == ISD::BUILD_VECTOR &&
1816 !isa<ConstantSDNode>(V1.getOperand(0))) {
1817 bool IsScalarToVector = true;
1818 for (unsigned i = 1, e = V1.getNumOperands(); i != e; ++i)
1819 if (V1.getOperand(i).getOpcode() != ISD::UNDEF) {
1820 IsScalarToVector = false;
1823 if (IsScalarToVector)
1824 return createSplat(DAG, dl, VT, V1.getOperand(0));
1826 return createSplat(DAG, dl, VT, DAG.getConstant(Lane, dl, MVT::i32));
1829 // FIXME: We need to support more general vector shuffles. See
1830 // below the comment from the ARM backend that deals in the general
1831 // case with the vector shuffles. For now, let expand handle these.
1834 // If the shuffle is not directly supported and it has 4 elements, use
1835 // the PerfectShuffle-generated table to synthesize it from other shuffles.
1838 // If BUILD_VECTOR has same base element repeated several times,
1840 static bool isCommonSplatElement(BuildVectorSDNode *BVN) {
1841 unsigned NElts = BVN->getNumOperands();
1842 SDValue V0 = BVN->getOperand(0);
1844 for (unsigned i = 1, e = NElts; i != e; ++i) {
1845 if (BVN->getOperand(i) != V0)
1851 // LowerVECTOR_SHIFT - Lower a vector shift. Try to convert
1852 // <VT> = SHL/SRA/SRL <VT> by <VT> to Hexagon specific
1853 // <VT> = SHL/SRA/SRL <VT> by <IT/i32>.
1854 static SDValue LowerVECTOR_SHIFT(SDValue Op, SelectionDAG &DAG) {
1855 BuildVectorSDNode *BVN = 0;
1856 SDValue V1 = Op.getOperand(0);
1857 SDValue V2 = Op.getOperand(1);
1860 EVT VT = Op.getValueType();
1862 if ((BVN = dyn_cast<BuildVectorSDNode>(V1.getNode())) &&
1863 isCommonSplatElement(BVN))
1865 else if ((BVN = dyn_cast<BuildVectorSDNode>(V2.getNode())) &&
1866 isCommonSplatElement(BVN))
1871 SDValue CommonSplat = BVN->getOperand(0);
1874 if (VT.getSimpleVT() == MVT::v4i16) {
1875 switch (Op.getOpcode()) {
1877 Result = DAG.getNode(HexagonISD::VSRAH, dl, VT, V3, CommonSplat);
1880 Result = DAG.getNode(HexagonISD::VSHLH, dl, VT, V3, CommonSplat);
1883 Result = DAG.getNode(HexagonISD::VSRLH, dl, VT, V3, CommonSplat);
1888 } else if (VT.getSimpleVT() == MVT::v2i32) {
1889 switch (Op.getOpcode()) {
1891 Result = DAG.getNode(HexagonISD::VSRAW, dl, VT, V3, CommonSplat);
1894 Result = DAG.getNode(HexagonISD::VSHLW, dl, VT, V3, CommonSplat);
1897 Result = DAG.getNode(HexagonISD::VSRLW, dl, VT, V3, CommonSplat);
1906 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
1910 HexagonTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
1911 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
1913 EVT VT = Op.getValueType();
1915 unsigned Size = VT.getSizeInBits();
1917 // A vector larger than 64 bits cannot be represented in Hexagon.
1918 // Expand will split the vector.
1922 APInt APSplatBits, APSplatUndef;
1923 unsigned SplatBitSize;
1925 unsigned NElts = BVN->getNumOperands();
1927 // Try to generate a SPLAT instruction.
1928 if ((VT.getSimpleVT() == MVT::v4i8 || VT.getSimpleVT() == MVT::v4i16) &&
1929 (BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
1930 HasAnyUndefs, 0, true) && SplatBitSize <= 16)) {
1931 unsigned SplatBits = APSplatBits.getZExtValue();
1932 int32_t SextVal = ((int32_t) (SplatBits << (32 - SplatBitSize)) >>
1933 (32 - SplatBitSize));
1934 return createSplat(DAG, dl, VT, DAG.getConstant(SextVal, dl, MVT::i32));
1937 // Try to generate COMBINE to build v2i32 vectors.
1938 if (VT.getSimpleVT() == MVT::v2i32) {
1939 SDValue V0 = BVN->getOperand(0);
1940 SDValue V1 = BVN->getOperand(1);
1942 if (V0.getOpcode() == ISD::UNDEF)
1943 V0 = DAG.getConstant(0, dl, MVT::i32);
1944 if (V1.getOpcode() == ISD::UNDEF)
1945 V1 = DAG.getConstant(0, dl, MVT::i32);
1947 ConstantSDNode *C0 = dyn_cast<ConstantSDNode>(V0);
1948 ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(V1);
1949 // If the element isn't a constant, it is in a register:
1950 // generate a COMBINE Register Register instruction.
1952 return DAG.getNode(HexagonISD::COMBINE, dl, VT, V1, V0);
1954 // If one of the operands is an 8 bit integer constant, generate
1955 // a COMBINE Immediate Immediate instruction.
1956 if (isInt<8>(C0->getSExtValue()) ||
1957 isInt<8>(C1->getSExtValue()))
1958 return DAG.getNode(HexagonISD::COMBINE, dl, VT, V1, V0);
1961 // Try to generate a S2_packhl to build v2i16 vectors.
1962 if (VT.getSimpleVT() == MVT::v2i16) {
1963 for (unsigned i = 0, e = NElts; i != e; ++i) {
1964 if (BVN->getOperand(i).getOpcode() == ISD::UNDEF)
1966 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(BVN->getOperand(i));
1967 // If the element isn't a constant, it is in a register:
1968 // generate a S2_packhl instruction.
1970 SDValue pack = DAG.getNode(HexagonISD::PACKHL, dl, MVT::v4i16,
1971 BVN->getOperand(1), BVN->getOperand(0));
1973 return DAG.getTargetExtractSubreg(Hexagon::subreg_loreg, dl, MVT::v2i16,
1979 // In the general case, generate a CONST32 or a CONST64 for constant vectors,
1980 // and insert_vector_elt for all the other cases.
1982 unsigned EltSize = Size / NElts;
1984 uint64_t Mask = ~uint64_t(0ULL) >> (64 - EltSize);
1985 bool HasNonConstantElements = false;
1987 for (unsigned i = 0, e = NElts; i != e; ++i) {
1988 // LLVM's BUILD_VECTOR operands are in Little Endian mode, whereas Hexagon's
1989 // combine, const64, etc. are Big Endian.
1990 unsigned OpIdx = NElts - i - 1;
1991 SDValue Operand = BVN->getOperand(OpIdx);
1992 if (Operand.getOpcode() == ISD::UNDEF)
1996 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Operand))
1997 Val = Cst->getSExtValue();
1999 HasNonConstantElements = true;
2002 Res = (Res << EltSize) | Val;
2006 ConstVal = DAG.getConstant(Res, dl, MVT::i64);
2008 ConstVal = DAG.getConstant(Res, dl, MVT::i32);
2010 // When there are non constant operands, add them with INSERT_VECTOR_ELT to
2011 // ConstVal, the constant part of the vector.
2012 if (HasNonConstantElements) {
2013 EVT EltVT = VT.getVectorElementType();
2014 SDValue Width = DAG.getConstant(EltVT.getSizeInBits(), dl, MVT::i64);
2015 SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width,
2016 DAG.getConstant(32, dl, MVT::i64));
2018 for (unsigned i = 0, e = NElts; i != e; ++i) {
2019 // LLVM's BUILD_VECTOR operands are in Little Endian mode, whereas Hexagon
2021 unsigned OpIdx = NElts - i - 1;
2022 SDValue Operand = BVN->getOperand(OpIdx);
2023 if (isa<ConstantSDNode>(Operand))
2024 // This operand is already in ConstVal.
2027 if (VT.getSizeInBits() == 64 &&
2028 Operand.getValueType().getSizeInBits() == 32) {
2029 SDValue C = DAG.getConstant(0, dl, MVT::i32);
2030 Operand = DAG.getNode(HexagonISD::COMBINE, dl, VT, C, Operand);
2033 SDValue Idx = DAG.getConstant(OpIdx, dl, MVT::i64);
2034 SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i64, Idx, Width);
2035 SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset);
2036 const SDValue Ops[] = {ConstVal, Operand, Combined};
2038 if (VT.getSizeInBits() == 32)
2039 ConstVal = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i32, Ops);
2041 ConstVal = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i64, Ops);
2045 return DAG.getNode(ISD::BITCAST, dl, VT, ConstVal);
2049 HexagonTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
2050 SelectionDAG &DAG) const {
2052 EVT VT = Op.getValueType();
2053 unsigned NElts = Op.getNumOperands();
2054 SDValue Vec = Op.getOperand(0);
2055 EVT VecVT = Vec.getValueType();
2056 SDValue Width = DAG.getConstant(VecVT.getSizeInBits(), dl, MVT::i64);
2057 SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width,
2058 DAG.getConstant(32, dl, MVT::i64));
2059 SDValue ConstVal = DAG.getConstant(0, dl, MVT::i64);
2061 ConstantSDNode *W = dyn_cast<ConstantSDNode>(Width);
2062 ConstantSDNode *S = dyn_cast<ConstantSDNode>(Shifted);
2064 if ((VecVT.getSimpleVT() == MVT::v2i16) && (NElts == 2) && W && S) {
2065 if ((W->getZExtValue() == 32) && ((S->getZExtValue() >> 32) == 32)) {
2066 // We are trying to concat two v2i16 to a single v4i16.
2067 SDValue Vec0 = Op.getOperand(1);
2068 SDValue Combined = DAG.getNode(HexagonISD::COMBINE, dl, VT, Vec0, Vec);
2069 return DAG.getNode(ISD::BITCAST, dl, VT, Combined);
2073 if ((VecVT.getSimpleVT() == MVT::v4i8) && (NElts == 2) && W && S) {
2074 if ((W->getZExtValue() == 32) && ((S->getZExtValue() >> 32) == 32)) {
2075 // We are trying to concat two v4i8 to a single v8i8.
2076 SDValue Vec0 = Op.getOperand(1);
2077 SDValue Combined = DAG.getNode(HexagonISD::COMBINE, dl, VT, Vec0, Vec);
2078 return DAG.getNode(ISD::BITCAST, dl, VT, Combined);
2082 for (unsigned i = 0, e = NElts; i != e; ++i) {
2083 unsigned OpIdx = NElts - i - 1;
2084 SDValue Operand = Op.getOperand(OpIdx);
2086 if (VT.getSizeInBits() == 64 &&
2087 Operand.getValueType().getSizeInBits() == 32) {
2088 SDValue C = DAG.getConstant(0, dl, MVT::i32);
2089 Operand = DAG.getNode(HexagonISD::COMBINE, dl, VT, C, Operand);
2092 SDValue Idx = DAG.getConstant(OpIdx, dl, MVT::i64);
2093 SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i64, Idx, Width);
2094 SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset);
2095 const SDValue Ops[] = {ConstVal, Operand, Combined};
2097 if (VT.getSizeInBits() == 32)
2098 ConstVal = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i32, Ops);
2100 ConstVal = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i64, Ops);
2103 return DAG.getNode(ISD::BITCAST, dl, VT, ConstVal);
2107 HexagonTargetLowering::LowerEXTRACT_VECTOR(SDValue Op,
2108 SelectionDAG &DAG) const {
2109 EVT VT = Op.getValueType();
2110 int VTN = VT.isVector() ? VT.getVectorNumElements() : 1;
2112 SDValue Idx = Op.getOperand(1);
2113 SDValue Vec = Op.getOperand(0);
2114 EVT VecVT = Vec.getValueType();
2115 EVT EltVT = VecVT.getVectorElementType();
2116 int EltSize = EltVT.getSizeInBits();
2117 SDValue Width = DAG.getConstant(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT ?
2118 EltSize : VTN * EltSize, dl, MVT::i64);
2120 // Constant element number.
2121 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Idx)) {
2122 uint64_t X = CI->getZExtValue();
2123 SDValue Offset = DAG.getConstant(X * EltSize, dl, MVT::i32);
2124 const SDValue Ops[] = {Vec, Width, Offset};
2126 ConstantSDNode *CW = dyn_cast<ConstantSDNode>(Width);
2127 assert(CW && "Non constant width in LowerEXTRACT_VECTOR");
2130 MVT SVT = VecVT.getSimpleVT();
2131 uint64_t W = CW->getZExtValue();
2134 // Translate this node into EXTRACT_SUBREG.
2135 unsigned Subreg = (X == 0) ? Hexagon::subreg_loreg : 0;
2138 Subreg = Hexagon::subreg_loreg;
2139 else if (SVT == MVT::v2i32 && X == 1)
2140 Subreg = Hexagon::subreg_hireg;
2141 else if (SVT == MVT::v4i16 && X == 2)
2142 Subreg = Hexagon::subreg_hireg;
2143 else if (SVT == MVT::v8i8 && X == 4)
2144 Subreg = Hexagon::subreg_hireg;
2146 llvm_unreachable("Bad offset");
2147 N = DAG.getTargetExtractSubreg(Subreg, dl, MVT::i32, Vec);
2149 } else if (VecVT.getSizeInBits() == 32) {
2150 N = DAG.getNode(HexagonISD::EXTRACTU, dl, MVT::i32, Ops);
2152 N = DAG.getNode(HexagonISD::EXTRACTU, dl, MVT::i64, Ops);
2153 if (VT.getSizeInBits() == 32)
2154 N = DAG.getTargetExtractSubreg(Hexagon::subreg_loreg, dl, MVT::i32, N);
2157 return DAG.getNode(ISD::BITCAST, dl, VT, N);
2160 // Variable element number.
2161 SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i32, Idx,
2162 DAG.getConstant(EltSize, dl, MVT::i32));
2163 SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width,
2164 DAG.getConstant(32, dl, MVT::i64));
2165 SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset);
2167 const SDValue Ops[] = {Vec, Combined};
2170 if (VecVT.getSizeInBits() == 32) {
2171 N = DAG.getNode(HexagonISD::EXTRACTURP, dl, MVT::i32, Ops);
2173 N = DAG.getNode(HexagonISD::EXTRACTURP, dl, MVT::i64, Ops);
2174 if (VT.getSizeInBits() == 32)
2175 N = DAG.getTargetExtractSubreg(Hexagon::subreg_loreg, dl, MVT::i32, N);
2177 return DAG.getNode(ISD::BITCAST, dl, VT, N);
2181 HexagonTargetLowering::LowerINSERT_VECTOR(SDValue Op,
2182 SelectionDAG &DAG) const {
2183 EVT VT = Op.getValueType();
2184 int VTN = VT.isVector() ? VT.getVectorNumElements() : 1;
2186 SDValue Vec = Op.getOperand(0);
2187 SDValue Val = Op.getOperand(1);
2188 SDValue Idx = Op.getOperand(2);
2189 EVT VecVT = Vec.getValueType();
2190 EVT EltVT = VecVT.getVectorElementType();
2191 int EltSize = EltVT.getSizeInBits();
2192 SDValue Width = DAG.getConstant(Op.getOpcode() == ISD::INSERT_VECTOR_ELT ?
2193 EltSize : VTN * EltSize, dl, MVT::i64);
2195 if (ConstantSDNode *C = cast<ConstantSDNode>(Idx)) {
2196 SDValue Offset = DAG.getConstant(C->getSExtValue() * EltSize, dl, MVT::i32);
2197 const SDValue Ops[] = {Vec, Val, Width, Offset};
2200 if (VT.getSizeInBits() == 32)
2201 N = DAG.getNode(HexagonISD::INSERT, dl, MVT::i32, Ops);
2203 N = DAG.getNode(HexagonISD::INSERT, dl, MVT::i64, Ops);
2205 return DAG.getNode(ISD::BITCAST, dl, VT, N);
2208 // Variable element number.
2209 SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i32, Idx,
2210 DAG.getConstant(EltSize, dl, MVT::i32));
2211 SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width,
2212 DAG.getConstant(32, dl, MVT::i64));
2213 SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset);
2215 if (VT.getSizeInBits() == 64 &&
2216 Val.getValueType().getSizeInBits() == 32) {
2217 SDValue C = DAG.getConstant(0, dl, MVT::i32);
2218 Val = DAG.getNode(HexagonISD::COMBINE, dl, VT, C, Val);
2221 const SDValue Ops[] = {Vec, Val, Combined};
2224 if (VT.getSizeInBits() == 32)
2225 N = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i32, Ops);
2227 N = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i64, Ops);
2229 return DAG.getNode(ISD::BITCAST, dl, VT, N);
2233 HexagonTargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
2234 // Assuming the caller does not have either a signext or zeroext modifier, and
2235 // only one value is accepted, any reasonable truncation is allowed.
2236 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
2239 // FIXME: in principle up to 64-bit could be made safe, but it would be very
2240 // fragile at the moment: any support for multiple value returns would be
2241 // liable to disallow tail calls involving i64 -> iN truncation in many cases.
2242 return Ty1->getPrimitiveSizeInBits() <= 32;
2246 HexagonTargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
2247 SDValue Chain = Op.getOperand(0);
2248 SDValue Offset = Op.getOperand(1);
2249 SDValue Handler = Op.getOperand(2);
2252 // Mark function as containing a call to EH_RETURN.
2253 HexagonMachineFunctionInfo *FuncInfo =
2254 DAG.getMachineFunction().getInfo<HexagonMachineFunctionInfo>();
2255 FuncInfo->setHasEHReturn();
2257 unsigned OffsetReg = Hexagon::R28;
2259 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(),
2260 DAG.getRegister(Hexagon::R30, getPointerTy()),
2261 DAG.getIntPtrConstant(4, dl));
2262 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
2264 Chain = DAG.getCopyToReg(Chain, dl, OffsetReg, Offset);
2266 // Not needed we already use it as explict input to EH_RETURN.
2267 // MF.getRegInfo().addLiveOut(OffsetReg);
2269 return DAG.getNode(HexagonISD::EH_RETURN, dl, MVT::Other, Chain);
2273 HexagonTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
2274 unsigned Opc = Op.getOpcode();
2278 Op.getNode()->dumpr(&DAG);
2279 if (Opc > HexagonISD::OP_BEGIN && Opc < HexagonISD::OP_END)
2280 errs() << "Check for a non-legal type in this operation\n";
2282 llvm_unreachable("Should not custom lower this!");
2283 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
2284 case ISD::INSERT_SUBVECTOR: return LowerINSERT_VECTOR(Op, DAG);
2285 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR(Op, DAG);
2286 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_VECTOR(Op, DAG);
2287 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR(Op, DAG);
2288 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
2289 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
2292 case ISD::SRL: return LowerVECTOR_SHIFT(Op, DAG);
2293 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
2294 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
2295 // Frame & Return address. Currently unimplemented.
2296 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
2297 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
2298 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG);
2299 case ISD::GlobalAddress: return LowerGLOBALADDRESS(Op, DAG);
2300 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
2301 case ISD::VASTART: return LowerVASTART(Op, DAG);
2302 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
2303 // Custom lower some vector loads.
2304 case ISD::LOAD: return LowerLOAD(Op, DAG);
2305 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
2306 case ISD::SETCC: return LowerSETCC(Op, DAG);
2307 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
2308 case ISD::CTPOP: return LowerCTPOP(Op, DAG);
2309 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
2310 case ISD::INLINEASM: return LowerINLINEASM(Op, DAG);
2315 HexagonTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
2316 MachineBasicBlock *BB)
2318 switch (MI->getOpcode()) {
2319 case Hexagon::ALLOCA: {
2320 MachineFunction *MF = BB->getParent();
2321 auto *FuncInfo = MF->getInfo<HexagonMachineFunctionInfo>();
2322 FuncInfo->addAllocaAdjustInst(MI);
2325 default: llvm_unreachable("Unexpected instr type to insert");
2329 //===----------------------------------------------------------------------===//
2330 // Inline Assembly Support
2331 //===----------------------------------------------------------------------===//
2333 std::pair<unsigned, const TargetRegisterClass *>
2334 HexagonTargetLowering::getRegForInlineAsmConstraint(
2335 const TargetRegisterInfo *TRI, const std::string &Constraint,
2337 if (Constraint.size() == 1) {
2338 switch (Constraint[0]) {
2340 switch (VT.SimpleTy) {
2342 llvm_unreachable("getRegForInlineAsmConstraint Unhandled data type");
2347 return std::make_pair(0U, &Hexagon::IntRegsRegClass);
2350 return std::make_pair(0U, &Hexagon::DoubleRegsRegClass);
2353 llvm_unreachable("Unknown asm register class");
2357 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
2360 /// isFPImmLegal - Returns true if the target can instruction select the
2361 /// specified FP immediate natively. If false, the legalizer will
2362 /// materialize the FP immediate as a load from a constant pool.
2363 bool HexagonTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
2364 return Subtarget.hasV5TOps();
2367 /// isLegalAddressingMode - Return true if the addressing mode represented by
2368 /// AM is legal for this target, for a load/store of the specified type.
2369 bool HexagonTargetLowering::isLegalAddressingMode(const AddrMode &AM,
2371 // Allows a signed-extended 11-bit immediate field.
2372 if (AM.BaseOffs <= -(1LL << 13) || AM.BaseOffs >= (1LL << 13)-1)
2375 // No global is ever allowed as a base.
2379 int Scale = AM.Scale;
2380 if (Scale < 0) Scale = -Scale;
2382 case 0: // No scale reg, "r+i", "r", or just "i".
2384 default: // No scaled addressing mode.
2390 /// isLegalICmpImmediate - Return true if the specified immediate is legal
2391 /// icmp immediate, that is the target has icmp instructions which can compare
2392 /// a register against the immediate without having to materialize the
2393 /// immediate into a register.
2394 bool HexagonTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
2395 return Imm >= -512 && Imm <= 511;
2398 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2399 /// for tail call optimization. Targets which want to do tail call
2400 /// optimization should implement this function.
2401 bool HexagonTargetLowering::IsEligibleForTailCallOptimization(
2403 CallingConv::ID CalleeCC,
2405 bool isCalleeStructRet,
2406 bool isCallerStructRet,
2407 const SmallVectorImpl<ISD::OutputArg> &Outs,
2408 const SmallVectorImpl<SDValue> &OutVals,
2409 const SmallVectorImpl<ISD::InputArg> &Ins,
2410 SelectionDAG& DAG) const {
2411 const Function *CallerF = DAG.getMachineFunction().getFunction();
2412 CallingConv::ID CallerCC = CallerF->getCallingConv();
2413 bool CCMatch = CallerCC == CalleeCC;
2415 // ***************************************************************************
2416 // Look for obvious safe cases to perform tail call optimization that do not
2417 // require ABI changes.
2418 // ***************************************************************************
2420 // If this is a tail call via a function pointer, then don't do it!
2421 if (!(dyn_cast<GlobalAddressSDNode>(Callee))
2422 && !(dyn_cast<ExternalSymbolSDNode>(Callee))) {
2426 // Do not optimize if the calling conventions do not match.
2430 // Do not tail call optimize vararg calls.
2434 // Also avoid tail call optimization if either caller or callee uses struct
2435 // return semantics.
2436 if (isCalleeStructRet || isCallerStructRet)
2439 // In addition to the cases above, we also disable Tail Call Optimization if
2440 // the calling convention code that at least one outgoing argument needs to
2441 // go on the stack. We cannot check that here because at this point that
2442 // information is not available.
2446 // Return true when the given node fits in a positive half word.
2447 bool llvm::isPositiveHalfWord(SDNode *N) {
2448 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
2449 if (CN && CN->getSExtValue() > 0 && isInt<16>(CN->getSExtValue()))
2452 switch (N->getOpcode()) {
2455 case ISD::SIGN_EXTEND_INREG: