1 //===-- HexagonISelDAGToDAG.cpp - A dag to dag inst selector for Hexagon --===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the Hexagon target.
12 //===----------------------------------------------------------------------===//
15 #include "HexagonISelLowering.h"
16 #include "HexagonTargetMachine.h"
17 #include "llvm/ADT/DenseMap.h"
18 #include "llvm/CodeGen/SelectionDAGISel.h"
19 #include "llvm/IR/Intrinsics.h"
20 #include "llvm/Support/CommandLine.h"
21 #include "llvm/Support/Compiler.h"
22 #include "llvm/Support/Debug.h"
25 #define DEBUG_TYPE "hexagon-isel"
29 MaxNumOfUsesForConstExtenders("ga-max-num-uses-for-constant-extenders",
30 cl::Hidden, cl::init(2),
31 cl::desc("Maximum number of uses of a global address such that we still us a"
32 "constant extended instruction"));
34 //===----------------------------------------------------------------------===//
35 // Instruction Selector Implementation
36 //===----------------------------------------------------------------------===//
39 void initializeHexagonDAGToDAGISelPass(PassRegistry&);
42 //===--------------------------------------------------------------------===//
43 /// HexagonDAGToDAGISel - Hexagon specific code to select Hexagon machine
44 /// instructions for SelectionDAG operations.
47 class HexagonDAGToDAGISel : public SelectionDAGISel {
48 /// Subtarget - Keep a pointer to the Hexagon Subtarget around so that we can
49 /// make the right decision when generating code for different targets.
50 const HexagonSubtarget *Subtarget;
52 // Keep a reference to HexagonTargetMachine.
53 const HexagonTargetMachine& TM;
54 DenseMap<const GlobalValue *, unsigned> GlobalAddressUseCountMap;
56 explicit HexagonDAGToDAGISel(HexagonTargetMachine &targetmachine,
57 CodeGenOpt::Level OptLevel)
58 : SelectionDAGISel(targetmachine, OptLevel), TM(targetmachine) {
59 initializeHexagonDAGToDAGISelPass(*PassRegistry::getPassRegistry());
61 bool hasNumUsesBelowThresGA(SDNode *N) const;
63 SDNode *Select(SDNode *N) override;
65 // Complex Pattern Selectors.
66 inline bool foldGlobalAddress(SDValue &N, SDValue &R);
67 inline bool foldGlobalAddressGP(SDValue &N, SDValue &R);
68 bool foldGlobalAddressImpl(SDValue &N, SDValue &R, bool ShouldLookForGP);
69 bool SelectADDRri(SDValue& N, SDValue &R1, SDValue &R2);
70 bool SelectADDRriS11_0(SDValue& N, SDValue &R1, SDValue &R2);
71 bool SelectADDRriS11_1(SDValue& N, SDValue &R1, SDValue &R2);
72 bool SelectADDRriS11_2(SDValue& N, SDValue &R1, SDValue &R2);
73 bool SelectMEMriS11_2(SDValue& Addr, SDValue &Base, SDValue &Offset);
74 bool SelectADDRriS11_3(SDValue& N, SDValue &R1, SDValue &R2);
75 bool SelectADDRrr(SDValue &Addr, SDValue &Base, SDValue &Offset);
76 bool SelectADDRriU6_0(SDValue& N, SDValue &R1, SDValue &R2);
77 bool SelectADDRriU6_1(SDValue& N, SDValue &R1, SDValue &R2);
78 bool SelectADDRriU6_2(SDValue& N, SDValue &R1, SDValue &R2);
80 // Complex Pattern Selectors.
81 inline bool SelectAddrGA(SDValue &N, SDValue &R);
82 inline bool SelectAddrGP(SDValue &N, SDValue &R);
83 bool SelectGlobalAddress(SDValue &N, SDValue &R, bool UseGP);
84 bool SelectAddrFI(SDValue &N, SDValue &R);
86 const char *getPassName() const override {
87 return "Hexagon DAG->DAG Pattern Instruction Selection";
90 bool runOnMachineFunction(MachineFunction &MF) override {
91 Subtarget = &MF.getSubtarget<HexagonSubtarget>();
92 return SelectionDAGISel::runOnMachineFunction(MF);
95 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
96 /// inline asm expressions.
97 bool SelectInlineAsmMemoryOperand(const SDValue &Op,
99 std::vector<SDValue> &OutOps) override;
100 bool SelectAddr(SDNode *Op, SDValue Addr, SDValue &Base, SDValue &Offset);
102 SDNode *SelectLoad(SDNode *N);
103 SDNode *SelectBaseOffsetLoad(LoadSDNode *LD, SDLoc dl);
104 SDNode *SelectIndexedLoad(LoadSDNode *LD, SDLoc dl);
105 SDNode *SelectIndexedLoadZeroExtend64(LoadSDNode *LD, unsigned Opcode,
107 SDNode *SelectIndexedLoadSignExtend64(LoadSDNode *LD, unsigned Opcode,
109 SDNode *SelectBaseOffsetStore(StoreSDNode *ST, SDLoc dl);
110 SDNode *SelectIndexedStore(StoreSDNode *ST, SDLoc dl);
111 SDNode *SelectStore(SDNode *N);
112 SDNode *SelectSHL(SDNode *N);
113 SDNode *SelectSelect(SDNode *N);
114 SDNode *SelectTruncate(SDNode *N);
115 SDNode *SelectMul(SDNode *N);
116 SDNode *SelectZeroExtend(SDNode *N);
117 SDNode *SelectIntrinsicWOChain(SDNode *N);
118 SDNode *SelectIntrinsicWChain(SDNode *N);
119 SDNode *SelectConstant(SDNode *N);
120 SDNode *SelectConstantFP(SDNode *N);
121 SDNode *SelectAdd(SDNode *N);
122 bool isConstExtProfitable(SDNode *N) const;
124 // XformMskToBitPosU5Imm - Returns the bit position which
125 // the single bit 32 bit mask represents.
126 // Used in Clr and Set bit immediate memops.
127 SDValue XformMskToBitPosU5Imm(uint32_t Imm) {
129 bitPos = Log2_32(Imm);
130 assert(bitPos >= 0 && bitPos < 32 &&
131 "Constant out of range for 32 BitPos Memops");
132 return CurDAG->getTargetConstant(bitPos, MVT::i32);
135 // XformMskToBitPosU4Imm - Returns the bit position which the single bit 16 bit
136 // mask represents. Used in Clr and Set bit immediate memops.
137 SDValue XformMskToBitPosU4Imm(uint16_t Imm) {
138 return XformMskToBitPosU5Imm(Imm);
141 // XformMskToBitPosU3Imm - Returns the bit position which the single bit 8 bit
142 // mask represents. Used in Clr and Set bit immediate memops.
143 SDValue XformMskToBitPosU3Imm(uint8_t Imm) {
144 return XformMskToBitPosU5Imm(Imm);
147 // Return true if there is exactly one bit set in V, i.e., if V is one of the
148 // following integers: 2^0, 2^1, ..., 2^31.
149 bool ImmIsSingleBit(uint32_t v) const {
150 return isPowerOf2_32(v);
153 // XformM5ToU5Imm - Return a target constant with the specified value, of type
154 // i32 where the negative literal is transformed into a positive literal for
156 inline SDValue XformM5ToU5Imm(signed Imm) {
157 assert( (Imm >= -31 && Imm <= -1) && "Constant out of range for Memops");
158 return CurDAG->getTargetConstant( - Imm, MVT::i32);
162 // XformU7ToU7M1Imm - Return a target constant decremented by 1, in range
163 // [1..128], used in cmpb.gtu instructions.
164 inline SDValue XformU7ToU7M1Imm(signed Imm) {
165 assert((Imm >= 1 && Imm <= 128) && "Constant out of range for cmpb op");
166 return CurDAG->getTargetConstant(Imm - 1, MVT::i8);
169 // XformS8ToS8M1Imm - Return a target constant decremented by 1.
170 inline SDValue XformSToSM1Imm(signed Imm) {
171 return CurDAG->getTargetConstant(Imm - 1, MVT::i32);
174 // XformU8ToU8M1Imm - Return a target constant decremented by 1.
175 inline SDValue XformUToUM1Imm(unsigned Imm) {
176 assert((Imm >= 1) && "Cannot decrement unsigned int less than 1");
177 return CurDAG->getTargetConstant(Imm - 1, MVT::i32);
180 // XformSToSM2Imm - Return a target constant decremented by 2.
181 inline SDValue XformSToSM2Imm(unsigned Imm) {
182 return CurDAG->getTargetConstant(Imm - 2, MVT::i32);
185 // XformSToSM3Imm - Return a target constant decremented by 3.
186 inline SDValue XformSToSM3Imm(unsigned Imm) {
187 return CurDAG->getTargetConstant(Imm - 3, MVT::i32);
190 // Include the pieces autogenerated from the target description.
191 #include "HexagonGenDAGISel.inc"
194 bool isValueExtension(SDValue const &Val, unsigned FromBits, SDValue &Src);
196 } // end anonymous namespace
199 /// createHexagonISelDag - This pass converts a legalized DAG into a
200 /// Hexagon-specific DAG, ready for instruction scheduling.
202 FunctionPass *llvm::createHexagonISelDag(HexagonTargetMachine &TM,
203 CodeGenOpt::Level OptLevel) {
204 return new HexagonDAGToDAGISel(TM, OptLevel);
207 static void initializePassOnce(PassRegistry &Registry) {
208 const char *Name = "Hexagon DAG->DAG Pattern Instruction Selection";
209 PassInfo *PI = new PassInfo(Name, "hexagon-isel",
210 &SelectionDAGISel::ID, nullptr, false, false);
211 Registry.registerPass(*PI, true);
214 void llvm::initializeHexagonDAGToDAGISelPass(PassRegistry &Registry) {
215 CALL_ONCE_INITIALIZATION(initializePassOnce)
219 static bool IsS11_0_Offset(SDNode * S) {
220 ConstantSDNode *N = cast<ConstantSDNode>(S);
222 // immS16 predicate - True if the immediate fits in a 16-bit sign extended
224 int64_t v = (int64_t)N->getSExtValue();
229 static bool IsS11_1_Offset(SDNode * S) {
230 ConstantSDNode *N = cast<ConstantSDNode>(S);
232 // immS16 predicate - True if the immediate fits in a 16-bit sign extended
234 int64_t v = (int64_t)N->getSExtValue();
235 return isShiftedInt<11,1>(v);
239 static bool IsS11_2_Offset(SDNode * S) {
240 ConstantSDNode *N = cast<ConstantSDNode>(S);
242 // immS16 predicate - True if the immediate fits in a 16-bit sign extended
244 int64_t v = (int64_t)N->getSExtValue();
245 return isShiftedInt<11,2>(v);
249 static bool IsS11_3_Offset(SDNode * S) {
250 ConstantSDNode *N = cast<ConstantSDNode>(S);
252 // immS16 predicate - True if the immediate fits in a 16-bit sign extended
254 int64_t v = (int64_t)N->getSExtValue();
255 return isShiftedInt<11,3>(v);
259 static bool IsU6_0_Offset(SDNode * S) {
260 ConstantSDNode *N = cast<ConstantSDNode>(S);
262 // u6 predicate - True if the immediate fits in a 6-bit unsigned extended
264 int64_t v = (int64_t)N->getSExtValue();
269 static bool IsU6_1_Offset(SDNode * S) {
270 ConstantSDNode *N = cast<ConstantSDNode>(S);
272 // u6 predicate - True if the immediate fits in a 6-bit unsigned extended
274 int64_t v = (int64_t)N->getSExtValue();
275 return isShiftedUInt<6,1>(v);
279 static bool IsU6_2_Offset(SDNode * S) {
280 ConstantSDNode *N = cast<ConstantSDNode>(S);
282 // u6 predicate - True if the immediate fits in a 6-bit unsigned extended
284 int64_t v = (int64_t)N->getSExtValue();
285 return isShiftedUInt<6,2>(v);
289 // Intrinsics that return a a predicate.
290 static unsigned doesIntrinsicReturnPredicate(unsigned ID)
295 case Intrinsic::hexagon_C2_cmpeq:
296 case Intrinsic::hexagon_C2_cmpgt:
297 case Intrinsic::hexagon_C2_cmpgtu:
298 case Intrinsic::hexagon_C2_cmpgtup:
299 case Intrinsic::hexagon_C2_cmpgtp:
300 case Intrinsic::hexagon_C2_cmpeqp:
301 case Intrinsic::hexagon_C2_bitsset:
302 case Intrinsic::hexagon_C2_bitsclr:
303 case Intrinsic::hexagon_C2_cmpeqi:
304 case Intrinsic::hexagon_C2_cmpgti:
305 case Intrinsic::hexagon_C2_cmpgtui:
306 case Intrinsic::hexagon_C2_cmpgei:
307 case Intrinsic::hexagon_C2_cmpgeui:
308 case Intrinsic::hexagon_C2_cmplt:
309 case Intrinsic::hexagon_C2_cmpltu:
310 case Intrinsic::hexagon_C2_bitsclri:
311 case Intrinsic::hexagon_C2_and:
312 case Intrinsic::hexagon_C2_or:
313 case Intrinsic::hexagon_C2_xor:
314 case Intrinsic::hexagon_C2_andn:
315 case Intrinsic::hexagon_C2_not:
316 case Intrinsic::hexagon_C2_orn:
317 case Intrinsic::hexagon_C2_pxfer_map:
318 case Intrinsic::hexagon_C2_any8:
319 case Intrinsic::hexagon_C2_all8:
320 case Intrinsic::hexagon_A2_vcmpbeq:
321 case Intrinsic::hexagon_A2_vcmpbgtu:
322 case Intrinsic::hexagon_A2_vcmpheq:
323 case Intrinsic::hexagon_A2_vcmphgt:
324 case Intrinsic::hexagon_A2_vcmphgtu:
325 case Intrinsic::hexagon_A2_vcmpweq:
326 case Intrinsic::hexagon_A2_vcmpwgt:
327 case Intrinsic::hexagon_A2_vcmpwgtu:
328 case Intrinsic::hexagon_C2_tfrrp:
329 case Intrinsic::hexagon_S2_tstbit_i:
330 case Intrinsic::hexagon_S2_tstbit_r:
335 static bool OffsetFitsS11(EVT MemType, int64_t Offset) {
336 if (MemType == MVT::i64 && isShiftedInt<11,3>(Offset)) {
339 if (MemType == MVT::i32 && isShiftedInt<11,2>(Offset)) {
342 if (MemType == MVT::i16 && isShiftedInt<11,1>(Offset)) {
345 if (MemType == MVT::i8 && isInt<11>(Offset)) {
353 // Try to lower loads of GlobalAdresses into base+offset loads. Custom
354 // lowering for GlobalAddress nodes has already turned it into a
357 SDNode *HexagonDAGToDAGISel::SelectBaseOffsetLoad(LoadSDNode *LD, SDLoc dl) {
358 SDValue Chain = LD->getChain();
359 SDNode* Const32 = LD->getBasePtr().getNode();
362 if (Const32->getOpcode() == HexagonISD::CONST32 &&
363 ISD::isNormalLoad(LD)) {
364 SDValue Base = Const32->getOperand(0);
365 EVT LoadedVT = LD->getMemoryVT();
366 int64_t Offset = cast<GlobalAddressSDNode>(Base)->getOffset();
367 if (Offset != 0 && OffsetFitsS11(LoadedVT, Offset)) {
368 MVT PointerTy = getTargetLowering()->getPointerTy();
369 const GlobalValue* GV =
370 cast<GlobalAddressSDNode>(Base)->getGlobal();
372 CurDAG->getTargetGlobalAddress(GV, dl, PointerTy, 0);
373 SDNode* NewBase = CurDAG->getMachineNode(Hexagon::CONST32_set,
376 // Figure out base + offset opcode
377 if (LoadedVT == MVT::i64) Opcode = Hexagon::L2_loadrd_io;
378 else if (LoadedVT == MVT::i32) Opcode = Hexagon::L2_loadri_io;
379 else if (LoadedVT == MVT::i16) Opcode = Hexagon::L2_loadrh_io;
380 else if (LoadedVT == MVT::i8) Opcode = Hexagon::L2_loadrb_io;
381 else llvm_unreachable("unknown memory type");
383 // Build indexed load.
384 SDValue TargetConstOff = CurDAG->getTargetConstant(Offset, PointerTy);
385 SDNode* Result = CurDAG->getMachineNode(Opcode, dl,
391 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
392 MemOp[0] = LD->getMemOperand();
393 cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1);
394 ReplaceUses(LD, Result);
399 return SelectCode(LD);
403 SDNode *HexagonDAGToDAGISel::SelectIndexedLoadSignExtend64(LoadSDNode *LD,
407 SDValue Chain = LD->getChain();
408 EVT LoadedVT = LD->getMemoryVT();
409 SDValue Base = LD->getBasePtr();
410 SDValue Offset = LD->getOffset();
411 SDNode *OffsetNode = Offset.getNode();
412 int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
413 SDValue N1 = LD->getOperand(1);
417 if (SelectADDRriS11_2(N1, CPTmpN1_0, CPTmpN1_1) &&
418 N1.getNode()->getValueType(0) == MVT::i32) {
419 const HexagonInstrInfo *TII = Subtarget->getInstrInfo();
420 if (TII->isValidAutoIncImm(LoadedVT, Val)) {
421 SDValue TargetConst = CurDAG->getTargetConstant(Val, MVT::i32);
422 SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::i32,
423 MVT::Other, Base, TargetConst,
425 SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_sxtw, dl, MVT::i64,
426 SDValue(Result_1, 0));
427 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
428 MemOp[0] = LD->getMemOperand();
429 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
430 const SDValue Froms[] = { SDValue(LD, 0),
434 const SDValue Tos[] = { SDValue(Result_2, 0),
435 SDValue(Result_1, 1),
438 ReplaceUses(Froms, Tos, 3);
441 SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
442 SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
443 SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
444 MVT::Other, Base, TargetConst0,
446 SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_sxtw, dl,
447 MVT::i64, SDValue(Result_1, 0));
448 SDNode* Result_3 = CurDAG->getMachineNode(Hexagon::A2_addi, dl,
449 MVT::i32, Base, TargetConstVal,
450 SDValue(Result_1, 1));
451 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
452 MemOp[0] = LD->getMemOperand();
453 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
454 const SDValue Froms[] = { SDValue(LD, 0),
458 const SDValue Tos[] = { SDValue(Result_2, 0),
459 SDValue(Result_3, 0),
462 ReplaceUses(Froms, Tos, 3);
465 return SelectCode(LD);
469 SDNode *HexagonDAGToDAGISel::SelectIndexedLoadZeroExtend64(LoadSDNode *LD,
473 SDValue Chain = LD->getChain();
474 EVT LoadedVT = LD->getMemoryVT();
475 SDValue Base = LD->getBasePtr();
476 SDValue Offset = LD->getOffset();
477 SDNode *OffsetNode = Offset.getNode();
478 int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
479 SDValue N1 = LD->getOperand(1);
483 if (SelectADDRriS11_2(N1, CPTmpN1_0, CPTmpN1_1) &&
484 N1.getNode()->getValueType(0) == MVT::i32) {
485 const HexagonInstrInfo *TII = Subtarget->getInstrInfo();
486 if (TII->isValidAutoIncImm(LoadedVT, Val)) {
487 SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
488 SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
489 SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
490 MVT::i32, MVT::Other, Base,
491 TargetConstVal, Chain);
492 SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_tfrsi, dl, MVT::i32,
494 SDNode *Result_3 = CurDAG->getMachineNode(Hexagon::A2_combinew, dl,
495 MVT::i64, MVT::Other,
497 SDValue(Result_1,0));
498 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
499 MemOp[0] = LD->getMemOperand();
500 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
501 const SDValue Froms[] = { SDValue(LD, 0),
505 const SDValue Tos[] = { SDValue(Result_3, 0),
506 SDValue(Result_1, 1),
509 ReplaceUses(Froms, Tos, 3);
513 // Generate an indirect load.
514 SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
515 SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
516 SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
518 Base, TargetConst0, Chain);
519 SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_tfrsi, dl, MVT::i32,
521 SDNode *Result_3 = CurDAG->getMachineNode(Hexagon::A2_combinew, dl,
522 MVT::i64, MVT::Other,
524 SDValue(Result_1,0));
525 // Add offset to base.
526 SDNode* Result_4 = CurDAG->getMachineNode(Hexagon::A2_addi, dl, MVT::i32,
527 Base, TargetConstVal,
528 SDValue(Result_1, 1));
529 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
530 MemOp[0] = LD->getMemOperand();
531 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
532 const SDValue Froms[] = { SDValue(LD, 0),
536 const SDValue Tos[] = { SDValue(Result_3, 0), // Load value.
537 SDValue(Result_4, 0), // New address.
540 ReplaceUses(Froms, Tos, 3);
544 return SelectCode(LD);
548 SDNode *HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, SDLoc dl) {
549 SDValue Chain = LD->getChain();
550 SDValue Base = LD->getBasePtr();
551 SDValue Offset = LD->getOffset();
552 SDNode *OffsetNode = Offset.getNode();
553 // Get the constant value.
554 int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
555 EVT LoadedVT = LD->getMemoryVT();
558 // Check for zero ext loads.
559 bool zextval = (LD->getExtensionType() == ISD::ZEXTLOAD);
561 // Figure out the opcode.
562 const HexagonInstrInfo *TII = Subtarget->getInstrInfo();
563 if (LoadedVT == MVT::i64) {
564 if (TII->isValidAutoIncImm(LoadedVT, Val))
565 Opcode = Hexagon::L2_loadrd_pi;
567 Opcode = Hexagon::L2_loadrd_io;
568 } else if (LoadedVT == MVT::i32) {
569 if (TII->isValidAutoIncImm(LoadedVT, Val))
570 Opcode = Hexagon::L2_loadri_pi;
572 Opcode = Hexagon::L2_loadri_io;
573 } else if (LoadedVT == MVT::i16) {
574 if (TII->isValidAutoIncImm(LoadedVT, Val))
575 Opcode = zextval ? Hexagon::L2_loadruh_pi : Hexagon::L2_loadrh_pi;
577 Opcode = zextval ? Hexagon::L2_loadruh_io : Hexagon::L2_loadrh_io;
578 } else if (LoadedVT == MVT::i8) {
579 if (TII->isValidAutoIncImm(LoadedVT, Val))
580 Opcode = zextval ? Hexagon::L2_loadrub_pi : Hexagon::L2_loadrb_pi;
582 Opcode = zextval ? Hexagon::L2_loadrub_io : Hexagon::L2_loadrb_io;
584 llvm_unreachable("unknown memory type");
586 // For zero ext i64 loads, we need to add combine instructions.
587 if (LD->getValueType(0) == MVT::i64 &&
588 LD->getExtensionType() == ISD::ZEXTLOAD) {
589 return SelectIndexedLoadZeroExtend64(LD, Opcode, dl);
591 if (LD->getValueType(0) == MVT::i64 &&
592 LD->getExtensionType() == ISD::SEXTLOAD) {
593 // Handle sign ext i64 loads.
594 return SelectIndexedLoadSignExtend64(LD, Opcode, dl);
596 if (TII->isValidAutoIncImm(LoadedVT, Val)) {
597 SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
598 SDNode* Result = CurDAG->getMachineNode(Opcode, dl,
600 MVT::i32, MVT::Other, Base,
601 TargetConstVal, Chain);
602 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
603 MemOp[0] = LD->getMemOperand();
604 cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1);
605 const SDValue Froms[] = { SDValue(LD, 0),
609 const SDValue Tos[] = { SDValue(Result, 0),
613 ReplaceUses(Froms, Tos, 3);
616 SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
617 SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
618 SDNode* Result_1 = CurDAG->getMachineNode(Opcode, dl,
620 MVT::Other, Base, TargetConst0,
622 SDNode* Result_2 = CurDAG->getMachineNode(Hexagon::A2_addi, dl, MVT::i32,
623 Base, TargetConstVal,
624 SDValue(Result_1, 1));
625 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
626 MemOp[0] = LD->getMemOperand();
627 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
628 const SDValue Froms[] = { SDValue(LD, 0),
632 const SDValue Tos[] = { SDValue(Result_1, 0),
633 SDValue(Result_2, 0),
636 ReplaceUses(Froms, Tos, 3);
642 SDNode *HexagonDAGToDAGISel::SelectLoad(SDNode *N) {
645 LoadSDNode *LD = cast<LoadSDNode>(N);
646 ISD::MemIndexedMode AM = LD->getAddressingMode();
648 // Handle indexed loads.
649 if (AM != ISD::UNINDEXED) {
650 result = SelectIndexedLoad(LD, dl);
652 result = SelectBaseOffsetLoad(LD, dl);
659 SDNode *HexagonDAGToDAGISel::SelectIndexedStore(StoreSDNode *ST, SDLoc dl) {
660 SDValue Chain = ST->getChain();
661 SDValue Base = ST->getBasePtr();
662 SDValue Offset = ST->getOffset();
663 SDValue Value = ST->getValue();
664 SDNode *OffsetNode = Offset.getNode();
665 // Get the constant value.
666 int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
667 EVT StoredVT = ST->getMemoryVT();
669 // Offset value must be within representable range
670 // and must have correct alignment properties.
671 const HexagonInstrInfo *TII = Subtarget->getInstrInfo();
672 if (TII->isValidAutoIncImm(StoredVT, Val)) {
673 SDValue Ops[] = {Base, CurDAG->getTargetConstant(Val, MVT::i32), Value,
677 // Figure out the post inc version of opcode.
678 if (StoredVT == MVT::i64) Opcode = Hexagon::S2_storerd_pi;
679 else if (StoredVT == MVT::i32) Opcode = Hexagon::S2_storeri_pi;
680 else if (StoredVT == MVT::i16) Opcode = Hexagon::S2_storerh_pi;
681 else if (StoredVT == MVT::i8) Opcode = Hexagon::S2_storerb_pi;
682 else llvm_unreachable("unknown memory type");
684 // Build post increment store.
685 SDNode* Result = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
687 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
688 MemOp[0] = ST->getMemOperand();
689 cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1);
691 ReplaceUses(ST, Result);
692 ReplaceUses(SDValue(ST,1), SDValue(Result,1));
696 // Note: Order of operands matches the def of instruction:
697 // def STrid : STInst<(outs), (ins MEMri:$addr, DoubleRegs:$src1), ...
698 // and it differs for POST_ST* for instance.
699 SDValue Ops[] = { Base, CurDAG->getTargetConstant(0, MVT::i32), Value,
703 // Figure out the opcode.
704 if (StoredVT == MVT::i64) Opcode = Hexagon::S2_storerd_io;
705 else if (StoredVT == MVT::i32) Opcode = Hexagon::S2_storeri_io;
706 else if (StoredVT == MVT::i16) Opcode = Hexagon::S2_storerh_io;
707 else if (StoredVT == MVT::i8) Opcode = Hexagon::S2_storerb_io;
708 else llvm_unreachable("unknown memory type");
710 // Build regular store.
711 SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
712 SDNode* Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
713 // Build splitted incriment instruction.
714 SDNode* Result_2 = CurDAG->getMachineNode(Hexagon::A2_addi, dl, MVT::i32,
717 SDValue(Result_1, 0));
718 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
719 MemOp[0] = ST->getMemOperand();
720 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
722 ReplaceUses(SDValue(ST,0), SDValue(Result_2,0));
723 ReplaceUses(SDValue(ST,1), SDValue(Result_1,0));
728 SDNode *HexagonDAGToDAGISel::SelectBaseOffsetStore(StoreSDNode *ST,
730 SDValue Chain = ST->getChain();
731 SDNode* Const32 = ST->getBasePtr().getNode();
732 SDValue Value = ST->getValue();
735 // Try to lower stores of GlobalAdresses into indexed stores. Custom
736 // lowering for GlobalAddress nodes has already turned it into a
737 // CONST32. Avoid truncating stores for the moment. Post-inc stores
738 // do the same. Don't think there's a reason for it, so will file a
740 if ((Const32->getOpcode() == HexagonISD::CONST32) &&
741 !(Value.getValueType() == MVT::i64 && ST->isTruncatingStore())) {
742 SDValue Base = Const32->getOperand(0);
743 if (Base.getOpcode() == ISD::TargetGlobalAddress) {
744 EVT StoredVT = ST->getMemoryVT();
745 int64_t Offset = cast<GlobalAddressSDNode>(Base)->getOffset();
746 if (Offset != 0 && OffsetFitsS11(StoredVT, Offset)) {
747 MVT PointerTy = getTargetLowering()->getPointerTy();
748 const GlobalValue* GV =
749 cast<GlobalAddressSDNode>(Base)->getGlobal();
751 CurDAG->getTargetGlobalAddress(GV, dl, PointerTy, 0);
752 SDNode* NewBase = CurDAG->getMachineNode(Hexagon::CONST32_set,
756 // Figure out base + offset opcode
757 if (StoredVT == MVT::i64) Opcode = Hexagon::S2_storerd_io;
758 else if (StoredVT == MVT::i32) Opcode = Hexagon::S2_storeri_io;
759 else if (StoredVT == MVT::i16) Opcode = Hexagon::S2_storerh_io;
760 else if (StoredVT == MVT::i8) Opcode = Hexagon::S2_storerb_io;
761 else llvm_unreachable("unknown memory type");
763 SDValue Ops[] = {SDValue(NewBase,0),
764 CurDAG->getTargetConstant(Offset,PointerTy),
766 // build indexed store
767 SDNode* Result = CurDAG->getMachineNode(Opcode, dl,
769 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
770 MemOp[0] = ST->getMemOperand();
771 cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1);
772 ReplaceUses(ST, Result);
778 return SelectCode(ST);
782 SDNode *HexagonDAGToDAGISel::SelectStore(SDNode *N) {
784 StoreSDNode *ST = cast<StoreSDNode>(N);
785 ISD::MemIndexedMode AM = ST->getAddressingMode();
787 // Handle indexed stores.
788 if (AM != ISD::UNINDEXED) {
789 return SelectIndexedStore(ST, dl);
792 return SelectBaseOffsetStore(ST, dl);
795 SDNode *HexagonDAGToDAGISel::SelectMul(SDNode *N) {
799 // %conv.i = sext i32 %tmp1 to i64
800 // %conv2.i = sext i32 %add to i64
801 // %mul.i = mul nsw i64 %conv2.i, %conv.i
803 // --- match with the following ---
805 // %mul.i = mpy (%tmp1, %add)
808 if (N->getValueType(0) == MVT::i64) {
809 // Shifting a i64 signed multiply.
810 SDValue MulOp0 = N->getOperand(0);
811 SDValue MulOp1 = N->getOperand(1);
816 // Handle sign_extend and sextload.
817 if (MulOp0.getOpcode() == ISD::SIGN_EXTEND) {
818 SDValue Sext0 = MulOp0.getOperand(0);
819 if (Sext0.getNode()->getValueType(0) != MVT::i32) {
820 return SelectCode(N);
824 } else if (MulOp0.getOpcode() == ISD::LOAD) {
825 LoadSDNode *LD = cast<LoadSDNode>(MulOp0.getNode());
826 if (LD->getMemoryVT() != MVT::i32 ||
827 LD->getExtensionType() != ISD::SEXTLOAD ||
828 LD->getAddressingMode() != ISD::UNINDEXED) {
829 return SelectCode(N);
832 SDValue Chain = LD->getChain();
833 SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
834 OP0 = SDValue(CurDAG->getMachineNode(Hexagon::L2_loadri_io, dl, MVT::i32,
836 LD->getBasePtr(), TargetConst0,
839 return SelectCode(N);
842 // Same goes for the second operand.
843 if (MulOp1.getOpcode() == ISD::SIGN_EXTEND) {
844 SDValue Sext1 = MulOp1.getOperand(0);
845 if (Sext1.getNode()->getValueType(0) != MVT::i32) {
846 return SelectCode(N);
850 } else if (MulOp1.getOpcode() == ISD::LOAD) {
851 LoadSDNode *LD = cast<LoadSDNode>(MulOp1.getNode());
852 if (LD->getMemoryVT() != MVT::i32 ||
853 LD->getExtensionType() != ISD::SEXTLOAD ||
854 LD->getAddressingMode() != ISD::UNINDEXED) {
855 return SelectCode(N);
858 SDValue Chain = LD->getChain();
859 SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
860 OP1 = SDValue(CurDAG->getMachineNode(Hexagon::L2_loadri_io, dl, MVT::i32,
862 LD->getBasePtr(), TargetConst0,
865 return SelectCode(N);
868 // Generate a mpy instruction.
869 SDNode *Result = CurDAG->getMachineNode(Hexagon::M2_dpmpyss_s0, dl, MVT::i64,
871 ReplaceUses(N, Result);
875 return SelectCode(N);
879 SDNode *HexagonDAGToDAGISel::SelectSelect(SDNode *N) {
881 SDValue N0 = N->getOperand(0);
882 if (N0.getOpcode() == ISD::SETCC) {
883 SDValue N00 = N0.getOperand(0);
884 if (N00.getOpcode() == ISD::SIGN_EXTEND_INREG) {
885 SDValue N000 = N00.getOperand(0);
886 SDValue N001 = N00.getOperand(1);
887 if (cast<VTSDNode>(N001)->getVT() == MVT::i16) {
888 SDValue N01 = N0.getOperand(1);
889 SDValue N02 = N0.getOperand(2);
891 // Pattern: (select:i32 (setcc:i1 (sext_inreg:i32 IntRegs:i32:$src2,
892 // i16:Other),IntRegs:i32:$src1, SETLT:Other),IntRegs:i32:$src1,
893 // IntRegs:i32:$src2)
894 // Emits: (MAXh_rr:i32 IntRegs:i32:$src1, IntRegs:i32:$src2)
895 // Pattern complexity = 9 cost = 1 size = 0.
896 if (cast<CondCodeSDNode>(N02)->get() == ISD::SETLT) {
897 SDValue N1 = N->getOperand(1);
899 SDValue N2 = N->getOperand(2);
901 N0.getNode()->getValueType(N0.getResNo()) == MVT::i1 &&
902 N00.getNode()->getValueType(N00.getResNo()) == MVT::i32) {
903 SDNode *SextNode = CurDAG->getMachineNode(Hexagon::A2_sxth, dl,
905 SDNode *Result = CurDAG->getMachineNode(Hexagon::A2_max, dl,
907 SDValue(SextNode, 0),
909 ReplaceUses(N, Result);
915 // Pattern: (select:i32 (setcc:i1 (sext_inreg:i32 IntRegs:i32:$src2,
916 // i16:Other), IntRegs:i32:$src1, SETGT:Other), IntRegs:i32:$src1,
917 // IntRegs:i32:$src2)
918 // Emits: (MINh_rr:i32 IntRegs:i32:$src1, IntRegs:i32:$src2)
919 // Pattern complexity = 9 cost = 1 size = 0.
920 if (cast<CondCodeSDNode>(N02)->get() == ISD::SETGT) {
921 SDValue N1 = N->getOperand(1);
923 SDValue N2 = N->getOperand(2);
925 N0.getNode()->getValueType(N0.getResNo()) == MVT::i1 &&
926 N00.getNode()->getValueType(N00.getResNo()) == MVT::i32) {
927 SDNode *SextNode = CurDAG->getMachineNode(Hexagon::A2_sxth, dl,
929 SDNode *Result = CurDAG->getMachineNode(Hexagon::A2_min, dl,
931 SDValue(SextNode, 0),
933 ReplaceUses(N, Result);
942 return SelectCode(N);
946 SDNode *HexagonDAGToDAGISel::SelectTruncate(SDNode *N) {
948 SDValue Shift = N->getOperand(0);
951 // %conv.i = sext i32 %tmp1 to i64
952 // %conv2.i = sext i32 %add to i64
953 // %mul.i = mul nsw i64 %conv2.i, %conv.i
954 // %shr5.i = lshr i64 %mul.i, 32
955 // %conv3.i = trunc i64 %shr5.i to i32
957 // --- match with the following ---
959 // %conv3.i = mpy (%tmp1, %add)
962 if (N->getValueType(0) == MVT::i32) {
964 if (Shift.getNode()->getValueType(0) == MVT::i64) {
965 // Trunc child is logical shift right.
966 if (Shift.getOpcode() != ISD::SRL) {
967 return SelectCode(N);
970 SDValue ShiftOp0 = Shift.getOperand(0);
971 SDValue ShiftOp1 = Shift.getOperand(1);
974 if (ShiftOp1.getOpcode() != ISD::Constant) {
975 return SelectCode(N);
979 cast<ConstantSDNode>(ShiftOp1.getNode())->getSExtValue();
980 if (ShiftConst != 32) {
981 return SelectCode(N);
984 // Shifting a i64 signed multiply
985 SDValue Mul = ShiftOp0;
986 if (Mul.getOpcode() != ISD::MUL) {
987 return SelectCode(N);
990 SDValue MulOp0 = Mul.getOperand(0);
991 SDValue MulOp1 = Mul.getOperand(1);
996 // Handle sign_extend and sextload
997 if (MulOp0.getOpcode() == ISD::SIGN_EXTEND) {
998 SDValue Sext0 = MulOp0.getOperand(0);
999 if (Sext0.getNode()->getValueType(0) != MVT::i32) {
1000 return SelectCode(N);
1004 } else if (MulOp0.getOpcode() == ISD::LOAD) {
1005 LoadSDNode *LD = cast<LoadSDNode>(MulOp0.getNode());
1006 if (LD->getMemoryVT() != MVT::i32 ||
1007 LD->getExtensionType() != ISD::SEXTLOAD ||
1008 LD->getAddressingMode() != ISD::UNINDEXED) {
1009 return SelectCode(N);
1012 SDValue Chain = LD->getChain();
1013 SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
1014 OP0 = SDValue(CurDAG->getMachineNode(Hexagon::L2_loadri_io, dl, MVT::i32,
1017 TargetConst0, Chain), 0);
1019 return SelectCode(N);
1022 // Same goes for the second operand.
1023 if (MulOp1.getOpcode() == ISD::SIGN_EXTEND) {
1024 SDValue Sext1 = MulOp1.getOperand(0);
1025 if (Sext1.getNode()->getValueType(0) != MVT::i32)
1026 return SelectCode(N);
1029 } else if (MulOp1.getOpcode() == ISD::LOAD) {
1030 LoadSDNode *LD = cast<LoadSDNode>(MulOp1.getNode());
1031 if (LD->getMemoryVT() != MVT::i32 ||
1032 LD->getExtensionType() != ISD::SEXTLOAD ||
1033 LD->getAddressingMode() != ISD::UNINDEXED) {
1034 return SelectCode(N);
1037 SDValue Chain = LD->getChain();
1038 SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
1039 OP1 = SDValue(CurDAG->getMachineNode(Hexagon::L2_loadri_io, dl, MVT::i32,
1042 TargetConst0, Chain), 0);
1044 return SelectCode(N);
1047 // Generate a mpy instruction.
1048 SDNode *Result = CurDAG->getMachineNode(Hexagon::M2_mpy_up, dl, MVT::i32,
1050 ReplaceUses(N, Result);
1055 return SelectCode(N);
1059 SDNode *HexagonDAGToDAGISel::SelectSHL(SDNode *N) {
1061 if (N->getValueType(0) == MVT::i32) {
1062 SDValue Shl_0 = N->getOperand(0);
1063 SDValue Shl_1 = N->getOperand(1);
1065 if (Shl_1.getOpcode() == ISD::Constant) {
1066 if (Shl_0.getOpcode() == ISD::MUL) {
1067 SDValue Mul_0 = Shl_0.getOperand(0); // Val
1068 SDValue Mul_1 = Shl_0.getOperand(1); // Const
1069 // RHS of mul is const.
1070 if (Mul_1.getOpcode() == ISD::Constant) {
1072 cast<ConstantSDNode>(Shl_1.getNode())->getSExtValue();
1074 cast<ConstantSDNode>(Mul_1.getNode())->getSExtValue();
1075 int32_t ValConst = MulConst << ShlConst;
1076 SDValue Val = CurDAG->getTargetConstant(ValConst,
1078 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val.getNode()))
1079 if (isInt<9>(CN->getSExtValue())) {
1081 CurDAG->getMachineNode(Hexagon::M2_mpysmi, dl,
1082 MVT::i32, Mul_0, Val);
1083 ReplaceUses(N, Result);
1088 } else if (Shl_0.getOpcode() == ISD::SUB) {
1089 SDValue Sub_0 = Shl_0.getOperand(0); // Const 0
1090 SDValue Sub_1 = Shl_0.getOperand(1); // Val
1091 if (Sub_0.getOpcode() == ISD::Constant) {
1093 cast<ConstantSDNode>(Sub_0.getNode())->getSExtValue();
1094 if (SubConst == 0) {
1095 if (Sub_1.getOpcode() == ISD::SHL) {
1096 SDValue Shl2_0 = Sub_1.getOperand(0); // Val
1097 SDValue Shl2_1 = Sub_1.getOperand(1); // Const
1098 if (Shl2_1.getOpcode() == ISD::Constant) {
1100 cast<ConstantSDNode>(Shl_1.getNode())->getSExtValue();
1102 cast<ConstantSDNode>(Shl2_1.getNode())->getSExtValue();
1103 int32_t ValConst = 1 << (ShlConst+Shl2Const);
1104 SDValue Val = CurDAG->getTargetConstant(-ValConst, MVT::i32);
1105 if (ConstantSDNode *CN =
1106 dyn_cast<ConstantSDNode>(Val.getNode()))
1107 if (isInt<9>(CN->getSExtValue())) {
1109 CurDAG->getMachineNode(Hexagon::M2_mpysmi, dl, MVT::i32,
1111 ReplaceUses(N, Result);
1121 return SelectCode(N);
1126 // If there is an zero_extend followed an intrinsic in DAG (this means - the
1127 // result of the intrinsic is predicate); convert the zero_extend to
1128 // transfer instruction.
1130 // Zero extend -> transfer is lowered here. Otherwise, zero_extend will be
1131 // converted into a MUX as predicate registers defined as 1 bit in the
1132 // compiler. Architecture defines them as 8-bit registers.
1133 // We want to preserve all the lower 8-bits and, not just 1 LSB bit.
1135 SDNode *HexagonDAGToDAGISel::SelectZeroExtend(SDNode *N) {
1137 SDNode *IsIntrinsic = N->getOperand(0).getNode();
1138 if ((IsIntrinsic->getOpcode() == ISD::INTRINSIC_WO_CHAIN)) {
1140 cast<ConstantSDNode>(IsIntrinsic->getOperand(0))->getZExtValue();
1141 if (doesIntrinsicReturnPredicate(ID)) {
1142 // Now we need to differentiate target data types.
1143 if (N->getValueType(0) == MVT::i64) {
1144 // Convert the zero_extend to Rs = Pd followed by COMBINE_rr(0,Rs).
1145 SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
1146 SDNode *Result_1 = CurDAG->getMachineNode(Hexagon::C2_tfrpr, dl,
1148 SDValue(IsIntrinsic, 0));
1149 SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_tfrsi, dl,
1152 SDNode *Result_3 = CurDAG->getMachineNode(Hexagon::A2_combinew, dl,
1153 MVT::i64, MVT::Other,
1154 SDValue(Result_2, 0),
1155 SDValue(Result_1, 0));
1156 ReplaceUses(N, Result_3);
1159 if (N->getValueType(0) == MVT::i32) {
1160 // Convert the zero_extend to Rs = Pd
1161 SDNode* RsPd = CurDAG->getMachineNode(Hexagon::C2_tfrpr, dl,
1163 SDValue(IsIntrinsic, 0));
1164 ReplaceUses(N, RsPd);
1167 llvm_unreachable("Unexpected value type");
1170 return SelectCode(N);
1174 // Checking for intrinsics which have predicate registers as operand(s)
1175 // and lowering to the actual intrinsic.
1177 SDNode *HexagonDAGToDAGISel::SelectIntrinsicWOChain(SDNode *N) {
1178 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
1181 case Intrinsic::hexagon_S2_vsplatrb:
1184 case Intrinsic::hexagon_S2_vsplatrh:
1188 return SelectCode(N);
1191 SDValue const &V = N->getOperand(1);
1193 if (isValueExtension(V, Bits, U)) {
1194 SDValue R = CurDAG->getNode(N->getOpcode(), SDLoc(N), N->getValueType(0),
1195 N->getOperand(0), U);
1196 return SelectCode(R.getNode());
1198 return SelectCode(N);
1202 // Map floating point constant values.
1204 SDNode *HexagonDAGToDAGISel::SelectConstantFP(SDNode *N) {
1206 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
1207 APFloat APF = CN->getValueAPF();
1208 if (N->getValueType(0) == MVT::f32) {
1209 return CurDAG->getMachineNode(Hexagon::TFRI_f, dl, MVT::f32,
1210 CurDAG->getTargetConstantFP(APF.convertToFloat(), MVT::f32));
1212 else if (N->getValueType(0) == MVT::f64) {
1213 return CurDAG->getMachineNode(Hexagon::CONST64_Float_Real, dl, MVT::f64,
1214 CurDAG->getTargetConstantFP(APF.convertToDouble(), MVT::f64));
1217 return SelectCode(N);
1222 // Map predicate true (encoded as -1 in LLVM) to a XOR.
1224 SDNode *HexagonDAGToDAGISel::SelectConstant(SDNode *N) {
1226 if (N->getValueType(0) == MVT::i1) {
1228 int32_t Val = cast<ConstantSDNode>(N)->getSExtValue();
1230 // Create the IntReg = 1 node.
1232 CurDAG->getMachineNode(Hexagon::A2_tfrsi, dl, MVT::i32,
1233 CurDAG->getTargetConstant(0, MVT::i32));
1236 SDNode* Pd = CurDAG->getMachineNode(Hexagon::C2_tfrrp, dl, MVT::i1,
1237 SDValue(IntRegTFR, 0));
1240 SDNode* NotPd = CurDAG->getMachineNode(Hexagon::C2_not, dl, MVT::i1,
1244 Result = CurDAG->getMachineNode(Hexagon::C2_xor, dl, MVT::i1,
1245 SDValue(Pd, 0), SDValue(NotPd, 0));
1247 // We have just built:
1249 // Pd = xor(not(Pd), Pd)
1251 ReplaceUses(N, Result);
1256 return SelectCode(N);
1261 // Map add followed by a asr -> asr +=.
1263 SDNode *HexagonDAGToDAGISel::SelectAdd(SDNode *N) {
1265 if (N->getValueType(0) != MVT::i32) {
1266 return SelectCode(N);
1268 // Identify nodes of the form: add(asr(...)).
1269 SDNode* Src1 = N->getOperand(0).getNode();
1270 if (Src1->getOpcode() != ISD::SRA || !Src1->hasOneUse()
1271 || Src1->getValueType(0) != MVT::i32) {
1272 return SelectCode(N);
1275 // Build Rd = Rd' + asr(Rs, Rt). The machine constraints will ensure that
1276 // Rd and Rd' are assigned to the same register
1277 SDNode* Result = CurDAG->getMachineNode(Hexagon::S2_asr_r_r_acc, dl, MVT::i32,
1279 Src1->getOperand(0),
1280 Src1->getOperand(1));
1281 ReplaceUses(N, Result);
1287 SDNode *HexagonDAGToDAGISel::Select(SDNode *N) {
1288 if (N->isMachineOpcode()) {
1290 return nullptr; // Already selected.
1294 switch (N->getOpcode()) {
1296 return SelectConstant(N);
1298 case ISD::ConstantFP:
1299 return SelectConstantFP(N);
1302 return SelectAdd(N);
1305 return SelectSHL(N);
1308 return SelectLoad(N);
1311 return SelectStore(N);
1314 return SelectSelect(N);
1317 return SelectTruncate(N);
1320 return SelectMul(N);
1322 case ISD::ZERO_EXTEND:
1323 return SelectZeroExtend(N);
1325 case ISD::INTRINSIC_WO_CHAIN:
1326 return SelectIntrinsicWOChain(N);
1329 return SelectCode(N);
1334 // Hexagon_TODO: Five functions for ADDRri?! Surely there must be a better way
1335 // to define these instructions.
1337 bool HexagonDAGToDAGISel::SelectADDRri(SDValue& Addr, SDValue &Base,
1339 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1340 Addr.getOpcode() == ISD::TargetGlobalAddress)
1341 return false; // Direct calls.
1343 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
1344 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1345 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1349 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1354 bool HexagonDAGToDAGISel::SelectADDRriS11_0(SDValue& Addr, SDValue &Base,
1356 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1357 Addr.getOpcode() == ISD::TargetGlobalAddress)
1358 return false; // Direct calls.
1360 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
1361 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1362 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1363 return (IsS11_0_Offset(Offset.getNode()));
1366 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1367 return (IsS11_0_Offset(Offset.getNode()));
1371 bool HexagonDAGToDAGISel::SelectADDRriS11_1(SDValue& Addr, SDValue &Base,
1373 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1374 Addr.getOpcode() == ISD::TargetGlobalAddress)
1375 return false; // Direct calls.
1377 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
1378 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1379 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1380 return (IsS11_1_Offset(Offset.getNode()));
1383 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1384 return (IsS11_1_Offset(Offset.getNode()));
1388 bool HexagonDAGToDAGISel::SelectADDRriS11_2(SDValue& Addr, SDValue &Base,
1390 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1391 Addr.getOpcode() == ISD::TargetGlobalAddress)
1392 return false; // Direct calls.
1394 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
1395 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1396 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1397 return (IsS11_2_Offset(Offset.getNode()));
1400 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1401 return (IsS11_2_Offset(Offset.getNode()));
1405 bool HexagonDAGToDAGISel::SelectADDRriU6_0(SDValue& Addr, SDValue &Base,
1407 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1408 Addr.getOpcode() == ISD::TargetGlobalAddress)
1409 return false; // Direct calls.
1411 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
1412 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1413 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1414 return (IsU6_0_Offset(Offset.getNode()));
1417 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1418 return (IsU6_0_Offset(Offset.getNode()));
1422 bool HexagonDAGToDAGISel::SelectADDRriU6_1(SDValue& Addr, SDValue &Base,
1424 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1425 Addr.getOpcode() == ISD::TargetGlobalAddress)
1426 return false; // Direct calls.
1428 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
1429 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1430 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1431 return (IsU6_1_Offset(Offset.getNode()));
1434 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1435 return (IsU6_1_Offset(Offset.getNode()));
1439 bool HexagonDAGToDAGISel::SelectADDRriU6_2(SDValue& Addr, SDValue &Base,
1441 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1442 Addr.getOpcode() == ISD::TargetGlobalAddress)
1443 return false; // Direct calls.
1445 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
1446 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1447 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1448 return (IsU6_2_Offset(Offset.getNode()));
1451 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1452 return (IsU6_2_Offset(Offset.getNode()));
1456 bool HexagonDAGToDAGISel::SelectMEMriS11_2(SDValue& Addr, SDValue &Base,
1459 if (Addr.getOpcode() != ISD::ADD) {
1460 return(SelectADDRriS11_2(Addr, Base, Offset));
1463 return SelectADDRriS11_2(Addr, Base, Offset);
1467 bool HexagonDAGToDAGISel::SelectADDRriS11_3(SDValue& Addr, SDValue &Base,
1469 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1470 Addr.getOpcode() == ISD::TargetGlobalAddress)
1471 return false; // Direct calls.
1473 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
1474 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1475 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1476 return (IsS11_3_Offset(Offset.getNode()));
1479 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1480 return (IsS11_3_Offset(Offset.getNode()));
1483 bool HexagonDAGToDAGISel::SelectADDRrr(SDValue &Addr, SDValue &R1,
1485 if (Addr.getOpcode() == ISD::FrameIndex) return false;
1486 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1487 Addr.getOpcode() == ISD::TargetGlobalAddress)
1488 return false; // Direct calls.
1490 if (Addr.getOpcode() == ISD::ADD) {
1491 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
1492 if (isInt<13>(CN->getSExtValue()))
1493 return false; // Let the reg+imm pattern catch this!
1494 R1 = Addr.getOperand(0);
1495 R2 = Addr.getOperand(1);
1505 // Handle generic address case. It is accessed from inlined asm =m constraints,
1506 // which could have any kind of pointer.
1507 bool HexagonDAGToDAGISel::SelectAddr(SDNode *Op, SDValue Addr,
1508 SDValue &Base, SDValue &Offset) {
1509 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1510 Addr.getOpcode() == ISD::TargetGlobalAddress)
1511 return false; // Direct calls.
1513 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
1514 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1515 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1519 if (Addr.getOpcode() == ISD::ADD) {
1520 Base = Addr.getOperand(0);
1521 Offset = Addr.getOperand(1);
1526 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1531 bool HexagonDAGToDAGISel::
1532 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
1533 std::vector<SDValue> &OutOps) {
1536 switch (ConstraintCode) {
1537 case 'o': // Offsetable.
1538 case 'v': // Not offsetable.
1539 default: return true;
1540 case 'm': // Memory.
1541 if (!SelectAddr(Op.getNode(), Op, Op0, Op1))
1546 OutOps.push_back(Op0);
1547 OutOps.push_back(Op1);
1551 bool HexagonDAGToDAGISel::isConstExtProfitable(SDNode *N) const {
1552 unsigned UseCount = 0;
1553 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1557 return (UseCount <= 1);
1561 //===--------------------------------------------------------------------===//
1562 // Return 'true' if use count of the global address is below threshold.
1563 //===--------------------------------------------------------------------===//
1564 bool HexagonDAGToDAGISel::hasNumUsesBelowThresGA(SDNode *N) const {
1565 assert(N->getOpcode() == ISD::TargetGlobalAddress &&
1566 "Expecting a target global address");
1568 // Always try to fold the address.
1569 if (TM.getOptLevel() == CodeGenOpt::Aggressive)
1572 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N);
1573 DenseMap<const GlobalValue *, unsigned>::const_iterator GI =
1574 GlobalAddressUseCountMap.find(GA->getGlobal());
1576 if (GI == GlobalAddressUseCountMap.end())
1579 return GI->second <= MaxNumOfUsesForConstExtenders;
1582 //===--------------------------------------------------------------------===//
1583 // Return true if the non-GP-relative global address can be folded.
1584 //===--------------------------------------------------------------------===//
1585 inline bool HexagonDAGToDAGISel::foldGlobalAddress(SDValue &N, SDValue &R) {
1586 return foldGlobalAddressImpl(N, R, false);
1589 //===--------------------------------------------------------------------===//
1590 // Return true if the GP-relative global address can be folded.
1591 //===--------------------------------------------------------------------===//
1592 inline bool HexagonDAGToDAGISel::foldGlobalAddressGP(SDValue &N, SDValue &R) {
1593 return foldGlobalAddressImpl(N, R, true);
1596 //===--------------------------------------------------------------------===//
1597 // Fold offset of the global address if number of uses are below threshold.
1598 //===--------------------------------------------------------------------===//
1599 bool HexagonDAGToDAGISel::foldGlobalAddressImpl(SDValue &N, SDValue &R,
1600 bool ShouldLookForGP) {
1601 if (N.getOpcode() == ISD::ADD) {
1602 SDValue N0 = N.getOperand(0);
1603 SDValue N1 = N.getOperand(1);
1604 if ((ShouldLookForGP && (N0.getOpcode() == HexagonISD::CONST32_GP)) ||
1605 (!ShouldLookForGP && (N0.getOpcode() == HexagonISD::CONST32))) {
1606 ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N1);
1607 GlobalAddressSDNode *GA =
1608 dyn_cast<GlobalAddressSDNode>(N0.getOperand(0));
1611 (GA->getOpcode() == ISD::TargetGlobalAddress)) {
1612 if ((N0.getOpcode() == HexagonISD::CONST32) &&
1613 !hasNumUsesBelowThresGA(GA))
1615 R = CurDAG->getTargetGlobalAddress(GA->getGlobal(),
1619 (uint64_t)Const->getSExtValue());
1627 bool HexagonDAGToDAGISel::SelectAddrFI(SDValue& N, SDValue &R) {
1628 if (N.getOpcode() != ISD::FrameIndex)
1630 FrameIndexSDNode *FX = cast<FrameIndexSDNode>(N);
1631 R = CurDAG->getTargetFrameIndex(FX->getIndex(), MVT::i32);
1635 inline bool HexagonDAGToDAGISel::SelectAddrGA(SDValue &N, SDValue &R) {
1636 return SelectGlobalAddress(N, R, false);
1639 inline bool HexagonDAGToDAGISel::SelectAddrGP(SDValue &N, SDValue &R) {
1640 return SelectGlobalAddress(N, R, true);
1643 bool HexagonDAGToDAGISel::SelectGlobalAddress(SDValue &N, SDValue &R,
1645 switch (N.getOpcode()) {
1647 SDValue N0 = N.getOperand(0);
1648 SDValue N1 = N.getOperand(1);
1649 unsigned GAOpc = N0.getOpcode();
1650 if (UseGP && GAOpc != HexagonISD::CONST32_GP)
1652 if (!UseGP && GAOpc != HexagonISD::CONST32)
1654 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N1)) {
1655 SDValue Addr = N0.getOperand(0);
1656 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Addr)) {
1657 if (GA->getOpcode() == ISD::TargetGlobalAddress) {
1658 uint64_t NewOff = GA->getOffset() + (uint64_t)Const->getSExtValue();
1659 R = CurDAG->getTargetGlobalAddress(GA->getGlobal(), SDLoc(Const),
1660 N.getValueType(), NewOff);
1667 case HexagonISD::CONST32:
1668 // The operand(0) of CONST32 is TargetGlobalAddress, which is what we
1669 // want in the instruction.
1671 R = N.getOperand(0);
1673 case HexagonISD::CONST32_GP:
1675 R = N.getOperand(0);
1684 bool HexagonDAGToDAGISel::isValueExtension(SDValue const &Val,
1685 unsigned FromBits, SDValue &Src) {
1686 unsigned Opc = Val.getOpcode();
1688 case ISD::SIGN_EXTEND:
1689 case ISD::ZERO_EXTEND:
1690 case ISD::ANY_EXTEND: {
1691 SDValue const &Op0 = Val.getOperand(0);
1692 EVT T = Op0.getValueType();
1693 if (T.isInteger() && T.getSizeInBits() == FromBits) {
1699 case ISD::SIGN_EXTEND_INREG:
1700 case ISD::AssertSext:
1701 case ISD::AssertZext:
1702 if (Val.getOperand(0).getValueType().isInteger()) {
1703 VTSDNode *T = cast<VTSDNode>(Val.getOperand(1));
1704 if (T->getVT().getSizeInBits() == FromBits) {
1705 Src = Val.getOperand(0);
1711 // Check if this is an AND with "FromBits" of lower bits set to 1.
1712 uint64_t FromMask = (1 << FromBits) - 1;
1713 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val.getOperand(0))) {
1714 if (C->getZExtValue() == FromMask) {
1715 Src = Val.getOperand(1);
1719 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val.getOperand(1))) {
1720 if (C->getZExtValue() == FromMask) {
1721 Src = Val.getOperand(0);
1729 // OR/XOR with the lower "FromBits" bits set to 0.
1730 uint64_t FromMask = (1 << FromBits) - 1;
1731 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val.getOperand(0))) {
1732 if ((C->getZExtValue() & FromMask) == 0) {
1733 Src = Val.getOperand(1);
1737 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val.getOperand(1))) {
1738 if ((C->getZExtValue() & FromMask) == 0) {
1739 Src = Val.getOperand(0);