1 //===-- HexagonISelDAGToDAG.cpp - A dag to dag inst selector for Hexagon --===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the Hexagon target.
12 //===----------------------------------------------------------------------===//
15 #include "HexagonISelLowering.h"
16 #include "HexagonTargetMachine.h"
17 #include "llvm/ADT/DenseMap.h"
18 #include "llvm/CodeGen/SelectionDAGISel.h"
19 #include "llvm/IR/Intrinsics.h"
20 #include "llvm/Support/CommandLine.h"
21 #include "llvm/Support/Compiler.h"
22 #include "llvm/Support/Debug.h"
25 #define DEBUG_TYPE "hexagon-isel"
29 MaxNumOfUsesForConstExtenders("ga-max-num-uses-for-constant-extenders",
30 cl::Hidden, cl::init(2),
31 cl::desc("Maximum number of uses of a global address such that we still us a"
32 "constant extended instruction"));
34 //===----------------------------------------------------------------------===//
35 // Instruction Selector Implementation
36 //===----------------------------------------------------------------------===//
39 void initializeHexagonDAGToDAGISelPass(PassRegistry&);
42 //===--------------------------------------------------------------------===//
43 /// HexagonDAGToDAGISel - Hexagon specific code to select Hexagon machine
44 /// instructions for SelectionDAG operations.
47 class HexagonDAGToDAGISel : public SelectionDAGISel {
48 /// Subtarget - Keep a pointer to the Hexagon Subtarget around so that we can
49 /// make the right decision when generating code for different targets.
50 const HexagonSubtarget *Subtarget;
52 // Keep a reference to HexagonTargetMachine.
53 const HexagonTargetMachine& TM;
54 DenseMap<const GlobalValue *, unsigned> GlobalAddressUseCountMap;
56 explicit HexagonDAGToDAGISel(HexagonTargetMachine &targetmachine,
57 CodeGenOpt::Level OptLevel)
58 : SelectionDAGISel(targetmachine, OptLevel), TM(targetmachine) {
59 initializeHexagonDAGToDAGISelPass(*PassRegistry::getPassRegistry());
61 bool hasNumUsesBelowThresGA(SDNode *N) const;
63 SDNode *Select(SDNode *N) override;
65 // Complex Pattern Selectors.
66 inline bool foldGlobalAddress(SDValue &N, SDValue &R);
67 inline bool foldGlobalAddressGP(SDValue &N, SDValue &R);
68 bool foldGlobalAddressImpl(SDValue &N, SDValue &R, bool ShouldLookForGP);
69 bool SelectADDRri(SDValue& N, SDValue &R1, SDValue &R2);
70 bool SelectADDRriS11_0(SDValue& N, SDValue &R1, SDValue &R2);
71 bool SelectADDRriS11_1(SDValue& N, SDValue &R1, SDValue &R2);
72 bool SelectADDRriS11_2(SDValue& N, SDValue &R1, SDValue &R2);
73 bool SelectMEMriS11_2(SDValue& Addr, SDValue &Base, SDValue &Offset);
74 bool SelectADDRriS11_3(SDValue& N, SDValue &R1, SDValue &R2);
75 bool SelectADDRrr(SDValue &Addr, SDValue &Base, SDValue &Offset);
76 bool SelectADDRriU6_0(SDValue& N, SDValue &R1, SDValue &R2);
77 bool SelectADDRriU6_1(SDValue& N, SDValue &R1, SDValue &R2);
78 bool SelectADDRriU6_2(SDValue& N, SDValue &R1, SDValue &R2);
80 // Complex Pattern Selectors.
81 inline bool SelectAddrGA(SDValue &N, SDValue &R);
82 inline bool SelectAddrGP(SDValue &N, SDValue &R);
83 bool SelectGlobalAddress(SDValue &N, SDValue &R, bool UseGP);
84 bool SelectAddrFI(SDValue &N, SDValue &R);
86 const char *getPassName() const override {
87 return "Hexagon DAG->DAG Pattern Instruction Selection";
90 bool runOnMachineFunction(MachineFunction &MF) override {
91 Subtarget = &MF.getSubtarget<HexagonSubtarget>();
92 return SelectionDAGISel::runOnMachineFunction(MF);
95 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
96 /// inline asm expressions.
97 bool SelectInlineAsmMemoryOperand(const SDValue &Op,
99 std::vector<SDValue> &OutOps) override;
100 bool SelectAddr(SDNode *Op, SDValue Addr, SDValue &Base, SDValue &Offset);
102 SDNode *SelectLoad(SDNode *N);
103 SDNode *SelectBaseOffsetLoad(LoadSDNode *LD, SDLoc dl);
104 SDNode *SelectIndexedLoad(LoadSDNode *LD, SDLoc dl);
105 SDNode *SelectIndexedLoadZeroExtend64(LoadSDNode *LD, unsigned Opcode,
107 SDNode *SelectIndexedLoadSignExtend64(LoadSDNode *LD, unsigned Opcode,
109 SDNode *SelectBaseOffsetStore(StoreSDNode *ST, SDLoc dl);
110 SDNode *SelectIndexedStore(StoreSDNode *ST, SDLoc dl);
111 SDNode *SelectStore(SDNode *N);
112 SDNode *SelectSHL(SDNode *N);
113 SDNode *SelectSelect(SDNode *N);
114 SDNode *SelectTruncate(SDNode *N);
115 SDNode *SelectMul(SDNode *N);
116 SDNode *SelectZeroExtend(SDNode *N);
117 SDNode *SelectIntrinsicWOChain(SDNode *N);
118 SDNode *SelectIntrinsicWChain(SDNode *N);
119 SDNode *SelectConstant(SDNode *N);
120 SDNode *SelectConstantFP(SDNode *N);
121 SDNode *SelectAdd(SDNode *N);
122 bool isConstExtProfitable(SDNode *N) const;
124 // XformMskToBitPosU5Imm - Returns the bit position which
125 // the single bit 32 bit mask represents.
126 // Used in Clr and Set bit immediate memops.
127 SDValue XformMskToBitPosU5Imm(uint32_t Imm) {
129 bitPos = Log2_32(Imm);
130 assert(bitPos >= 0 && bitPos < 32 &&
131 "Constant out of range for 32 BitPos Memops");
132 return CurDAG->getTargetConstant(bitPos, MVT::i32);
135 // XformMskToBitPosU4Imm - Returns the bit position which the single bit 16 bit
136 // mask represents. Used in Clr and Set bit immediate memops.
137 SDValue XformMskToBitPosU4Imm(uint16_t Imm) {
138 return XformMskToBitPosU5Imm(Imm);
141 // XformMskToBitPosU3Imm - Returns the bit position which the single bit 8 bit
142 // mask represents. Used in Clr and Set bit immediate memops.
143 SDValue XformMskToBitPosU3Imm(uint8_t Imm) {
144 return XformMskToBitPosU5Imm(Imm);
147 // Return true if there is exactly one bit set in V, i.e., if V is one of the
148 // following integers: 2^0, 2^1, ..., 2^31.
149 bool ImmIsSingleBit(uint32_t v) const {
150 return isPowerOf2_32(v);
153 // XformM5ToU5Imm - Return a target constant with the specified value, of type
154 // i32 where the negative literal is transformed into a positive literal for
156 inline SDValue XformM5ToU5Imm(signed Imm) {
157 assert( (Imm >= -31 && Imm <= -1) && "Constant out of range for Memops");
158 return CurDAG->getTargetConstant( - Imm, MVT::i32);
162 // XformU7ToU7M1Imm - Return a target constant decremented by 1, in range
163 // [1..128], used in cmpb.gtu instructions.
164 inline SDValue XformU7ToU7M1Imm(signed Imm) {
165 assert((Imm >= 1 && Imm <= 128) && "Constant out of range for cmpb op");
166 return CurDAG->getTargetConstant(Imm - 1, MVT::i8);
169 // XformS8ToS8M1Imm - Return a target constant decremented by 1.
170 inline SDValue XformSToSM1Imm(signed Imm) {
171 return CurDAG->getTargetConstant(Imm - 1, MVT::i32);
174 // XformU8ToU8M1Imm - Return a target constant decremented by 1.
175 inline SDValue XformUToUM1Imm(unsigned Imm) {
176 assert((Imm >= 1) && "Cannot decrement unsigned int less than 1");
177 return CurDAG->getTargetConstant(Imm - 1, MVT::i32);
180 // XformSToSM2Imm - Return a target constant decremented by 2.
181 inline SDValue XformSToSM2Imm(unsigned Imm) {
182 return CurDAG->getTargetConstant(Imm - 2, MVT::i32);
185 // XformSToSM3Imm - Return a target constant decremented by 3.
186 inline SDValue XformSToSM3Imm(unsigned Imm) {
187 return CurDAG->getTargetConstant(Imm - 3, MVT::i32);
190 // Include the pieces autogenerated from the target description.
191 #include "HexagonGenDAGISel.inc"
194 bool isValueExtension(SDValue const &Val, unsigned FromBits, SDValue &Src);
196 } // end anonymous namespace
199 /// createHexagonISelDag - This pass converts a legalized DAG into a
200 /// Hexagon-specific DAG, ready for instruction scheduling.
202 FunctionPass *llvm::createHexagonISelDag(HexagonTargetMachine &TM,
203 CodeGenOpt::Level OptLevel) {
204 return new HexagonDAGToDAGISel(TM, OptLevel);
207 static void initializePassOnce(PassRegistry &Registry) {
208 const char *Name = "Hexagon DAG->DAG Pattern Instruction Selection";
209 PassInfo *PI = new PassInfo(Name, "hexagon-isel",
210 &SelectionDAGISel::ID, nullptr, false, false);
211 Registry.registerPass(*PI, true);
214 void llvm::initializeHexagonDAGToDAGISelPass(PassRegistry &Registry) {
215 CALL_ONCE_INITIALIZATION(initializePassOnce)
219 static bool IsS11_0_Offset(SDNode * S) {
220 ConstantSDNode *N = cast<ConstantSDNode>(S);
222 // immS16 predicate - True if the immediate fits in a 16-bit sign extended
224 int64_t v = (int64_t)N->getSExtValue();
229 static bool IsS11_1_Offset(SDNode * S) {
230 ConstantSDNode *N = cast<ConstantSDNode>(S);
232 // immS16 predicate - True if the immediate fits in a 16-bit sign extended
234 int64_t v = (int64_t)N->getSExtValue();
235 return isShiftedInt<11,1>(v);
239 static bool IsS11_2_Offset(SDNode * S) {
240 ConstantSDNode *N = cast<ConstantSDNode>(S);
242 // immS16 predicate - True if the immediate fits in a 16-bit sign extended
244 int64_t v = (int64_t)N->getSExtValue();
245 return isShiftedInt<11,2>(v);
249 static bool IsS11_3_Offset(SDNode * S) {
250 ConstantSDNode *N = cast<ConstantSDNode>(S);
252 // immS16 predicate - True if the immediate fits in a 16-bit sign extended
254 int64_t v = (int64_t)N->getSExtValue();
255 return isShiftedInt<11,3>(v);
259 static bool IsU6_0_Offset(SDNode * S) {
260 ConstantSDNode *N = cast<ConstantSDNode>(S);
262 // u6 predicate - True if the immediate fits in a 6-bit unsigned extended
264 int64_t v = (int64_t)N->getSExtValue();
269 static bool IsU6_1_Offset(SDNode * S) {
270 ConstantSDNode *N = cast<ConstantSDNode>(S);
272 // u6 predicate - True if the immediate fits in a 6-bit unsigned extended
274 int64_t v = (int64_t)N->getSExtValue();
275 return isShiftedUInt<6,1>(v);
279 static bool IsU6_2_Offset(SDNode * S) {
280 ConstantSDNode *N = cast<ConstantSDNode>(S);
282 // u6 predicate - True if the immediate fits in a 6-bit unsigned extended
284 int64_t v = (int64_t)N->getSExtValue();
285 return isShiftedUInt<6,2>(v);
289 // Intrinsics that return a a predicate.
290 static unsigned doesIntrinsicReturnPredicate(unsigned ID)
295 case Intrinsic::hexagon_C2_cmpeq:
296 case Intrinsic::hexagon_C2_cmpgt:
297 case Intrinsic::hexagon_C2_cmpgtu:
298 case Intrinsic::hexagon_C2_cmpgtup:
299 case Intrinsic::hexagon_C2_cmpgtp:
300 case Intrinsic::hexagon_C2_cmpeqp:
301 case Intrinsic::hexagon_C2_bitsset:
302 case Intrinsic::hexagon_C2_bitsclr:
303 case Intrinsic::hexagon_C2_cmpeqi:
304 case Intrinsic::hexagon_C2_cmpgti:
305 case Intrinsic::hexagon_C2_cmpgtui:
306 case Intrinsic::hexagon_C2_cmpgei:
307 case Intrinsic::hexagon_C2_cmpgeui:
308 case Intrinsic::hexagon_C2_cmplt:
309 case Intrinsic::hexagon_C2_cmpltu:
310 case Intrinsic::hexagon_C2_bitsclri:
311 case Intrinsic::hexagon_C2_and:
312 case Intrinsic::hexagon_C2_or:
313 case Intrinsic::hexagon_C2_xor:
314 case Intrinsic::hexagon_C2_andn:
315 case Intrinsic::hexagon_C2_not:
316 case Intrinsic::hexagon_C2_orn:
317 case Intrinsic::hexagon_C2_pxfer_map:
318 case Intrinsic::hexagon_C2_any8:
319 case Intrinsic::hexagon_C2_all8:
320 case Intrinsic::hexagon_A2_vcmpbeq:
321 case Intrinsic::hexagon_A2_vcmpbgtu:
322 case Intrinsic::hexagon_A2_vcmpheq:
323 case Intrinsic::hexagon_A2_vcmphgt:
324 case Intrinsic::hexagon_A2_vcmphgtu:
325 case Intrinsic::hexagon_A2_vcmpweq:
326 case Intrinsic::hexagon_A2_vcmpwgt:
327 case Intrinsic::hexagon_A2_vcmpwgtu:
328 case Intrinsic::hexagon_C2_tfrrp:
329 case Intrinsic::hexagon_S2_tstbit_i:
330 case Intrinsic::hexagon_S2_tstbit_r:
336 SDNode *HexagonDAGToDAGISel::SelectIndexedLoadSignExtend64(LoadSDNode *LD,
340 SDValue Chain = LD->getChain();
341 EVT LoadedVT = LD->getMemoryVT();
342 SDValue Base = LD->getBasePtr();
343 SDValue Offset = LD->getOffset();
344 SDNode *OffsetNode = Offset.getNode();
345 int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
346 SDValue N1 = LD->getOperand(1);
350 if (SelectADDRriS11_2(N1, CPTmpN1_0, CPTmpN1_1) &&
351 N1.getNode()->getValueType(0) == MVT::i32) {
352 const HexagonInstrInfo *TII = Subtarget->getInstrInfo();
353 if (TII->isValidAutoIncImm(LoadedVT, Val)) {
354 SDValue TargetConst = CurDAG->getTargetConstant(Val, MVT::i32);
355 SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::i32,
356 MVT::Other, Base, TargetConst,
358 SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_sxtw, dl, MVT::i64,
359 SDValue(Result_1, 0));
360 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
361 MemOp[0] = LD->getMemOperand();
362 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
363 const SDValue Froms[] = { SDValue(LD, 0),
367 const SDValue Tos[] = { SDValue(Result_2, 0),
368 SDValue(Result_1, 1),
371 ReplaceUses(Froms, Tos, 3);
374 SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
375 SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
376 SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
377 MVT::Other, Base, TargetConst0,
379 SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_sxtw, dl,
380 MVT::i64, SDValue(Result_1, 0));
381 SDNode* Result_3 = CurDAG->getMachineNode(Hexagon::A2_addi, dl,
382 MVT::i32, Base, TargetConstVal,
383 SDValue(Result_1, 1));
384 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
385 MemOp[0] = LD->getMemOperand();
386 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
387 const SDValue Froms[] = { SDValue(LD, 0),
391 const SDValue Tos[] = { SDValue(Result_2, 0),
392 SDValue(Result_3, 0),
395 ReplaceUses(Froms, Tos, 3);
398 return SelectCode(LD);
402 SDNode *HexagonDAGToDAGISel::SelectIndexedLoadZeroExtend64(LoadSDNode *LD,
406 SDValue Chain = LD->getChain();
407 EVT LoadedVT = LD->getMemoryVT();
408 SDValue Base = LD->getBasePtr();
409 SDValue Offset = LD->getOffset();
410 SDNode *OffsetNode = Offset.getNode();
411 int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
412 SDValue N1 = LD->getOperand(1);
416 if (SelectADDRriS11_2(N1, CPTmpN1_0, CPTmpN1_1) &&
417 N1.getNode()->getValueType(0) == MVT::i32) {
418 const HexagonInstrInfo *TII = Subtarget->getInstrInfo();
419 if (TII->isValidAutoIncImm(LoadedVT, Val)) {
420 SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
421 SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
422 SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
423 MVT::i32, MVT::Other, Base,
424 TargetConstVal, Chain);
425 SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_tfrsi, dl, MVT::i32,
427 SDNode *Result_3 = CurDAG->getMachineNode(Hexagon::A2_combinew, dl,
428 MVT::i64, MVT::Other,
430 SDValue(Result_1,0));
431 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
432 MemOp[0] = LD->getMemOperand();
433 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
434 const SDValue Froms[] = { SDValue(LD, 0),
438 const SDValue Tos[] = { SDValue(Result_3, 0),
439 SDValue(Result_1, 1),
442 ReplaceUses(Froms, Tos, 3);
446 // Generate an indirect load.
447 SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
448 SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
449 SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
451 Base, TargetConst0, Chain);
452 SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_tfrsi, dl, MVT::i32,
454 SDNode *Result_3 = CurDAG->getMachineNode(Hexagon::A2_combinew, dl,
455 MVT::i64, MVT::Other,
457 SDValue(Result_1,0));
458 // Add offset to base.
459 SDNode* Result_4 = CurDAG->getMachineNode(Hexagon::A2_addi, dl, MVT::i32,
460 Base, TargetConstVal,
461 SDValue(Result_1, 1));
462 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
463 MemOp[0] = LD->getMemOperand();
464 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
465 const SDValue Froms[] = { SDValue(LD, 0),
469 const SDValue Tos[] = { SDValue(Result_3, 0), // Load value.
470 SDValue(Result_4, 0), // New address.
473 ReplaceUses(Froms, Tos, 3);
477 return SelectCode(LD);
481 SDNode *HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, SDLoc dl) {
482 SDValue Chain = LD->getChain();
483 SDValue Base = LD->getBasePtr();
484 SDValue Offset = LD->getOffset();
485 SDNode *OffsetNode = Offset.getNode();
486 // Get the constant value.
487 int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
488 EVT LoadedVT = LD->getMemoryVT();
491 // Check for zero ext loads.
492 bool zextval = (LD->getExtensionType() == ISD::ZEXTLOAD);
494 // Figure out the opcode.
495 const HexagonInstrInfo *TII = Subtarget->getInstrInfo();
496 if (LoadedVT == MVT::i64) {
497 if (TII->isValidAutoIncImm(LoadedVT, Val))
498 Opcode = Hexagon::L2_loadrd_pi;
500 Opcode = Hexagon::L2_loadrd_io;
501 } else if (LoadedVT == MVT::i32) {
502 if (TII->isValidAutoIncImm(LoadedVT, Val))
503 Opcode = Hexagon::L2_loadri_pi;
505 Opcode = Hexagon::L2_loadri_io;
506 } else if (LoadedVT == MVT::i16) {
507 if (TII->isValidAutoIncImm(LoadedVT, Val))
508 Opcode = zextval ? Hexagon::L2_loadruh_pi : Hexagon::L2_loadrh_pi;
510 Opcode = zextval ? Hexagon::L2_loadruh_io : Hexagon::L2_loadrh_io;
511 } else if (LoadedVT == MVT::i8) {
512 if (TII->isValidAutoIncImm(LoadedVT, Val))
513 Opcode = zextval ? Hexagon::L2_loadrub_pi : Hexagon::L2_loadrb_pi;
515 Opcode = zextval ? Hexagon::L2_loadrub_io : Hexagon::L2_loadrb_io;
517 llvm_unreachable("unknown memory type");
519 // For zero ext i64 loads, we need to add combine instructions.
520 if (LD->getValueType(0) == MVT::i64 &&
521 LD->getExtensionType() == ISD::ZEXTLOAD) {
522 return SelectIndexedLoadZeroExtend64(LD, Opcode, dl);
524 if (LD->getValueType(0) == MVT::i64 &&
525 LD->getExtensionType() == ISD::SEXTLOAD) {
526 // Handle sign ext i64 loads.
527 return SelectIndexedLoadSignExtend64(LD, Opcode, dl);
529 if (TII->isValidAutoIncImm(LoadedVT, Val)) {
530 SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
531 SDNode* Result = CurDAG->getMachineNode(Opcode, dl,
533 MVT::i32, MVT::Other, Base,
534 TargetConstVal, Chain);
535 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
536 MemOp[0] = LD->getMemOperand();
537 cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1);
538 const SDValue Froms[] = { SDValue(LD, 0),
542 const SDValue Tos[] = { SDValue(Result, 0),
546 ReplaceUses(Froms, Tos, 3);
549 SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
550 SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
551 SDNode* Result_1 = CurDAG->getMachineNode(Opcode, dl,
553 MVT::Other, Base, TargetConst0,
555 SDNode* Result_2 = CurDAG->getMachineNode(Hexagon::A2_addi, dl, MVT::i32,
556 Base, TargetConstVal,
557 SDValue(Result_1, 1));
558 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
559 MemOp[0] = LD->getMemOperand();
560 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
561 const SDValue Froms[] = { SDValue(LD, 0),
565 const SDValue Tos[] = { SDValue(Result_1, 0),
566 SDValue(Result_2, 0),
569 ReplaceUses(Froms, Tos, 3);
575 SDNode *HexagonDAGToDAGISel::SelectLoad(SDNode *N) {
578 LoadSDNode *LD = cast<LoadSDNode>(N);
579 ISD::MemIndexedMode AM = LD->getAddressingMode();
581 // Handle indexed loads.
582 if (AM != ISD::UNINDEXED) {
583 result = SelectIndexedLoad(LD, dl);
585 result = SelectCode(LD);
592 SDNode *HexagonDAGToDAGISel::SelectIndexedStore(StoreSDNode *ST, SDLoc dl) {
593 SDValue Chain = ST->getChain();
594 SDValue Base = ST->getBasePtr();
595 SDValue Offset = ST->getOffset();
596 SDValue Value = ST->getValue();
597 SDNode *OffsetNode = Offset.getNode();
598 // Get the constant value.
599 int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
600 EVT StoredVT = ST->getMemoryVT();
602 // Offset value must be within representable range
603 // and must have correct alignment properties.
604 const HexagonInstrInfo *TII = Subtarget->getInstrInfo();
605 if (TII->isValidAutoIncImm(StoredVT, Val)) {
606 SDValue Ops[] = {Base, CurDAG->getTargetConstant(Val, MVT::i32), Value,
610 // Figure out the post inc version of opcode.
611 if (StoredVT == MVT::i64) Opcode = Hexagon::S2_storerd_pi;
612 else if (StoredVT == MVT::i32) Opcode = Hexagon::S2_storeri_pi;
613 else if (StoredVT == MVT::i16) Opcode = Hexagon::S2_storerh_pi;
614 else if (StoredVT == MVT::i8) Opcode = Hexagon::S2_storerb_pi;
615 else llvm_unreachable("unknown memory type");
617 // Build post increment store.
618 SDNode* Result = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
620 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
621 MemOp[0] = ST->getMemOperand();
622 cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1);
624 ReplaceUses(ST, Result);
625 ReplaceUses(SDValue(ST,1), SDValue(Result,1));
629 // Note: Order of operands matches the def of instruction:
630 // def STrid : STInst<(outs), (ins MEMri:$addr, DoubleRegs:$src1), ...
631 // and it differs for POST_ST* for instance.
632 SDValue Ops[] = { Base, CurDAG->getTargetConstant(0, MVT::i32), Value,
636 // Figure out the opcode.
637 if (StoredVT == MVT::i64) Opcode = Hexagon::S2_storerd_io;
638 else if (StoredVT == MVT::i32) Opcode = Hexagon::S2_storeri_io;
639 else if (StoredVT == MVT::i16) Opcode = Hexagon::S2_storerh_io;
640 else if (StoredVT == MVT::i8) Opcode = Hexagon::S2_storerb_io;
641 else llvm_unreachable("unknown memory type");
643 // Build regular store.
644 SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
645 SDNode* Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
646 // Build splitted incriment instruction.
647 SDNode* Result_2 = CurDAG->getMachineNode(Hexagon::A2_addi, dl, MVT::i32,
650 SDValue(Result_1, 0));
651 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
652 MemOp[0] = ST->getMemOperand();
653 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
655 ReplaceUses(SDValue(ST,0), SDValue(Result_2,0));
656 ReplaceUses(SDValue(ST,1), SDValue(Result_1,0));
661 SDNode *HexagonDAGToDAGISel::SelectStore(SDNode *N) {
663 StoreSDNode *ST = cast<StoreSDNode>(N);
664 ISD::MemIndexedMode AM = ST->getAddressingMode();
666 // Handle indexed stores.
667 if (AM != ISD::UNINDEXED) {
668 return SelectIndexedStore(ST, dl);
671 return SelectCode(ST);
674 SDNode *HexagonDAGToDAGISel::SelectMul(SDNode *N) {
678 // %conv.i = sext i32 %tmp1 to i64
679 // %conv2.i = sext i32 %add to i64
680 // %mul.i = mul nsw i64 %conv2.i, %conv.i
682 // --- match with the following ---
684 // %mul.i = mpy (%tmp1, %add)
687 if (N->getValueType(0) == MVT::i64) {
688 // Shifting a i64 signed multiply.
689 SDValue MulOp0 = N->getOperand(0);
690 SDValue MulOp1 = N->getOperand(1);
695 // Handle sign_extend and sextload.
696 if (MulOp0.getOpcode() == ISD::SIGN_EXTEND) {
697 SDValue Sext0 = MulOp0.getOperand(0);
698 if (Sext0.getNode()->getValueType(0) != MVT::i32) {
699 return SelectCode(N);
703 } else if (MulOp0.getOpcode() == ISD::LOAD) {
704 LoadSDNode *LD = cast<LoadSDNode>(MulOp0.getNode());
705 if (LD->getMemoryVT() != MVT::i32 ||
706 LD->getExtensionType() != ISD::SEXTLOAD ||
707 LD->getAddressingMode() != ISD::UNINDEXED) {
708 return SelectCode(N);
711 SDValue Chain = LD->getChain();
712 SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
713 OP0 = SDValue(CurDAG->getMachineNode(Hexagon::L2_loadri_io, dl, MVT::i32,
715 LD->getBasePtr(), TargetConst0,
718 return SelectCode(N);
721 // Same goes for the second operand.
722 if (MulOp1.getOpcode() == ISD::SIGN_EXTEND) {
723 SDValue Sext1 = MulOp1.getOperand(0);
724 if (Sext1.getNode()->getValueType(0) != MVT::i32) {
725 return SelectCode(N);
729 } else if (MulOp1.getOpcode() == ISD::LOAD) {
730 LoadSDNode *LD = cast<LoadSDNode>(MulOp1.getNode());
731 if (LD->getMemoryVT() != MVT::i32 ||
732 LD->getExtensionType() != ISD::SEXTLOAD ||
733 LD->getAddressingMode() != ISD::UNINDEXED) {
734 return SelectCode(N);
737 SDValue Chain = LD->getChain();
738 SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
739 OP1 = SDValue(CurDAG->getMachineNode(Hexagon::L2_loadri_io, dl, MVT::i32,
741 LD->getBasePtr(), TargetConst0,
744 return SelectCode(N);
747 // Generate a mpy instruction.
748 SDNode *Result = CurDAG->getMachineNode(Hexagon::M2_dpmpyss_s0, dl, MVT::i64,
750 ReplaceUses(N, Result);
754 return SelectCode(N);
758 SDNode *HexagonDAGToDAGISel::SelectSelect(SDNode *N) {
760 SDValue N0 = N->getOperand(0);
761 if (N0.getOpcode() == ISD::SETCC) {
762 SDValue N00 = N0.getOperand(0);
763 if (N00.getOpcode() == ISD::SIGN_EXTEND_INREG) {
764 SDValue N000 = N00.getOperand(0);
765 SDValue N001 = N00.getOperand(1);
766 if (cast<VTSDNode>(N001)->getVT() == MVT::i16) {
767 SDValue N01 = N0.getOperand(1);
768 SDValue N02 = N0.getOperand(2);
770 // Pattern: (select:i32 (setcc:i1 (sext_inreg:i32 IntRegs:i32:$src2,
771 // i16:Other),IntRegs:i32:$src1, SETLT:Other),IntRegs:i32:$src1,
772 // IntRegs:i32:$src2)
773 // Emits: (MAXh_rr:i32 IntRegs:i32:$src1, IntRegs:i32:$src2)
774 // Pattern complexity = 9 cost = 1 size = 0.
775 if (cast<CondCodeSDNode>(N02)->get() == ISD::SETLT) {
776 SDValue N1 = N->getOperand(1);
778 SDValue N2 = N->getOperand(2);
780 N0.getNode()->getValueType(N0.getResNo()) == MVT::i1 &&
781 N00.getNode()->getValueType(N00.getResNo()) == MVT::i32) {
782 SDNode *SextNode = CurDAG->getMachineNode(Hexagon::A2_sxth, dl,
784 SDNode *Result = CurDAG->getMachineNode(Hexagon::A2_max, dl,
786 SDValue(SextNode, 0),
788 ReplaceUses(N, Result);
794 // Pattern: (select:i32 (setcc:i1 (sext_inreg:i32 IntRegs:i32:$src2,
795 // i16:Other), IntRegs:i32:$src1, SETGT:Other), IntRegs:i32:$src1,
796 // IntRegs:i32:$src2)
797 // Emits: (MINh_rr:i32 IntRegs:i32:$src1, IntRegs:i32:$src2)
798 // Pattern complexity = 9 cost = 1 size = 0.
799 if (cast<CondCodeSDNode>(N02)->get() == ISD::SETGT) {
800 SDValue N1 = N->getOperand(1);
802 SDValue N2 = N->getOperand(2);
804 N0.getNode()->getValueType(N0.getResNo()) == MVT::i1 &&
805 N00.getNode()->getValueType(N00.getResNo()) == MVT::i32) {
806 SDNode *SextNode = CurDAG->getMachineNode(Hexagon::A2_sxth, dl,
808 SDNode *Result = CurDAG->getMachineNode(Hexagon::A2_min, dl,
810 SDValue(SextNode, 0),
812 ReplaceUses(N, Result);
821 return SelectCode(N);
825 SDNode *HexagonDAGToDAGISel::SelectTruncate(SDNode *N) {
827 SDValue Shift = N->getOperand(0);
830 // %conv.i = sext i32 %tmp1 to i64
831 // %conv2.i = sext i32 %add to i64
832 // %mul.i = mul nsw i64 %conv2.i, %conv.i
833 // %shr5.i = lshr i64 %mul.i, 32
834 // %conv3.i = trunc i64 %shr5.i to i32
836 // --- match with the following ---
838 // %conv3.i = mpy (%tmp1, %add)
841 if (N->getValueType(0) == MVT::i32) {
843 if (Shift.getNode()->getValueType(0) == MVT::i64) {
844 // Trunc child is logical shift right.
845 if (Shift.getOpcode() != ISD::SRL) {
846 return SelectCode(N);
849 SDValue ShiftOp0 = Shift.getOperand(0);
850 SDValue ShiftOp1 = Shift.getOperand(1);
853 if (ShiftOp1.getOpcode() != ISD::Constant) {
854 return SelectCode(N);
858 cast<ConstantSDNode>(ShiftOp1.getNode())->getSExtValue();
859 if (ShiftConst != 32) {
860 return SelectCode(N);
863 // Shifting a i64 signed multiply
864 SDValue Mul = ShiftOp0;
865 if (Mul.getOpcode() != ISD::MUL) {
866 return SelectCode(N);
869 SDValue MulOp0 = Mul.getOperand(0);
870 SDValue MulOp1 = Mul.getOperand(1);
875 // Handle sign_extend and sextload
876 if (MulOp0.getOpcode() == ISD::SIGN_EXTEND) {
877 SDValue Sext0 = MulOp0.getOperand(0);
878 if (Sext0.getNode()->getValueType(0) != MVT::i32) {
879 return SelectCode(N);
883 } else if (MulOp0.getOpcode() == ISD::LOAD) {
884 LoadSDNode *LD = cast<LoadSDNode>(MulOp0.getNode());
885 if (LD->getMemoryVT() != MVT::i32 ||
886 LD->getExtensionType() != ISD::SEXTLOAD ||
887 LD->getAddressingMode() != ISD::UNINDEXED) {
888 return SelectCode(N);
891 SDValue Chain = LD->getChain();
892 SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
893 OP0 = SDValue(CurDAG->getMachineNode(Hexagon::L2_loadri_io, dl, MVT::i32,
896 TargetConst0, Chain), 0);
898 return SelectCode(N);
901 // Same goes for the second operand.
902 if (MulOp1.getOpcode() == ISD::SIGN_EXTEND) {
903 SDValue Sext1 = MulOp1.getOperand(0);
904 if (Sext1.getNode()->getValueType(0) != MVT::i32)
905 return SelectCode(N);
908 } else if (MulOp1.getOpcode() == ISD::LOAD) {
909 LoadSDNode *LD = cast<LoadSDNode>(MulOp1.getNode());
910 if (LD->getMemoryVT() != MVT::i32 ||
911 LD->getExtensionType() != ISD::SEXTLOAD ||
912 LD->getAddressingMode() != ISD::UNINDEXED) {
913 return SelectCode(N);
916 SDValue Chain = LD->getChain();
917 SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
918 OP1 = SDValue(CurDAG->getMachineNode(Hexagon::L2_loadri_io, dl, MVT::i32,
921 TargetConst0, Chain), 0);
923 return SelectCode(N);
926 // Generate a mpy instruction.
927 SDNode *Result = CurDAG->getMachineNode(Hexagon::M2_mpy_up, dl, MVT::i32,
929 ReplaceUses(N, Result);
934 return SelectCode(N);
938 SDNode *HexagonDAGToDAGISel::SelectSHL(SDNode *N) {
940 if (N->getValueType(0) == MVT::i32) {
941 SDValue Shl_0 = N->getOperand(0);
942 SDValue Shl_1 = N->getOperand(1);
944 if (Shl_1.getOpcode() == ISD::Constant) {
945 if (Shl_0.getOpcode() == ISD::MUL) {
946 SDValue Mul_0 = Shl_0.getOperand(0); // Val
947 SDValue Mul_1 = Shl_0.getOperand(1); // Const
948 // RHS of mul is const.
949 if (Mul_1.getOpcode() == ISD::Constant) {
951 cast<ConstantSDNode>(Shl_1.getNode())->getSExtValue();
953 cast<ConstantSDNode>(Mul_1.getNode())->getSExtValue();
954 int32_t ValConst = MulConst << ShlConst;
955 SDValue Val = CurDAG->getTargetConstant(ValConst,
957 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val.getNode()))
958 if (isInt<9>(CN->getSExtValue())) {
960 CurDAG->getMachineNode(Hexagon::M2_mpysmi, dl,
961 MVT::i32, Mul_0, Val);
962 ReplaceUses(N, Result);
967 } else if (Shl_0.getOpcode() == ISD::SUB) {
968 SDValue Sub_0 = Shl_0.getOperand(0); // Const 0
969 SDValue Sub_1 = Shl_0.getOperand(1); // Val
970 if (Sub_0.getOpcode() == ISD::Constant) {
972 cast<ConstantSDNode>(Sub_0.getNode())->getSExtValue();
974 if (Sub_1.getOpcode() == ISD::SHL) {
975 SDValue Shl2_0 = Sub_1.getOperand(0); // Val
976 SDValue Shl2_1 = Sub_1.getOperand(1); // Const
977 if (Shl2_1.getOpcode() == ISD::Constant) {
979 cast<ConstantSDNode>(Shl_1.getNode())->getSExtValue();
981 cast<ConstantSDNode>(Shl2_1.getNode())->getSExtValue();
982 int32_t ValConst = 1 << (ShlConst+Shl2Const);
983 SDValue Val = CurDAG->getTargetConstant(-ValConst, MVT::i32);
984 if (ConstantSDNode *CN =
985 dyn_cast<ConstantSDNode>(Val.getNode()))
986 if (isInt<9>(CN->getSExtValue())) {
988 CurDAG->getMachineNode(Hexagon::M2_mpysmi, dl, MVT::i32,
990 ReplaceUses(N, Result);
1000 return SelectCode(N);
1005 // If there is an zero_extend followed an intrinsic in DAG (this means - the
1006 // result of the intrinsic is predicate); convert the zero_extend to
1007 // transfer instruction.
1009 // Zero extend -> transfer is lowered here. Otherwise, zero_extend will be
1010 // converted into a MUX as predicate registers defined as 1 bit in the
1011 // compiler. Architecture defines them as 8-bit registers.
1012 // We want to preserve all the lower 8-bits and, not just 1 LSB bit.
1014 SDNode *HexagonDAGToDAGISel::SelectZeroExtend(SDNode *N) {
1016 SDNode *IsIntrinsic = N->getOperand(0).getNode();
1017 if ((IsIntrinsic->getOpcode() == ISD::INTRINSIC_WO_CHAIN)) {
1019 cast<ConstantSDNode>(IsIntrinsic->getOperand(0))->getZExtValue();
1020 if (doesIntrinsicReturnPredicate(ID)) {
1021 // Now we need to differentiate target data types.
1022 if (N->getValueType(0) == MVT::i64) {
1023 // Convert the zero_extend to Rs = Pd followed by COMBINE_rr(0,Rs).
1024 SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
1025 SDNode *Result_1 = CurDAG->getMachineNode(Hexagon::C2_tfrpr, dl,
1027 SDValue(IsIntrinsic, 0));
1028 SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_tfrsi, dl,
1031 SDNode *Result_3 = CurDAG->getMachineNode(Hexagon::A2_combinew, dl,
1032 MVT::i64, MVT::Other,
1033 SDValue(Result_2, 0),
1034 SDValue(Result_1, 0));
1035 ReplaceUses(N, Result_3);
1038 if (N->getValueType(0) == MVT::i32) {
1039 // Convert the zero_extend to Rs = Pd
1040 SDNode* RsPd = CurDAG->getMachineNode(Hexagon::C2_tfrpr, dl,
1042 SDValue(IsIntrinsic, 0));
1043 ReplaceUses(N, RsPd);
1046 llvm_unreachable("Unexpected value type");
1049 return SelectCode(N);
1053 // Checking for intrinsics which have predicate registers as operand(s)
1054 // and lowering to the actual intrinsic.
1056 SDNode *HexagonDAGToDAGISel::SelectIntrinsicWOChain(SDNode *N) {
1057 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
1060 case Intrinsic::hexagon_S2_vsplatrb:
1063 case Intrinsic::hexagon_S2_vsplatrh:
1067 return SelectCode(N);
1070 SDValue const &V = N->getOperand(1);
1072 if (isValueExtension(V, Bits, U)) {
1073 SDValue R = CurDAG->getNode(N->getOpcode(), SDLoc(N), N->getValueType(0),
1074 N->getOperand(0), U);
1075 return SelectCode(R.getNode());
1077 return SelectCode(N);
1081 // Map floating point constant values.
1083 SDNode *HexagonDAGToDAGISel::SelectConstantFP(SDNode *N) {
1085 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
1086 APFloat APF = CN->getValueAPF();
1087 if (N->getValueType(0) == MVT::f32) {
1088 return CurDAG->getMachineNode(Hexagon::TFRI_f, dl, MVT::f32,
1089 CurDAG->getTargetConstantFP(APF.convertToFloat(), MVT::f32));
1091 else if (N->getValueType(0) == MVT::f64) {
1092 return CurDAG->getMachineNode(Hexagon::CONST64_Float_Real, dl, MVT::f64,
1093 CurDAG->getTargetConstantFP(APF.convertToDouble(), MVT::f64));
1096 return SelectCode(N);
1101 // Map predicate true (encoded as -1 in LLVM) to a XOR.
1103 SDNode *HexagonDAGToDAGISel::SelectConstant(SDNode *N) {
1105 if (N->getValueType(0) == MVT::i1) {
1107 int32_t Val = cast<ConstantSDNode>(N)->getSExtValue();
1109 // Create the IntReg = 1 node.
1111 CurDAG->getMachineNode(Hexagon::A2_tfrsi, dl, MVT::i32,
1112 CurDAG->getTargetConstant(0, MVT::i32));
1115 SDNode* Pd = CurDAG->getMachineNode(Hexagon::C2_tfrrp, dl, MVT::i1,
1116 SDValue(IntRegTFR, 0));
1119 SDNode* NotPd = CurDAG->getMachineNode(Hexagon::C2_not, dl, MVT::i1,
1123 Result = CurDAG->getMachineNode(Hexagon::C2_xor, dl, MVT::i1,
1124 SDValue(Pd, 0), SDValue(NotPd, 0));
1126 // We have just built:
1128 // Pd = xor(not(Pd), Pd)
1130 ReplaceUses(N, Result);
1135 return SelectCode(N);
1140 // Map add followed by a asr -> asr +=.
1142 SDNode *HexagonDAGToDAGISel::SelectAdd(SDNode *N) {
1144 if (N->getValueType(0) != MVT::i32) {
1145 return SelectCode(N);
1147 // Identify nodes of the form: add(asr(...)).
1148 SDNode* Src1 = N->getOperand(0).getNode();
1149 if (Src1->getOpcode() != ISD::SRA || !Src1->hasOneUse()
1150 || Src1->getValueType(0) != MVT::i32) {
1151 return SelectCode(N);
1154 // Build Rd = Rd' + asr(Rs, Rt). The machine constraints will ensure that
1155 // Rd and Rd' are assigned to the same register
1156 SDNode* Result = CurDAG->getMachineNode(Hexagon::S2_asr_r_r_acc, dl, MVT::i32,
1158 Src1->getOperand(0),
1159 Src1->getOperand(1));
1160 ReplaceUses(N, Result);
1166 SDNode *HexagonDAGToDAGISel::Select(SDNode *N) {
1167 if (N->isMachineOpcode()) {
1169 return nullptr; // Already selected.
1173 switch (N->getOpcode()) {
1175 return SelectConstant(N);
1177 case ISD::ConstantFP:
1178 return SelectConstantFP(N);
1181 return SelectAdd(N);
1184 return SelectSHL(N);
1187 return SelectLoad(N);
1190 return SelectStore(N);
1193 return SelectSelect(N);
1196 return SelectTruncate(N);
1199 return SelectMul(N);
1201 case ISD::ZERO_EXTEND:
1202 return SelectZeroExtend(N);
1204 case ISD::INTRINSIC_WO_CHAIN:
1205 return SelectIntrinsicWOChain(N);
1208 return SelectCode(N);
1213 // Hexagon_TODO: Five functions for ADDRri?! Surely there must be a better way
1214 // to define these instructions.
1216 bool HexagonDAGToDAGISel::SelectADDRri(SDValue& Addr, SDValue &Base,
1218 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1219 Addr.getOpcode() == ISD::TargetGlobalAddress)
1220 return false; // Direct calls.
1222 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
1223 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1224 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1228 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1233 bool HexagonDAGToDAGISel::SelectADDRriS11_0(SDValue& Addr, SDValue &Base,
1235 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1236 Addr.getOpcode() == ISD::TargetGlobalAddress)
1237 return false; // Direct calls.
1239 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
1240 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1241 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1242 return (IsS11_0_Offset(Offset.getNode()));
1245 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1246 return (IsS11_0_Offset(Offset.getNode()));
1250 bool HexagonDAGToDAGISel::SelectADDRriS11_1(SDValue& Addr, SDValue &Base,
1252 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1253 Addr.getOpcode() == ISD::TargetGlobalAddress)
1254 return false; // Direct calls.
1256 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
1257 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1258 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1259 return (IsS11_1_Offset(Offset.getNode()));
1262 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1263 return (IsS11_1_Offset(Offset.getNode()));
1267 bool HexagonDAGToDAGISel::SelectADDRriS11_2(SDValue& Addr, SDValue &Base,
1269 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1270 Addr.getOpcode() == ISD::TargetGlobalAddress)
1271 return false; // Direct calls.
1273 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
1274 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1275 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1276 return (IsS11_2_Offset(Offset.getNode()));
1279 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1280 return (IsS11_2_Offset(Offset.getNode()));
1284 bool HexagonDAGToDAGISel::SelectADDRriU6_0(SDValue& Addr, SDValue &Base,
1286 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1287 Addr.getOpcode() == ISD::TargetGlobalAddress)
1288 return false; // Direct calls.
1290 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
1291 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1292 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1293 return (IsU6_0_Offset(Offset.getNode()));
1296 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1297 return (IsU6_0_Offset(Offset.getNode()));
1301 bool HexagonDAGToDAGISel::SelectADDRriU6_1(SDValue& Addr, SDValue &Base,
1303 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1304 Addr.getOpcode() == ISD::TargetGlobalAddress)
1305 return false; // Direct calls.
1307 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
1308 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1309 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1310 return (IsU6_1_Offset(Offset.getNode()));
1313 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1314 return (IsU6_1_Offset(Offset.getNode()));
1318 bool HexagonDAGToDAGISel::SelectADDRriU6_2(SDValue& Addr, SDValue &Base,
1320 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1321 Addr.getOpcode() == ISD::TargetGlobalAddress)
1322 return false; // Direct calls.
1324 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
1325 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1326 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1327 return (IsU6_2_Offset(Offset.getNode()));
1330 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1331 return (IsU6_2_Offset(Offset.getNode()));
1335 bool HexagonDAGToDAGISel::SelectMEMriS11_2(SDValue& Addr, SDValue &Base,
1338 if (Addr.getOpcode() != ISD::ADD) {
1339 return(SelectADDRriS11_2(Addr, Base, Offset));
1342 return SelectADDRriS11_2(Addr, Base, Offset);
1346 bool HexagonDAGToDAGISel::SelectADDRriS11_3(SDValue& Addr, SDValue &Base,
1348 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1349 Addr.getOpcode() == ISD::TargetGlobalAddress)
1350 return false; // Direct calls.
1352 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
1353 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1354 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1355 return (IsS11_3_Offset(Offset.getNode()));
1358 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1359 return (IsS11_3_Offset(Offset.getNode()));
1362 bool HexagonDAGToDAGISel::SelectADDRrr(SDValue &Addr, SDValue &R1,
1364 if (Addr.getOpcode() == ISD::FrameIndex) return false;
1365 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1366 Addr.getOpcode() == ISD::TargetGlobalAddress)
1367 return false; // Direct calls.
1369 if (Addr.getOpcode() == ISD::ADD) {
1370 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
1371 if (isInt<13>(CN->getSExtValue()))
1372 return false; // Let the reg+imm pattern catch this!
1373 R1 = Addr.getOperand(0);
1374 R2 = Addr.getOperand(1);
1384 // Handle generic address case. It is accessed from inlined asm =m constraints,
1385 // which could have any kind of pointer.
1386 bool HexagonDAGToDAGISel::SelectAddr(SDNode *Op, SDValue Addr,
1387 SDValue &Base, SDValue &Offset) {
1388 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1389 Addr.getOpcode() == ISD::TargetGlobalAddress)
1390 return false; // Direct calls.
1392 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
1393 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1394 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1398 if (Addr.getOpcode() == ISD::ADD) {
1399 Base = Addr.getOperand(0);
1400 Offset = Addr.getOperand(1);
1405 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1410 bool HexagonDAGToDAGISel::
1411 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
1412 std::vector<SDValue> &OutOps) {
1415 switch (ConstraintCode) {
1416 case 'o': // Offsetable.
1417 case 'v': // Not offsetable.
1418 default: return true;
1419 case 'm': // Memory.
1420 if (!SelectAddr(Op.getNode(), Op, Op0, Op1))
1425 OutOps.push_back(Op0);
1426 OutOps.push_back(Op1);
1430 bool HexagonDAGToDAGISel::isConstExtProfitable(SDNode *N) const {
1431 unsigned UseCount = 0;
1432 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1436 return (UseCount <= 1);
1440 //===--------------------------------------------------------------------===//
1441 // Return 'true' if use count of the global address is below threshold.
1442 //===--------------------------------------------------------------------===//
1443 bool HexagonDAGToDAGISel::hasNumUsesBelowThresGA(SDNode *N) const {
1444 assert(N->getOpcode() == ISD::TargetGlobalAddress &&
1445 "Expecting a target global address");
1447 // Always try to fold the address.
1448 if (TM.getOptLevel() == CodeGenOpt::Aggressive)
1451 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N);
1452 DenseMap<const GlobalValue *, unsigned>::const_iterator GI =
1453 GlobalAddressUseCountMap.find(GA->getGlobal());
1455 if (GI == GlobalAddressUseCountMap.end())
1458 return GI->second <= MaxNumOfUsesForConstExtenders;
1461 //===--------------------------------------------------------------------===//
1462 // Return true if the non-GP-relative global address can be folded.
1463 //===--------------------------------------------------------------------===//
1464 inline bool HexagonDAGToDAGISel::foldGlobalAddress(SDValue &N, SDValue &R) {
1465 return foldGlobalAddressImpl(N, R, false);
1468 //===--------------------------------------------------------------------===//
1469 // Return true if the GP-relative global address can be folded.
1470 //===--------------------------------------------------------------------===//
1471 inline bool HexagonDAGToDAGISel::foldGlobalAddressGP(SDValue &N, SDValue &R) {
1472 return foldGlobalAddressImpl(N, R, true);
1475 //===--------------------------------------------------------------------===//
1476 // Fold offset of the global address if number of uses are below threshold.
1477 //===--------------------------------------------------------------------===//
1478 bool HexagonDAGToDAGISel::foldGlobalAddressImpl(SDValue &N, SDValue &R,
1479 bool ShouldLookForGP) {
1480 if (N.getOpcode() == ISD::ADD) {
1481 SDValue N0 = N.getOperand(0);
1482 SDValue N1 = N.getOperand(1);
1483 if ((ShouldLookForGP && (N0.getOpcode() == HexagonISD::CONST32_GP)) ||
1484 (!ShouldLookForGP && (N0.getOpcode() == HexagonISD::CONST32))) {
1485 ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N1);
1486 GlobalAddressSDNode *GA =
1487 dyn_cast<GlobalAddressSDNode>(N0.getOperand(0));
1490 (GA->getOpcode() == ISD::TargetGlobalAddress)) {
1491 if ((N0.getOpcode() == HexagonISD::CONST32) &&
1492 !hasNumUsesBelowThresGA(GA))
1494 R = CurDAG->getTargetGlobalAddress(GA->getGlobal(),
1498 (uint64_t)Const->getSExtValue());
1506 bool HexagonDAGToDAGISel::SelectAddrFI(SDValue& N, SDValue &R) {
1507 if (N.getOpcode() != ISD::FrameIndex)
1509 FrameIndexSDNode *FX = cast<FrameIndexSDNode>(N);
1510 R = CurDAG->getTargetFrameIndex(FX->getIndex(), MVT::i32);
1514 inline bool HexagonDAGToDAGISel::SelectAddrGA(SDValue &N, SDValue &R) {
1515 return SelectGlobalAddress(N, R, false);
1518 inline bool HexagonDAGToDAGISel::SelectAddrGP(SDValue &N, SDValue &R) {
1519 return SelectGlobalAddress(N, R, true);
1522 bool HexagonDAGToDAGISel::SelectGlobalAddress(SDValue &N, SDValue &R,
1524 switch (N.getOpcode()) {
1526 SDValue N0 = N.getOperand(0);
1527 SDValue N1 = N.getOperand(1);
1528 unsigned GAOpc = N0.getOpcode();
1529 if (UseGP && GAOpc != HexagonISD::CONST32_GP)
1531 if (!UseGP && GAOpc != HexagonISD::CONST32)
1533 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N1)) {
1534 SDValue Addr = N0.getOperand(0);
1535 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Addr)) {
1536 if (GA->getOpcode() == ISD::TargetGlobalAddress) {
1537 uint64_t NewOff = GA->getOffset() + (uint64_t)Const->getSExtValue();
1538 R = CurDAG->getTargetGlobalAddress(GA->getGlobal(), SDLoc(Const),
1539 N.getValueType(), NewOff);
1546 case HexagonISD::CONST32:
1547 // The operand(0) of CONST32 is TargetGlobalAddress, which is what we
1548 // want in the instruction.
1550 R = N.getOperand(0);
1552 case HexagonISD::CONST32_GP:
1554 R = N.getOperand(0);
1563 bool HexagonDAGToDAGISel::isValueExtension(SDValue const &Val,
1564 unsigned FromBits, SDValue &Src) {
1565 unsigned Opc = Val.getOpcode();
1567 case ISD::SIGN_EXTEND:
1568 case ISD::ZERO_EXTEND:
1569 case ISD::ANY_EXTEND: {
1570 SDValue const &Op0 = Val.getOperand(0);
1571 EVT T = Op0.getValueType();
1572 if (T.isInteger() && T.getSizeInBits() == FromBits) {
1578 case ISD::SIGN_EXTEND_INREG:
1579 case ISD::AssertSext:
1580 case ISD::AssertZext:
1581 if (Val.getOperand(0).getValueType().isInteger()) {
1582 VTSDNode *T = cast<VTSDNode>(Val.getOperand(1));
1583 if (T->getVT().getSizeInBits() == FromBits) {
1584 Src = Val.getOperand(0);
1590 // Check if this is an AND with "FromBits" of lower bits set to 1.
1591 uint64_t FromMask = (1 << FromBits) - 1;
1592 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val.getOperand(0))) {
1593 if (C->getZExtValue() == FromMask) {
1594 Src = Val.getOperand(1);
1598 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val.getOperand(1))) {
1599 if (C->getZExtValue() == FromMask) {
1600 Src = Val.getOperand(0);
1608 // OR/XOR with the lower "FromBits" bits set to 0.
1609 uint64_t FromMask = (1 << FromBits) - 1;
1610 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val.getOperand(0))) {
1611 if ((C->getZExtValue() & FromMask) == 0) {
1612 Src = Val.getOperand(1);
1616 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val.getOperand(1))) {
1617 if ((C->getZExtValue() & FromMask) == 0) {
1618 Src = Val.getOperand(0);