1 //=- HexagonFrameLowering.h - Define frame lowering for Hexagon --*- C++ -*--=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONFRAMELOWERING_H
11 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONFRAMELOWERING_H
14 #include "llvm/Target/TargetFrameLowering.h"
18 class HexagonInstrInfo;
19 class HexagonRegisterInfo;
21 class HexagonFrameLowering : public TargetFrameLowering {
23 explicit HexagonFrameLowering()
24 : TargetFrameLowering(StackGrowsDown, 8, 0, 1, true) {}
26 // All of the prolog/epilog functionality, including saving and restoring
27 // callee-saved registers is handled in emitPrologue. This is to have the
28 // logic for shrink-wrapping in one place.
29 void emitPrologue(MachineFunction &MF) const override;
30 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const
32 bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
33 MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI,
34 const TargetRegisterInfo *TRI) const override {
37 bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
38 MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI,
39 const TargetRegisterInfo *TRI) const override {
43 void eliminateCallFramePseudoInstr(MachineFunction &MF,
44 MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override;
45 void processFunctionBeforeFrameFinalized(MachineFunction &MF,
46 RegScavenger *RS = nullptr) const override;
47 void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
48 RegScavenger *RS) const override;
50 bool targetHandlesStackFrameRounding() const override {
53 int getFrameIndexOffset(const MachineFunction &MF, int FI) const override;
54 bool hasFP(const MachineFunction &MF) const override;
56 const SpillSlot *getCalleeSavedSpillSlots(unsigned &NumEntries)
58 static const SpillSlot Offsets[] = {
59 { Hexagon::R17, -4 }, { Hexagon::R16, -8 }, { Hexagon::D8, -8 },
60 { Hexagon::R19, -12 }, { Hexagon::R18, -16 }, { Hexagon::D9, -16 },
61 { Hexagon::R21, -20 }, { Hexagon::R20, -24 }, { Hexagon::D10, -24 },
62 { Hexagon::R23, -28 }, { Hexagon::R22, -32 }, { Hexagon::D11, -32 },
63 { Hexagon::R25, -36 }, { Hexagon::R24, -40 }, { Hexagon::D12, -40 },
64 { Hexagon::R27, -44 }, { Hexagon::R26, -48 }, { Hexagon::D13, -48 }
66 NumEntries = array_lengthof(Offsets);
70 bool assignCalleeSavedSpillSlots(MachineFunction &MF,
71 const TargetRegisterInfo *TRI, std::vector<CalleeSavedInfo> &CSI)
74 bool needsAligna(const MachineFunction &MF) const;
75 MachineInstr *getAlignaInstr(MachineFunction &MF) const;
78 typedef std::vector<CalleeSavedInfo> CSIVect;
80 void expandAlloca(MachineInstr *AI, const HexagonInstrInfo &TII,
81 unsigned SP, unsigned CF) const;
82 void insertPrologueInBlock(MachineBasicBlock &MBB) const;
83 void insertEpilogueInBlock(MachineBasicBlock &MBB) const;
84 bool insertCSRSpillsInBlock(MachineBasicBlock &MBB, const CSIVect &CSI,
85 const HexagonRegisterInfo &HRI) const;
86 bool insertCSRRestoresInBlock(MachineBasicBlock &MBB, const CSIVect &CSI,
87 const HexagonRegisterInfo &HRI) const;
89 void adjustForCalleeSavedRegsSpillCall(MachineFunction &MF) const;
90 bool replacePredRegPseudoSpillCode(MachineFunction &MF) const;
91 bool replaceVecPredRegPseudoSpillCode(MachineFunction &MF) const;
93 void findShrunkPrologEpilog(MachineFunction &MF, MachineBasicBlock *&PrologB,
94 MachineBasicBlock *&EpilogB) const;
96 bool shouldInlineCSR(llvm::MachineFunction&, const CSIVect&) const;
97 bool useSpillFunction(MachineFunction &MF, const CSIVect &CSI) const;
98 bool useRestoreFunction(MachineFunction &MF, const CSIVect &CSI) const;
101 } // End llvm namespace