1 //===-- HexagonFrameLowering.cpp - Define frame lowering ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 #define DEBUG_TYPE "hexagon-pei"
13 #include "HexagonFrameLowering.h"
15 #include "HexagonInstrInfo.h"
16 #include "HexagonMachineFunctionInfo.h"
17 #include "HexagonRegisterInfo.h"
18 #include "HexagonSubtarget.h"
19 #include "HexagonTargetMachine.h"
20 #include "llvm/ADT/BitVector.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/CodeGen/AsmPrinter.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineFunctionPass.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineModuleInfo.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/RegisterScavenging.h"
30 #include "llvm/IR/Function.h"
31 #include "llvm/IR/Type.h"
32 #include "llvm/MC/MCAsmInfo.h"
33 #include "llvm/MC/MachineLocation.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/raw_ostream.h"
37 #include "llvm/Target/TargetInstrInfo.h"
38 #include "llvm/Target/TargetMachine.h"
39 #include "llvm/Target/TargetOptions.h"
41 // Hexagon stack frame layout as defined by the ABI:
47 // SP during function's FP during function's |
48 // +-- runtime (top of stack) runtime (bottom) --+ |
50 // --++---------------------+------------------+-----------------++-+-------
51 // | parameter area for | variable-size | fixed-size |LR| arg
52 // | called functions | local objects | local objects |FP|
53 // --+----------------------+------------------+-----------------+--+-------
54 // <- size known -> <- size unknown -> <- size known ->
56 // Low address High address
61 // - In any circumstances, the outgoing function arguments are always accessi-
62 // ble using the SP, and the incoming arguments are accessible using the FP.
63 // - If the local objects are not aligned, they can always be accessed using
65 // - If there are no variable-sized objects, the local objects can always be
66 // accessed using the SP, regardless whether they are aligned or not. (The
67 // alignment padding will be at the bottom of the stack (highest address),
68 // and so the offset with respect to the SP will be known at the compile-
71 // The only complication occurs if there are both, local aligned objects, and
72 // dynamically allocated (variable-sized) objects. The alignment pad will be
73 // placed between the FP and the local objects, thus preventing the use of the
74 // FP to access the local objects. At the same time, the variable-sized objects
75 // will be between the SP and the local objects, thus introducing an unknown
76 // distance from the SP to the locals.
78 // To avoid this problem, a new register is created that holds the aligned
79 // address of the bottom of the stack, referred in the sources as AP (aligned
80 // pointer). The AP will be equal to "FP-p", where "p" is the smallest pad
81 // that aligns AP to the required boundary (a maximum of the alignments of
82 // all stack objects, fixed- and variable-sized). All local objects[1] will
83 // then use AP as the base pointer.
84 // [1] The exception is with "fixed" stack objects. "Fixed" stack objects get
85 // their name from being allocated at fixed locations on the stack, relative
86 // to the FP. In the presence of dynamic allocation and local alignment, such
87 // objects can only be accessed through the FP.
89 // Illustration of the AP:
92 // ---------------+---------------------+-----+-----------------------++-+--
93 // Rest of the | Local stack objects | Pad | Fixed stack objects |LR|
94 // stack frame | (aligned) | | (CSR, spills, etc.) |FP|
95 // ---------------+---------------------+-----+-----------------+-----+--+--
96 // |<-- Multiple of the -->|
97 // stack alignment +-- AP
99 // The AP is set up at the beginning of the function. Since it is not a dedi-
100 // cated (reserved) register, it needs to be kept live throughout the function
101 // to be available as the base register for local object accesses.
102 // Normally, an address of a stack objects is obtained by a pseudo-instruction
103 // TFR_FI. To access local objects with the AP register present, a different
104 // pseudo-instruction needs to be used: TFR_FIA. The TFR_FIA takes one extra
105 // argument compared to TFR_FI: the first input register is the AP register.
106 // This keeps the register live between its definition and its uses.
108 // The AP register is originally set up using pseudo-instruction ALIGNA:
111 // A - required stack alignment
112 // The alignment value must be the maximum of all alignments required by
115 // The dynamic allocation uses a pseudo-instruction ALLOCA:
118 // Rd - address of the allocated space
119 // Rs - minimum size (the actual allocated can be larger to accommodate
121 // A - required alignment
124 using namespace llvm;
126 static cl::opt<bool> DisableDeallocRet(
127 "disable-hexagon-dealloc-ret",
129 cl::desc("Disable Dealloc Return for Hexagon target"));
132 DisableProEpilogCodeMerge("disable-hexagon-prolog-epilog-code-merge",
133 cl::Hidden, cl::desc("Disable prolog/epilog code merge"), cl::init(false),
137 NumberScavengerSlots("number-scavenger-slots",
138 cl::Hidden, cl::desc("Set the number of scavenger slots"), cl::init(2),
142 SpillFuncThreshold("spill-func-threshold",
143 cl::Hidden, cl::desc("Specify O2(not Os) spill func threshold"),
144 cl::init(6), cl::ZeroOrMore);
147 SpillFuncThresholdOs("spill-func-threshold-Os",
148 cl::Hidden, cl::desc("Specify Os spill func threshold"),
149 cl::init(1), cl::ZeroOrMore);
151 /// Map a register pair Reg to the subregister that has the greater "number",
152 /// i.e. D3 (aka R7:6) will be mapped to R7, etc.
153 static unsigned getMax32BitSubRegister(unsigned Reg,
154 const TargetRegisterInfo *TRI,
156 if (Reg < Hexagon::D0 || Reg > Hexagon::D15)
161 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
163 if (*SubRegs > RegNo)
166 if (!RegNo || *SubRegs < RegNo)
173 /// Returns the biggest callee saved register in the vector.
174 static unsigned getMaxCalleeSavedReg(const std::vector<CalleeSavedInfo> &CSI,
175 const TargetRegisterInfo *TRI) {
176 assert(Hexagon::R1 > 0 &&
177 "Assume physical registers are encoded as positive integers");
181 unsigned Max = getMax32BitSubRegister(CSI[0].getReg(), TRI);
182 for (unsigned I = 1, E = CSI.size(); I < E; ++I) {
183 unsigned Reg = getMax32BitSubRegister(CSI[I].getReg(), TRI);
191 void HexagonFrameLowering::emitPrologue(MachineFunction &MF) const {
192 MachineBasicBlock &MBB = MF.front();
193 MachineFrameInfo *MFI = MF.getFrameInfo();
194 MachineModuleInfo &MMI = MF.getMMI();
195 MachineBasicBlock::iterator MBBI = MBB.begin();
196 auto &HTM = static_cast<const HexagonTargetMachine&>(MF.getTarget());
197 auto &HST = static_cast<const HexagonSubtarget&>(MF.getSubtarget());
198 auto &HII = *HST.getInstrInfo();
199 auto &HRI = *HST.getRegisterInfo();
202 unsigned MaxAlign = std::max(MFI->getMaxAlignment(), getStackAlignment());
204 // Calculate the total stack frame size.
205 // Get the number of bytes to allocate from the FrameInfo.
206 unsigned FrameSize = MFI->getStackSize();
207 // Round up the max call frame size to the max alignment on the stack.
208 unsigned MaxCFA = RoundUpToAlignment(MFI->getMaxCallFrameSize(), MaxAlign);
209 MFI->setMaxCallFrameSize(MaxCFA);
211 FrameSize = MaxCFA + RoundUpToAlignment(FrameSize, MaxAlign);
212 MFI->setStackSize(FrameSize);
214 bool AlignStack = (MaxAlign > 8);
216 // Check if frame moves are needed for EH.
217 bool needsFrameMoves = MMI.hasDebugInfo() ||
218 MF.getFunction()->needsUnwindTableEntry();
220 // Get the number of bytes to allocate from the FrameInfo.
221 unsigned NumBytes = MFI->getStackSize();
222 unsigned SP = HRI.getStackRegister();
223 unsigned MaxCF = MFI->getMaxCallFrameSize();
224 MachineBasicBlock::iterator InsertPt = MBB.begin();
226 auto *FuncInfo = MF.getInfo<HexagonMachineFunctionInfo>();
227 auto &AdjustRegs = FuncInfo->getAllocaAdjustInsts();
229 for (auto MI : AdjustRegs) {
230 assert((MI->getOpcode() == Hexagon::ALLOCA) && "Expected alloca");
231 expandAlloca(MI, HII, SP, MaxCF);
232 MI->eraseFromParent();
236 // Only insert ALLOCFRAME if we need to or at -O0 for the debugger. Think
237 // that this shouldn't be required, but doing so now because gcc does and
238 // gdb can't break at the start of the function without it. Will remove if
239 // this turns out to be a gdb bug.
241 bool NoOpt = (HTM.getOptLevel() == CodeGenOpt::None);
242 if (!NoOpt && !FuncInfo->hasClobberLR() && !hasFP(MF))
245 // Check for overflow.
246 // Hexagon_TODO: Ugh! hardcoding. Is there an API that can be used?
247 const unsigned int ALLOCFRAME_MAX = 16384;
249 // Create a dummy memory operand to avoid allocframe from being treated as
250 // a volatile memory reference.
251 MachineMemOperand *MMO =
252 MF.getMachineMemOperand(MachinePointerInfo(), MachineMemOperand::MOStore,
255 if (NumBytes >= ALLOCFRAME_MAX) {
256 // Emit allocframe(#0).
257 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::S2_allocframe))
261 // Subtract offset from frame pointer.
262 // We use a caller-saved non-parameter register for that.
263 unsigned CallerSavedReg = HRI.getFirstCallerSavedNonParamReg();
264 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::CONST32_Int_Real),
265 CallerSavedReg).addImm(NumBytes);
266 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_sub), SP).
268 addReg(CallerSavedReg);
270 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::S2_allocframe))
276 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_andir), SP)
278 .addImm(-int64_t(MaxAlign));
281 if (needsFrameMoves) {
282 std::vector<MCCFIInstruction> Instructions = MMI.getFrameInstructions();
283 MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol();
285 // Advance CFA. DW_CFA_def_cfa
286 unsigned DwFPReg = HRI.getDwarfRegNum(HRI.getFrameRegister(), true);
287 unsigned DwRAReg = HRI.getDwarfRegNum(HRI.getRARegister(), true);
290 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createDefCfa(
291 FrameLabel, DwFPReg, -8));
292 BuildMI(MBB, MBBI, dl, HII.get(TargetOpcode::CFI_INSTRUCTION))
293 .addCFIIndex(CFIIndex);
295 // R31 (return addr) = CFA - #4
296 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
297 FrameLabel, DwRAReg, -4));
298 BuildMI(MBB, MBBI, dl, HII.get(TargetOpcode::CFI_INSTRUCTION))
299 .addCFIIndex(CFIIndex);
301 // R30 (frame ptr) = CFA - #8)
302 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
303 FrameLabel, DwFPReg, -8));
304 BuildMI(MBB, MBBI, dl, HII.get(TargetOpcode::CFI_INSTRUCTION))
305 .addCFIIndex(CFIIndex);
307 unsigned int regsToMove[] = {
308 Hexagon::R1, Hexagon::R0, Hexagon::R3, Hexagon::R2,
309 Hexagon::R17, Hexagon::R16, Hexagon::R19, Hexagon::R18,
310 Hexagon::R21, Hexagon::R20, Hexagon::R23, Hexagon::R22,
311 Hexagon::R25, Hexagon::R24, Hexagon::R27, Hexagon::R26,
312 Hexagon::D0, Hexagon::D1, Hexagon::D8, Hexagon::D9, Hexagon::D10,
313 Hexagon::D11, Hexagon::D12, Hexagon::D13, Hexagon::NoRegister
316 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
318 for (unsigned i = 0; regsToMove[i] != Hexagon::NoRegister; ++i) {
319 for (unsigned I = 0, E = CSI.size(); I < E; ++I) {
320 if (CSI[I].getReg() == regsToMove[i]) {
321 // Subtract 8 to make room for R30 and R31, which are added above.
322 int64_t Offset = getFrameIndexOffset(MF, CSI[I].getFrameIdx()) - 8;
324 if (regsToMove[i] < Hexagon::D0 || regsToMove[i] > Hexagon::D15) {
325 unsigned DwarfReg = HRI.getDwarfRegNum(regsToMove[i], true);
326 unsigned CFIIndex = MMI.addFrameInst(
327 MCCFIInstruction::createOffset(FrameLabel,
329 BuildMI(MBB, MBBI, dl, HII.get(TargetOpcode::CFI_INSTRUCTION))
330 .addCFIIndex(CFIIndex);
332 // Split the double regs into subregs, and generate appropriate
334 // The only reason, we are split double regs is, llvm-mc does not
335 // understand paired registers for cfi_offset.
336 // Eg .cfi_offset r1:0, -64
337 unsigned HiReg = getMax32BitSubRegister(regsToMove[i], &HRI);
338 unsigned LoReg = getMax32BitSubRegister(regsToMove[i], &HRI, false);
339 unsigned HiDwarfReg = HRI.getDwarfRegNum(HiReg, true);
340 unsigned LoDwarfReg = HRI.getDwarfRegNum(LoReg, true);
341 unsigned HiCFIIndex = MMI.addFrameInst(
342 MCCFIInstruction::createOffset(FrameLabel,
343 HiDwarfReg, Offset+4));
344 BuildMI(MBB, MBBI, dl, HII.get(TargetOpcode::CFI_INSTRUCTION))
345 .addCFIIndex(HiCFIIndex);
346 unsigned LoCFIIndex = MMI.addFrameInst(
347 MCCFIInstruction::createOffset(FrameLabel,
348 LoDwarfReg, Offset));
349 BuildMI(MBB, MBBI, dl, HII.get(TargetOpcode::CFI_INSTRUCTION))
350 .addCFIIndex(LoCFIIndex);
359 // Returns true if MBB has a machine instructions that indicates a tail call
361 bool HexagonFrameLowering::hasTailCall(MachineBasicBlock &MBB) const {
362 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
363 unsigned RetOpcode = MBBI->getOpcode();
365 return RetOpcode == Hexagon::TCRETURNi || RetOpcode == Hexagon::TCRETURNr;
368 void HexagonFrameLowering::emitEpilogue(MachineFunction &MF,
369 MachineBasicBlock &MBB) const {
371 // Only insert deallocframe if we need to. Also at -O0. See comment
372 // in emitPrologue above.
374 if (!hasFP(MF) && MF.getTarget().getOptLevel() != CodeGenOpt::None)
377 auto &HST = static_cast<const HexagonSubtarget&>(MF.getSubtarget());
378 auto &HII = *HST.getInstrInfo();
380 MachineBasicBlock::iterator MBBI = std::prev(MBB.end());
381 MachineBasicBlock::iterator MBBI_end = MBB.end();
382 DebugLoc dl = MBBI->getDebugLoc();
385 if (MBBI->getOpcode() == Hexagon::EH_RETURN_JMPR) {
386 MachineOperand &OffsetReg = MBBI->getOperand(0);
387 assert(OffsetReg.isReg() && "Offset should be in register!");
388 BuildMI(MBB, MBBI, dl, HII.get(Hexagon::L2_deallocframe));
389 BuildMI(MBB, MBBI, dl, HII.get(Hexagon::A2_add),
390 Hexagon::R29).addReg(Hexagon::R29).addReg(Hexagon::R28);
393 // Replace 'jumpr r31' instruction with dealloc_return for V4 and higher
395 if (MBBI->getOpcode() == Hexagon::JMPret && !DisableDeallocRet) {
396 // Check for RESTORE_DEALLOC_RET_JMP_V4 call. Don't emit an extra DEALLOC
397 // instruction if we encounter it.
398 MachineBasicBlock::iterator BeforeJMPR =
399 MBB.begin() == MBBI ? MBBI : std::prev(MBBI);
400 if (BeforeJMPR != MBBI &&
401 BeforeJMPR->getOpcode() == Hexagon::RESTORE_DEALLOC_RET_JMP_V4) {
402 // Remove the JMPR node.
407 // Add dealloc_return.
408 MachineInstrBuilder MIB =
409 BuildMI(MBB, MBBI_end, dl, HII.get(Hexagon::L4_return));
410 // Transfer the function live-out registers.
411 MIB->copyImplicitOps(*MBB.getParent(), &*MBBI);
412 // Remove the JUMPR node.
414 } else { // Add deallocframe for tail calls.
415 // Check for RESTORE_DEALLOC_BEFORE_TAILCALL_V4. We don't need an extra
416 // L2_deallocframe instruction after it.
417 MachineBasicBlock::iterator Term = MBB.getFirstTerminator();
418 MachineBasicBlock::iterator I =
419 Term == MBB.begin() ? MBB.end() : std::prev(Term);
420 if (I != MBB.end() &&
421 I->getOpcode() == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4)
424 BuildMI(MBB, MBBI, dl, HII.get(Hexagon::L2_deallocframe));
428 bool HexagonFrameLowering::hasFP(const MachineFunction &MF) const {
429 const MachineFrameInfo *MFI = MF.getFrameInfo();
430 const HexagonMachineFunctionInfo *FuncInfo =
431 MF.getInfo<HexagonMachineFunctionInfo>();
432 return (MFI->hasCalls() || (MFI->getStackSize() > 0) ||
433 FuncInfo->hasClobberLR() );
443 getSpillFunctionFor(unsigned MaxReg, SpillKind SpillType) {
444 const char * V4SpillToMemoryFunctions[] = {
445 "__save_r16_through_r17",
446 "__save_r16_through_r19",
447 "__save_r16_through_r21",
448 "__save_r16_through_r23",
449 "__save_r16_through_r25",
450 "__save_r16_through_r27" };
452 const char * V4SpillFromMemoryFunctions[] = {
453 "__restore_r16_through_r17_and_deallocframe",
454 "__restore_r16_through_r19_and_deallocframe",
455 "__restore_r16_through_r21_and_deallocframe",
456 "__restore_r16_through_r23_and_deallocframe",
457 "__restore_r16_through_r25_and_deallocframe",
458 "__restore_r16_through_r27_and_deallocframe" };
460 const char * V4SpillFromMemoryTailcallFunctions[] = {
461 "__restore_r16_through_r17_and_deallocframe_before_tailcall",
462 "__restore_r16_through_r19_and_deallocframe_before_tailcall",
463 "__restore_r16_through_r21_and_deallocframe_before_tailcall",
464 "__restore_r16_through_r23_and_deallocframe_before_tailcall",
465 "__restore_r16_through_r25_and_deallocframe_before_tailcall",
466 "__restore_r16_through_r27_and_deallocframe_before_tailcall"
469 const char **SpillFunc = nullptr;
473 SpillFunc = V4SpillToMemoryFunctions;
476 SpillFunc = V4SpillFromMemoryFunctions;
478 case SK_FromMemTailcall:
479 SpillFunc = V4SpillFromMemoryTailcallFunctions;
482 assert(SpillFunc && "Unknown spill kind");
484 // Spill all callee-saved registers up to the highest register used.
499 assert(false && "Unhandled maximum callee save register");
505 /// Adds all callee-saved registers up to MaxReg to the instruction.
506 static void addCalleeSaveRegistersAsImpOperand(MachineInstr *Inst,
507 unsigned MaxReg, bool IsDef) {
508 // Add the callee-saved registers as implicit uses.
509 for (unsigned R = Hexagon::R16; R <= MaxReg; ++R) {
510 MachineOperand ImpUse = MachineOperand::CreateReg(R, IsDef, true);
511 Inst->addOperand(ImpUse);
515 /// Returns true if we have V4 operations, optimization level is equal to
516 /// O2 or Os and exception handling is not required.
517 static bool shouldOptimizeForSize(MachineFunction &MF) {
518 if (MF.getInfo<HexagonMachineFunctionInfo>()->hasEHReturn())
521 if (MF.getTarget().getOptLevel() == CodeGenOpt::Default) /* -O2 or -Os */
524 const Function *F = MF.getFunction();
525 if (F->hasFnAttribute(Attribute::MinSize))
528 return F->hasFnAttribute(Attribute::OptimizeForSize);
532 HexagonFrameLowering::spillCalleeSavedRegisters(
533 MachineBasicBlock &MBB,
534 MachineBasicBlock::iterator MI,
535 const std::vector<CalleeSavedInfo> &CSI,
536 const TargetRegisterInfo *TRI) const {
537 MachineFunction *MF = MBB.getParent();
538 const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();
539 const HexagonRegisterInfo *HRI =
540 static_cast<const HexagonRegisterInfo*>(TRI);
546 // Check whether we should emit a function call to spill the registers.
547 bool ShouldOptimizeForSize = shouldOptimizeForSize(*MF);
549 if (ShouldOptimizeForSize && !DisableProEpilogCodeMerge) {
550 // We have different cut offs when we use callee saved stubs at -Os.
551 bool HasOptimizeForSizeAttr = MF->getFunction()->getAttributes()
552 .hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
553 unsigned CalleeSavedStubCutOff = HasOptimizeForSizeAttr ?
554 SpillFuncThresholdOs : SpillFuncThreshold;
556 // Use a function call if we have to spill registers.
557 if (CSI.size() > CalleeSavedStubCutOff) {
558 unsigned MaxReg = getMaxCalleeSavedReg(CSI, TRI);
559 const char *SpillFun = getSpillFunctionFor(MaxReg, SK_ToMem);
560 // Call spill function.
561 DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc();
562 MachineInstr *SaveRegsCall =
563 BuildMI(MBB, MI, DL, TII.get(Hexagon::SAVE_REGISTERS_CALL_V4))
564 .addExternalSymbol(SpillFun);
565 // Add callee-saved registers as use.
566 addCalleeSaveRegistersAsImpOperand(SaveRegsCall, MaxReg, false);
567 // Add live in registers.
568 for (unsigned I = 0; I < CSI.size(); ++I)
569 MBB.addLiveIn(CSI[I].getReg());
574 for (unsigned i = 0; i < CSI.size(); ++i) {
575 unsigned Reg = CSI[i].getReg();
576 // Add live in registers. We treat eh_return callee saved register r0 - r3
577 // specially. They are not really callee saved registers as they are not
578 // supposed to be killed.
579 bool IsEHReturnCalleeSavedReg = HRI->isEHReturnCalleeSaveReg(Reg);
581 if (HRI->isCalleeSaveReg(Reg)) {
582 int FrameIdx = CSI[i].getFrameIdx();
583 const TargetRegisterClass *RegClass =
584 TRI->getMinimalPhysRegClass(Reg);
585 TII.storeRegToStackSlot(MBB, MI, Reg, !IsEHReturnCalleeSavedReg,
586 FrameIdx, RegClass, TRI);
587 if (!IsEHReturnCalleeSavedReg)
590 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
591 TII.storeRegToStackSlot(MBB, MI, Reg, !IsEHReturnCalleeSavedReg,
592 CSI[i].getFrameIdx(), RC, TRI);
593 if (!IsEHReturnCalleeSavedReg)
601 bool HexagonFrameLowering::restoreCalleeSavedRegisters(
602 MachineBasicBlock &MBB,
603 MachineBasicBlock::iterator MI,
604 const std::vector<CalleeSavedInfo> &CSI,
605 const TargetRegisterInfo *TRI) const {
607 MachineFunction *MF = MBB.getParent();
608 const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();
614 // Check whether we should emit a function call to spill the registers.
615 bool ShouldOptimizeForSize = shouldOptimizeForSize(*MF);
617 if (ShouldOptimizeForSize && !DisableProEpilogCodeMerge) {
618 // We have different cut offs when we use callee saved stubs at -Os.
619 bool HasOptimizeForSizeAttr = MF->getFunction()->getAttributes()
620 .hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
621 unsigned CalleeSavedStubCutOff = HasOptimizeForSizeAttr ?
622 (SpillFuncThresholdOs - 1) : SpillFuncThreshold;
624 // Use a function call if we have to spill registers.
625 if (CSI.size() > CalleeSavedStubCutOff) {
626 bool IsTailCallBB = hasTailCall(MBB);
627 unsigned MaxReg = getMaxCalleeSavedReg(CSI, TRI);
628 const char *SpillFun =
629 getSpillFunctionFor(MaxReg, IsTailCallBB ?
630 SK_FromMemTailcall : SK_FromMem);
632 // Call spill function.
633 DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc();
634 MachineInstr *DeallocCall = nullptr;
637 DeallocCall = BuildMI(MBB, MI, DL,
638 TII.get(Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4))
639 .addExternalSymbol(SpillFun);
642 MachineBasicBlock::iterator JumprInst = std::prev(MBB.end());
643 assert(JumprInst->getOpcode() == Hexagon::JMPret);
645 BuildMI(MBB, MI, DL, TII.get(Hexagon::RESTORE_DEALLOC_RET_JMP_V4))
646 .addExternalSymbol(SpillFun);
647 // Transfer the function live-out registers.
648 DeallocCall->copyImplicitOps(*MBB.getParent(), JumprInst);
650 addCalleeSaveRegistersAsImpOperand(DeallocCall, MaxReg, true);
655 const HexagonRegisterInfo *HRI =
656 static_cast<const HexagonRegisterInfo*>(TRI);
658 for (unsigned i = 0; i < CSI.size(); ++i) {
659 unsigned Reg = CSI[i].getReg();
660 // Add live in registers. We treat eh_return callee saved register r0 - r3
661 // specially. They are not really callee saved registers as they are not
662 // supposed to be killed.
663 bool IsEHReturnCalleeSavedReg = HRI->isEHReturnCalleeSaveReg(Reg);
665 if (HRI->isCalleeSaveReg(Reg)) {
666 int FrameIdx = CSI[i].getFrameIdx();
667 const TargetRegisterClass *RegClass =
668 TRI->getMinimalPhysRegClass(Reg);
669 TII.loadRegFromStackSlot(MBB, MI, Reg, FrameIdx,
672 if (!IsEHReturnCalleeSavedReg)
676 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
677 TII.loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RC, TRI);
678 if (!IsEHReturnCalleeSavedReg)
685 void HexagonFrameLowering::
686 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
687 MachineBasicBlock::iterator I) const {
688 MachineInstr &MI = *I;
689 unsigned Opc = MI.getOpcode();
690 assert((Opc == Hexagon::ADJCALLSTACKDOWN || Opc == Hexagon::ADJCALLSTACKUP) &&
691 "Cannot handle this call frame pseudo instruction");
695 int HexagonFrameLowering::getFrameIndexOffset(const MachineFunction &MF,
697 return MF.getFrameInfo()->getObjectOffset(FI);
700 void HexagonFrameLowering::processFunctionBeforeFrameFinalized(
701 MachineFunction &MF, RegScavenger *RS) const {
702 // If this function has uses aligned stack and also has variable sized stack
703 // objects, then we need to map all spill slots to fixed positions, so that
704 // they can be accessed through FP. Otherwise they would have to be accessed
705 // via AP, which may not be available at the particular place in the program.
706 MachineFrameInfo *MFI = MF.getFrameInfo();
707 bool HasAlloca = MFI->hasVarSizedObjects();
708 bool HasAligna = (MFI->getMaxAlignment() > getStackAlignment());
710 if (!HasAlloca || !HasAligna)
713 unsigned LFS = MFI->getLocalFrameSize();
715 for (int i = 0, e = MFI->getObjectIndexEnd(); i != e; ++i) {
716 if (!MFI->isSpillSlotObjectIndex(i) || MFI->isDeadObjectIndex(i))
718 int S = MFI->getObjectSize(i);
721 MFI->mapLocalFrameObject(i, Offset);
724 MFI->setLocalFrameSize(LFS);
725 unsigned A = MFI->getLocalFrameMaxAlign();
726 assert(A <= 8 && "Unexpected local frame alignment");
728 MFI->setLocalFrameMaxAlign(8);
729 MFI->setUseLocalStackAllocationBlock(true);
732 /// Returns true if there is no caller saved registers available.
733 static bool needToReserveScavengingSpillSlots(MachineFunction &MF,
734 const HexagonRegisterInfo &HRI) {
735 MachineRegisterInfo &MRI = MF.getRegInfo();
736 const uint16_t *CallerSavedRegs = HRI.getCallerSavedRegs(&MF);
737 // Check for an unused caller-saved register.
738 for ( ; *CallerSavedRegs; ++CallerSavedRegs) {
739 unsigned FreeReg = *CallerSavedRegs;
740 if (MRI.isPhysRegUsed(FreeReg))
743 // Check aliased register usage.
744 bool IsCurrentRegUsed = false;
745 for (MCRegAliasIterator AI(FreeReg, &HRI, false); AI.isValid(); ++AI)
746 if (MRI.isPhysRegUsed(*AI)) {
747 IsCurrentRegUsed = true;
750 if (IsCurrentRegUsed)
753 // Neither directly used nor used through an aliased register.
756 // All caller-saved registers are used.
760 /// Marks physical registers as used so that the callee-saved registers are
761 /// always a multiple of two.
762 void HexagonFrameLowering::
763 adjustForCalleeSavedRegsSpillCall(MachineFunction &MF) const {
764 // We need to pretend that the callee-saved registers are a multiple of two
765 // because there are only library functions to handle those cases.
766 // (save_r16_to_17, save_r16_to_r19, ...)
767 MachineRegisterInfo &MRI = MF.getRegInfo();
768 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
769 const uint16_t *CSRegs = TRI.getCalleeSavedRegs(&MF);
771 // Compute the smallest and biggest callee-saved register used.
772 unsigned Biggest = 0;
773 unsigned Smallest = Hexagon::R31;
774 unsigned NumUsed = 0;
775 for (; *CSRegs; ++CSRegs){
776 unsigned CurrCSR = *CSRegs;
777 if (MRI.isPhysRegUsed(CurrCSR)) {
779 if (CurrCSR >= Biggest)
781 if (CurrCSR <= Smallest)
785 // Also check alias registers.
786 for (MCRegAliasIterator AI(CurrCSR, &TRI, false); AI.isValid(); ++AI) {
787 if (MRI.isPhysRegUsed(*AI)) {
789 if (CurrCSR >= Biggest)
791 if (CurrCSR <= Smallest)
798 // Don't do anything if the number of register used is zero.
802 // Ensure that the biggest register is r17, r19, ...
803 if ((Biggest - Hexagon::R0) % 2 == 0)
805 assert(Smallest != Hexagon::R31 && "Should not happen");
806 // Make sure all the physical register are marked as used so that they are
807 // assigned stack slots.
808 for (unsigned I = Smallest; I <= Biggest; ++I)
809 if (!MRI.isPhysRegUsed(I))
810 MRI.setPhysRegUsed(I);
813 /// Replaces the predicate spill code pseudo instructions by valid instructions.
814 bool HexagonFrameLowering::replacePredRegPseudoSpillCode(MachineFunction &MF)
816 auto &HST = static_cast<const HexagonSubtarget&>(MF.getSubtarget());
817 auto &HII = *HST.getInstrInfo();
818 MachineRegisterInfo &MRI = MF.getRegInfo();
819 bool HasReplacedPseudoInst = false;
820 // Replace predicate spill pseudo instructions by real code.
821 // Loop over all of the basic blocks.
822 for (MachineFunction::iterator MBBb = MF.begin(), MBBe = MF.end();
823 MBBb != MBBe; ++MBBb) {
824 MachineBasicBlock* MBB = MBBb;
825 // Traverse the basic block.
826 MachineBasicBlock::iterator NextII;
827 for (MachineBasicBlock::iterator MII = MBB->begin(); MII != MBB->end();
829 MachineInstr *MI = MII;
830 NextII = std::next(MII);
831 int Opc = MI->getOpcode();
832 if (Opc == Hexagon::STriw_pred) {
833 HasReplacedPseudoInst = true;
834 // STriw_pred FI, 0, SrcReg;
835 unsigned VirtReg = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
836 unsigned SrcReg = MI->getOperand(2).getReg();
837 bool IsOrigSrcRegKilled = MI->getOperand(2).isKill();
839 assert(MI->getOperand(0).isFI() && "Expect a frame index");
840 assert(Hexagon::PredRegsRegClass.contains(SrcReg) &&
841 "Not a predicate register");
843 // Insert transfer to general purpose register.
844 // VirtReg = C2_tfrpr SrcPredReg
845 BuildMI(*MBB, MII, MI->getDebugLoc(), HII.get(Hexagon::C2_tfrpr),
846 VirtReg).addReg(SrcReg, getKillRegState(IsOrigSrcRegKilled));
848 // Change instruction to S2_storeri_io.
849 // S2_storeri_io FI, 0, VirtReg
850 MI->setDesc(HII.get(Hexagon::S2_storeri_io));
851 MI->getOperand(2).setReg(VirtReg);
852 MI->getOperand(2).setIsKill();
854 } else if (Opc == Hexagon::LDriw_pred) {
855 // DstReg = LDriw_pred FI, 0
856 MachineOperand &M0 = MI->getOperand(0);
862 unsigned VirtReg = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
863 unsigned DestReg = MI->getOperand(0).getReg();
865 assert(MI->getOperand(1).isFI() && "Expect a frame index");
866 assert(Hexagon::PredRegsRegClass.contains(DestReg) &&
867 "Not a predicate register");
869 // Change instruction to L2_loadri_io.
870 // VirtReg = L2_loadri_io FI, 0
871 MI->setDesc(HII.get(Hexagon::L2_loadri_io));
872 MI->getOperand(0).setReg(VirtReg);
874 // Insert transfer to general purpose register.
875 // DestReg = C2_tfrrp VirtReg
876 const MCInstrDesc &D = HII.get(Hexagon::C2_tfrrp);
877 BuildMI(*MBB, std::next(MII), MI->getDebugLoc(), D, DestReg)
878 .addReg(VirtReg, getKillRegState(true));
879 HasReplacedPseudoInst = true;
883 return HasReplacedPseudoInst;
886 void HexagonFrameLowering::processFunctionBeforeCalleeSavedScan(
887 MachineFunction &MF, RegScavenger* RS) const {
888 auto &HST = static_cast<const HexagonSubtarget&>(MF.getSubtarget());
889 auto &HRI = *HST.getRegisterInfo();
891 bool HasEHReturn = MF.getInfo<HexagonMachineFunctionInfo>()->hasEHReturn();
893 // If we have a function containing __builtin_eh_return we want to spill and
894 // restore all callee saved registers. Pretend that they are used.
896 MachineRegisterInfo &MRI = MF.getRegInfo();
897 for (const uint16_t *CSRegs = HRI.getCalleeSavedRegs(&MF); *CSRegs;
899 if (!MRI.isPhysRegUsed(*CSRegs))
900 MRI.setPhysRegUsed(*CSRegs);
903 const TargetRegisterClass &RC = Hexagon::IntRegsRegClass;
905 // Replace predicate register pseudo spill code.
906 bool HasReplacedPseudoInst = replacePredRegPseudoSpillCode(MF);
908 // We need to reserve a a spill slot if scavenging could potentially require
909 // spilling a scavenged register.
910 if (HasReplacedPseudoInst && needToReserveScavengingSpillSlots(MF, HRI)) {
911 MachineFrameInfo *MFI = MF.getFrameInfo();
912 for (int i=0; i < NumberScavengerSlots; i++)
913 RS->addScavengingFrameIndex(
914 MFI->CreateSpillStackObject(RC.getSize(), RC.getAlignment()));
917 bool ShouldOptimizeForSize = shouldOptimizeForSize(MF);
919 // Do nothing if we are not optimizing for size.
920 if (!ShouldOptimizeForSize || DisableProEpilogCodeMerge)
923 // Adjust the used callee save registers to be a multiple of two as there are
924 // only library functions for them.
925 adjustForCalleeSavedRegsSpillCall(MF);
928 bool HexagonFrameLowering::assignCalleeSavedSpillSlots(MachineFunction &MF,
929 const TargetRegisterInfo *TRI, std::vector<CalleeSavedInfo> &CSI) const {
930 const Function &F = *MF.getFunction();
931 DEBUG(dbgs() << LLVM_FUNCTION_NAME << " on " << F.getName() << '\n');
932 MachineFrameInfo *MFI = MF.getFrameInfo();
933 unsigned NR = TRI->getNumRegs();
936 // Generate a set of unique, callee-saved registers (SRegs), where each
937 // register in the set is maximal in terms of sub-/super-register relation,
938 // i.e. for each R in SRegs, no proper super-register of R is also in SRegs.
940 // 1a. For each callee-saved register, add that register to SRegs.
941 DEBUG(dbgs() << "Initial CS registers: {");
942 for (unsigned i = 0, n = CSI.size(); i < n; ++i) {
943 unsigned R = CSI[i].getReg();
944 DEBUG(dbgs() << ' ' << PrintReg(R, TRI));
945 for (MCSubRegIterator SR(R, TRI, true); SR.isValid(); ++SR)
948 DEBUG(dbgs() << " }\n");
950 // 1b. Collect all registers that have at least one sub-registers in SRegs.
951 BitVector TmpSup(NR);
952 for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
954 for (MCSuperRegIterator SR(R, TRI); SR.isValid(); ++SR)
957 // 1c. Out of all the super-registers found in 1b, add to SRegs those of
958 // them, whose all sub-registers are already in SReg, or will be added to
959 // SReg (i.e. are in TmpSup).
960 // At the end of this step, the following will be true:
961 // R \in SRegs => (if S is sub-register of R, then S \in SRegs)
962 // S1..Sn = { sub-registers of R }, and S1..Sn \in SRegs => R \in SRegs
963 for (int x = TmpSup.find_first(); x >= 0; x = TmpSup.find_next(x)) {
966 for (MCSubRegIterator SR(R, TRI); SR.isValid(); ++SR) {
967 if (SRegs[*SR] || TmpSup[*SR])
972 // On Hexagon, a super-register is covered by its sub-registers.
977 // 2. For each reserved register, remove that register and all of its
978 // sub- and super-registers from SRegs.
979 BitVector Reserved = TRI->getReservedRegs(MF);
980 for (int x = Reserved.find_first(); x >= 0; x = Reserved.find_next(x)) {
982 for (MCSubRegIterator SR(R, TRI, true); SR.isValid(); ++SR)
984 for (MCSuperRegIterator SR(R, TRI); SR.isValid(); ++SR)
988 // 3. For each register R in SRegs, if any super-register of R is in SRegs,
989 // remove R from SRegs.
990 for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
992 for (MCSuperRegIterator SR(R, TRI); SR.isValid(); ++SR) {
1000 // Now, for each register that has a fixed stack slot, create the stack
1004 typedef TargetFrameLowering::SpillSlot SpillSlot;
1006 int MinOffset = 0; // CS offsets are negative.
1007 const SpillSlot *FixedSlots = getCalleeSavedSpillSlots(NumFixed);
1008 for (const SpillSlot *S = FixedSlots; S != FixedSlots+NumFixed; ++S) {
1011 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(S->Reg);
1012 int FI = MFI->CreateFixedSpillStackObject(RC->getSize(), S->Offset);
1013 MinOffset = std::min(MinOffset, S->Offset);
1014 CSI.push_back(CalleeSavedInfo(S->Reg, FI));
1015 SRegs[S->Reg] = false;
1018 // There can be some registers that don't have fixed slots. For example,
1019 // we need to store R0-R3 in functions with exception handling. For each
1020 // such register, create a non-fixed stack object.
1021 for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
1023 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(R);
1024 int Off = MinOffset - RC->getSize();
1025 unsigned Align = std::min(RC->getAlignment(), getStackAlignment());
1026 assert(isPowerOf2_32(Align));
1028 int FI = MFI->CreateFixedSpillStackObject(RC->getSize(), Off);
1029 MinOffset = std::min(MinOffset, Off);
1030 CSI.push_back(CalleeSavedInfo(R, FI));
1035 dbgs() << "CS information: {";
1036 for (unsigned i = 0, n = CSI.size(); i < n; ++i) {
1037 int FI = CSI[i].getFrameIdx();
1038 int Off = MFI->getObjectOffset(FI);
1039 dbgs() << ' ' << PrintReg(CSI[i].getReg(), TRI) << ":fi#" << FI << ":sp";
1048 // Verify that all registers were handled.
1049 bool MissedReg = false;
1050 for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
1052 dbgs() << PrintReg(R, TRI) << ' ';
1056 llvm_unreachable("...there are unhandled callee-saved registers!");
1062 void HexagonFrameLowering::expandAlloca(MachineInstr *AI,
1063 const HexagonInstrInfo &TII, unsigned SP, unsigned CF) const {
1064 MachineBasicBlock &MB = *AI->getParent();
1065 DebugLoc DL = AI->getDebugLoc();
1066 unsigned A = AI->getOperand(2).getImm();
1069 // Rd = alloca Rs, #A
1071 // If Rs and Rd are different registers, use this sequence:
1072 // Rd = sub(r29, Rs)
1073 // r29 = sub(r29, Rs)
1074 // Rd = and(Rd, #-A) ; if necessary
1075 // r29 = and(r29, #-A) ; if necessary
1076 // Rd = add(Rd, #CF) ; CF size aligned to at most A
1078 // Rd = sub(r29, Rs)
1079 // Rd = and(Rd, #-A) ; if necessary
1081 // Rd = add(Rd, #CF) ; CF size aligned to at most A
1083 MachineOperand &RdOp = AI->getOperand(0);
1084 MachineOperand &RsOp = AI->getOperand(1);
1085 unsigned Rd = RdOp.getReg(), Rs = RsOp.getReg();
1087 // Rd = sub(r29, Rs)
1088 BuildMI(MB, AI, DL, TII.get(Hexagon::A2_sub), Rd)
1092 // r29 = sub(r29, Rs)
1093 BuildMI(MB, AI, DL, TII.get(Hexagon::A2_sub), SP)
1098 // Rd = and(Rd, #-A)
1099 BuildMI(MB, AI, DL, TII.get(Hexagon::A2_andir), Rd)
1101 .addImm(-int64_t(A));
1103 BuildMI(MB, AI, DL, TII.get(Hexagon::A2_andir), SP)
1105 .addImm(-int64_t(A));
1109 BuildMI(MB, AI, DL, TII.get(TargetOpcode::COPY), SP)
1113 // Rd = add(Rd, #CF)
1114 BuildMI(MB, AI, DL, TII.get(Hexagon::A2_addi), Rd)
1120 bool HexagonFrameLowering::needsAligna(const MachineFunction &MF) const {
1121 const MachineFrameInfo *MFI = MF.getFrameInfo();
1122 if (!MFI->hasVarSizedObjects())
1124 unsigned MaxA = MFI->getMaxAlignment();
1125 if (MaxA <= getStackAlignment())
1130 MachineInstr *HexagonFrameLowering::getAlignaInstr(MachineFunction &MF) const {
1133 if (I.getOpcode() == Hexagon::ALIGNA)