1 //===- SPUSubtarget.cpp - STI Cell SPU Subtarget Information --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the CellSPU-specific subclass of TargetSubtarget.
12 //===----------------------------------------------------------------------===//
14 #include "SPUSubtarget.h"
16 #include "SPUGenSubtarget.inc"
17 #include "llvm/ADT/SmallVector.h"
18 #include "SPURegisterInfo.h"
22 SPUSubtarget::SPUSubtarget(const std::string &TT, const std::string &CPU,
23 const std::string &FS) :
25 ProcDirective(SPU::DEFAULT_PROC),
28 // Should be the target SPU processor type. For now, since there's only
29 // one, simply default to the current "v0" default:
30 std::string default_cpu("v0");
32 // Parse features string.
33 ParseSubtargetFeatures(FS, default_cpu);
36 /// SetJITMode - This is called to inform the subtarget info that we are
37 /// producing code for the JIT.
38 void SPUSubtarget::SetJITMode() {
41 /// Enable PostRA scheduling for optimization levels -O2 and -O3.
42 bool SPUSubtarget::enablePostRAScheduler(
43 CodeGenOpt::Level OptLevel,
44 TargetSubtarget::AntiDepBreakMode& Mode,
45 RegClassVector& CriticalPathRCs) const {
46 Mode = TargetSubtarget::ANTIDEP_CRITICAL;
47 // CriticalPathsRCs seems to be the set of
48 // RegisterClasses that antidep breakings are performed for.
49 // Do it for all register classes
50 CriticalPathRCs.clear();
51 CriticalPathRCs.push_back(&SPU::R8CRegClass);
52 CriticalPathRCs.push_back(&SPU::R16CRegClass);
53 CriticalPathRCs.push_back(&SPU::R32CRegClass);
54 CriticalPathRCs.push_back(&SPU::R32FPRegClass);
55 CriticalPathRCs.push_back(&SPU::R64CRegClass);
56 CriticalPathRCs.push_back(&SPU::VECREGRegClass);
57 return OptLevel >= CodeGenOpt::Default;