1 //===- SPURegisterInfo.cpp - Cell SPU Register Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Cell implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "reginfo"
16 #include "SPURegisterInfo.h"
17 #include "SPURegisterNames.h"
18 #include "SPUInstrBuilder.h"
19 #include "SPUSubtarget.h"
20 #include "SPUMachineFunction.h"
21 #include "SPUFrameLowering.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Type.h"
24 #include "llvm/CodeGen/ValueTypes.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineModuleInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineLocation.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/RegisterScavenging.h"
32 #include "llvm/CodeGen/ValueTypes.h"
33 #include "llvm/Target/TargetFrameLowering.h"
34 #include "llvm/Target/TargetInstrInfo.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
37 #include "llvm/Support/CommandLine.h"
38 #include "llvm/Support/Debug.h"
39 #include "llvm/Support/ErrorHandling.h"
40 #include "llvm/Support/MathExtras.h"
41 #include "llvm/Support/raw_ostream.h"
42 #include "llvm/ADT/BitVector.h"
43 #include "llvm/ADT/STLExtras.h"
46 #define GET_REGINFO_MC_DESC
47 #define GET_REGINFO_TARGET_DESC
48 #include "SPUGenRegisterInfo.inc"
52 /// getRegisterNumbering - Given the enum value for some register, e.g.
53 /// PPC::F14, return the number that it corresponds to (e.g. 14).
54 unsigned SPURegisterInfo::getRegisterNumbering(unsigned RegEnum) {
57 case SPU::R0: return 0;
58 case SPU::R1: return 1;
59 case SPU::R2: return 2;
60 case SPU::R3: return 3;
61 case SPU::R4: return 4;
62 case SPU::R5: return 5;
63 case SPU::R6: return 6;
64 case SPU::R7: return 7;
65 case SPU::R8: return 8;
66 case SPU::R9: return 9;
67 case SPU::R10: return 10;
68 case SPU::R11: return 11;
69 case SPU::R12: return 12;
70 case SPU::R13: return 13;
71 case SPU::R14: return 14;
72 case SPU::R15: return 15;
73 case SPU::R16: return 16;
74 case SPU::R17: return 17;
75 case SPU::R18: return 18;
76 case SPU::R19: return 19;
77 case SPU::R20: return 20;
78 case SPU::R21: return 21;
79 case SPU::R22: return 22;
80 case SPU::R23: return 23;
81 case SPU::R24: return 24;
82 case SPU::R25: return 25;
83 case SPU::R26: return 26;
84 case SPU::R27: return 27;
85 case SPU::R28: return 28;
86 case SPU::R29: return 29;
87 case SPU::R30: return 30;
88 case SPU::R31: return 31;
89 case SPU::R32: return 32;
90 case SPU::R33: return 33;
91 case SPU::R34: return 34;
92 case SPU::R35: return 35;
93 case SPU::R36: return 36;
94 case SPU::R37: return 37;
95 case SPU::R38: return 38;
96 case SPU::R39: return 39;
97 case SPU::R40: return 40;
98 case SPU::R41: return 41;
99 case SPU::R42: return 42;
100 case SPU::R43: return 43;
101 case SPU::R44: return 44;
102 case SPU::R45: return 45;
103 case SPU::R46: return 46;
104 case SPU::R47: return 47;
105 case SPU::R48: return 48;
106 case SPU::R49: return 49;
107 case SPU::R50: return 50;
108 case SPU::R51: return 51;
109 case SPU::R52: return 52;
110 case SPU::R53: return 53;
111 case SPU::R54: return 54;
112 case SPU::R55: return 55;
113 case SPU::R56: return 56;
114 case SPU::R57: return 57;
115 case SPU::R58: return 58;
116 case SPU::R59: return 59;
117 case SPU::R60: return 60;
118 case SPU::R61: return 61;
119 case SPU::R62: return 62;
120 case SPU::R63: return 63;
121 case SPU::R64: return 64;
122 case SPU::R65: return 65;
123 case SPU::R66: return 66;
124 case SPU::R67: return 67;
125 case SPU::R68: return 68;
126 case SPU::R69: return 69;
127 case SPU::R70: return 70;
128 case SPU::R71: return 71;
129 case SPU::R72: return 72;
130 case SPU::R73: return 73;
131 case SPU::R74: return 74;
132 case SPU::R75: return 75;
133 case SPU::R76: return 76;
134 case SPU::R77: return 77;
135 case SPU::R78: return 78;
136 case SPU::R79: return 79;
137 case SPU::R80: return 80;
138 case SPU::R81: return 81;
139 case SPU::R82: return 82;
140 case SPU::R83: return 83;
141 case SPU::R84: return 84;
142 case SPU::R85: return 85;
143 case SPU::R86: return 86;
144 case SPU::R87: return 87;
145 case SPU::R88: return 88;
146 case SPU::R89: return 89;
147 case SPU::R90: return 90;
148 case SPU::R91: return 91;
149 case SPU::R92: return 92;
150 case SPU::R93: return 93;
151 case SPU::R94: return 94;
152 case SPU::R95: return 95;
153 case SPU::R96: return 96;
154 case SPU::R97: return 97;
155 case SPU::R98: return 98;
156 case SPU::R99: return 99;
157 case SPU::R100: return 100;
158 case SPU::R101: return 101;
159 case SPU::R102: return 102;
160 case SPU::R103: return 103;
161 case SPU::R104: return 104;
162 case SPU::R105: return 105;
163 case SPU::R106: return 106;
164 case SPU::R107: return 107;
165 case SPU::R108: return 108;
166 case SPU::R109: return 109;
167 case SPU::R110: return 110;
168 case SPU::R111: return 111;
169 case SPU::R112: return 112;
170 case SPU::R113: return 113;
171 case SPU::R114: return 114;
172 case SPU::R115: return 115;
173 case SPU::R116: return 116;
174 case SPU::R117: return 117;
175 case SPU::R118: return 118;
176 case SPU::R119: return 119;
177 case SPU::R120: return 120;
178 case SPU::R121: return 121;
179 case SPU::R122: return 122;
180 case SPU::R123: return 123;
181 case SPU::R124: return 124;
182 case SPU::R125: return 125;
183 case SPU::R126: return 126;
184 case SPU::R127: return 127;
186 report_fatal_error("Unhandled reg in SPURegisterInfo::getRegisterNumbering");
190 SPURegisterInfo::SPURegisterInfo(const SPUSubtarget &subtarget,
191 const TargetInstrInfo &tii) :
192 SPUGenRegisterInfo(SPURegDesc, SPURegInfoDesc,
193 SPU::ADJCALLSTACKDOWN, SPU::ADJCALLSTACKUP),
194 Subtarget(subtarget),
199 /// getPointerRegClass - Return the register class to use to hold pointers.
200 /// This is used for addressing modes.
201 const TargetRegisterClass *
202 SPURegisterInfo::getPointerRegClass(unsigned Kind) const {
203 return &SPU::R32CRegClass;
207 SPURegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const
209 // Cell ABI calling convention
210 static const unsigned SPU_CalleeSaveRegs[] = {
211 SPU::R80, SPU::R81, SPU::R82, SPU::R83,
212 SPU::R84, SPU::R85, SPU::R86, SPU::R87,
213 SPU::R88, SPU::R89, SPU::R90, SPU::R91,
214 SPU::R92, SPU::R93, SPU::R94, SPU::R95,
215 SPU::R96, SPU::R97, SPU::R98, SPU::R99,
216 SPU::R100, SPU::R101, SPU::R102, SPU::R103,
217 SPU::R104, SPU::R105, SPU::R106, SPU::R107,
218 SPU::R108, SPU::R109, SPU::R110, SPU::R111,
219 SPU::R112, SPU::R113, SPU::R114, SPU::R115,
220 SPU::R116, SPU::R117, SPU::R118, SPU::R119,
221 SPU::R120, SPU::R121, SPU::R122, SPU::R123,
222 SPU::R124, SPU::R125, SPU::R126, SPU::R127,
223 SPU::R2, /* environment pointer */
224 SPU::R1, /* stack pointer */
225 SPU::R0, /* link register */
229 return SPU_CalleeSaveRegs;
233 R0 (link register), R1 (stack pointer) and R2 (environment pointer -- this is
234 generally unused) are the Cell's reserved registers
236 BitVector SPURegisterInfo::getReservedRegs(const MachineFunction &MF) const {
237 BitVector Reserved(getNumRegs());
238 Reserved.set(SPU::R0); // LR
239 Reserved.set(SPU::R1); // SP
240 Reserved.set(SPU::R2); // environment pointer
244 //===----------------------------------------------------------------------===//
245 // Stack Frame Processing methods
246 //===----------------------------------------------------------------------===//
248 //--------------------------------------------------------------------------
250 SPURegisterInfo::eliminateCallFramePseudoInstr(MachineFunction &MF,
251 MachineBasicBlock &MBB,
252 MachineBasicBlock::iterator I)
255 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
260 SPURegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
261 RegScavenger *RS) const
264 MachineInstr &MI = *II;
265 MachineBasicBlock &MBB = *MI.getParent();
266 MachineFunction &MF = *MBB.getParent();
267 MachineFrameInfo *MFI = MF.getFrameInfo();
268 DebugLoc dl = II->getDebugLoc();
270 while (!MI.getOperand(i).isFI()) {
272 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
275 MachineOperand &SPOp = MI.getOperand(i);
276 int FrameIndex = SPOp.getIndex();
278 // Now add the frame object offset to the offset from r1.
279 int Offset = MFI->getObjectOffset(FrameIndex);
281 // Most instructions, except for generated FrameIndex additions using AIr32
282 // and ILAr32, have the immediate in operand 1. AIr32 and ILAr32 have the
283 // immediate in operand 2.
285 if (MI.getOpcode() == SPU::AIr32 || MI.getOpcode() == SPU::ILAr32)
288 MachineOperand &MO = MI.getOperand(OpNo);
290 // Offset is biased by $lr's slot at the bottom.
291 Offset += MO.getImm() + MFI->getStackSize() + SPUFrameLowering::minStackSize();
292 assert((Offset & 0xf) == 0
293 && "16-byte alignment violated in eliminateFrameIndex");
295 // Replace the FrameIndex with base register with $sp (aka $r1)
296 SPOp.ChangeToRegister(SPU::R1, false);
298 // if 'Offset' doesn't fit to the D-form instruction's
299 // immediate, convert the instruction to X-form
300 // if the instruction is not an AI (which takes a s10 immediate), assume
301 // it is a load/store that can take a s14 immediate
302 if ((MI.getOpcode() == SPU::AIr32 && !isInt<10>(Offset))
303 || !isInt<14>(Offset)) {
304 int newOpcode = convertDFormToXForm(MI.getOpcode());
305 unsigned tmpReg = findScratchRegister(II, RS, &SPU::R32CRegClass, SPAdj);
306 BuildMI(MBB, II, dl, TII.get(SPU::ILr32), tmpReg )
308 BuildMI(MBB, II, dl, TII.get(newOpcode), MI.getOperand(0).getReg())
309 .addReg(tmpReg, RegState::Kill)
311 // remove the replaced D-form instruction
314 MO.ChangeToImmediate(Offset);
319 SPURegisterInfo::getRARegister() const
325 SPURegisterInfo::getFrameRegister(const MachineFunction &MF) const
331 SPURegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
332 // FIXME: Most probably dwarf numbers differs for Linux and Darwin
333 return SPUGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
336 int SPURegisterInfo::getLLVMRegNum(unsigned RegNum, bool isEH) const {
337 return SPUGenRegisterInfo::getLLVMRegNumFull(RegNum, 0);
341 SPURegisterInfo::convertDFormToXForm(int dFormOpcode) const
345 case SPU::AIr32: return SPU::Ar32;
346 case SPU::LQDr32: return SPU::LQXr32;
347 case SPU::LQDr128: return SPU::LQXr128;
348 case SPU::LQDv16i8: return SPU::LQXv16i8;
349 case SPU::LQDv4i32: return SPU::LQXv4i32;
350 case SPU::LQDv4f32: return SPU::LQXv4f32;
351 case SPU::STQDr32: return SPU::STQXr32;
352 case SPU::STQDr128: return SPU::STQXr128;
353 case SPU::STQDv16i8: return SPU::STQXv16i8;
354 case SPU::STQDv4i32: return SPU::STQXv4i32;
355 case SPU::STQDv4f32: return SPU::STQXv4f32;
357 default: assert( false && "Unhandled D to X-form conversion");
359 // default will assert, but need to return something to keep the
364 // TODO this is already copied from PPC. Could this convenience function
365 // be moved to the RegScavenger class?
367 SPURegisterInfo::findScratchRegister(MachineBasicBlock::iterator II,
369 const TargetRegisterClass *RC,
372 assert(RS && "Register scavenging must be on");
373 unsigned Reg = RS->FindUnusedReg(RC);
375 Reg = RS->scavengeRegister(RC, II, SPAdj);
376 assert( Reg && "Register scavenger failed");