1 //===- SPUInstrInfo.cpp - Cell SPU Instruction Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Cell SPU implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "SPURegisterNames.h"
15 #include "SPUInstrInfo.h"
16 #include "SPUInstrBuilder.h"
17 #include "SPUTargetMachine.h"
18 #include "SPUGenInstrInfo.inc"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/Support/Streams.h"
21 #include "llvm/Support/Debug.h"
26 //! Predicate for an unconditional branch instruction
27 inline bool isUncondBranch(const MachineInstr *I) {
28 unsigned opc = I->getOpcode();
30 return (opc == SPU::BR
35 //! Predicate for a conditional branch instruction
36 inline bool isCondBranch(const MachineInstr *I) {
37 unsigned opc = I->getOpcode();
39 return (opc == SPU::BRNZr32
40 || opc == SPU::BRNZv4i32
42 || opc == SPU::BRZv4i32
43 || opc == SPU::BRHNZr16
44 || opc == SPU::BRHNZv8i16
45 || opc == SPU::BRHZr16
46 || opc == SPU::BRHZv8i16);
50 SPUInstrInfo::SPUInstrInfo(SPUTargetMachine &tm)
51 : TargetInstrInfoImpl(SPUInsts, sizeof(SPUInsts)/sizeof(SPUInsts[0])),
53 RI(*TM.getSubtargetImpl(), *this)
57 SPUInstrInfo::isMoveInstr(const MachineInstr& MI,
60 unsigned& SrcSR, unsigned& DstSR) const {
61 SrcSR = DstSR = 0; // No sub-registers.
63 // Primarily, ORI and OR are generated by copyRegToReg. But, there are other
64 // cases where we can safely say that what's being done is really a move
65 // (see how PowerPC does this -- it's the model for this code too.)
66 switch (MI.getOpcode()) {
81 assert(MI.getNumOperands() == 3 &&
82 MI.getOperand(0).isReg() &&
83 MI.getOperand(1).isReg() &&
84 MI.getOperand(2).isImm() &&
85 "invalid SPU ORI/ORHI/ORBI/AHI/AI/SFI/SFHI instruction!");
86 if (MI.getOperand(2).getImm() == 0) {
87 sourceReg = MI.getOperand(1).getReg();
88 destReg = MI.getOperand(0).getReg();
93 assert(MI.getNumOperands() == 3 &&
94 "wrong number of operands to AIr32");
95 if (MI.getOperand(0).isReg() &&
96 MI.getOperand(1).isReg() &&
97 (MI.getOperand(2).isImm() &&
98 MI.getOperand(2).getImm() == 0)) {
99 sourceReg = MI.getOperand(1).getReg();
100 destReg = MI.getOperand(0).getReg();
117 case SPU::ORv16i8_i8:
118 case SPU::ORv8i16_i16:
119 case SPU::ORv4i32_i32:
120 case SPU::ORv2i64_i64:
121 case SPU::ORv4f32_f32:
122 case SPU::ORv2f64_f64:
123 case SPU::ORi8_v16i8:
124 case SPU::ORi16_v8i16:
125 case SPU::ORi32_v4i32:
126 case SPU::ORi64_v2i64:
127 case SPU::ORf32_v4f32:
128 case SPU::ORf64_v2f64:
130 case SPU::ORi128_r64:
131 case SPU::ORi128_f64:
132 case SPU::ORi128_r32:
133 case SPU::ORi128_f32:
134 case SPU::ORi128_r16:
136 case SPU::ORi128_vec:
137 case SPU::ORr64_i128:
138 case SPU::ORf64_i128:
139 case SPU::ORr32_i128:
140 case SPU::ORf32_i128:
141 case SPU::ORr16_i128:
143 case SPU::ORvec_i128:
160 case SPU::ORr64_f64: {
161 assert(MI.getNumOperands() == 2 &&
162 MI.getOperand(0).isReg() &&
163 MI.getOperand(1).isReg() &&
164 "invalid SPU OR<type>_<vec> or LR instruction!");
165 if (MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
166 sourceReg = MI.getOperand(0).getReg();
167 destReg = MI.getOperand(0).getReg();
182 assert(MI.getNumOperands() == 3 &&
183 MI.getOperand(0).isReg() &&
184 MI.getOperand(1).isReg() &&
185 MI.getOperand(2).isReg() &&
186 "invalid SPU OR(vec|r32|r64|gprc) instruction!");
187 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
188 sourceReg = MI.getOperand(1).getReg();
189 destReg = MI.getOperand(0).getReg();
199 SPUInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
200 int &FrameIndex) const {
201 switch (MI->getOpcode()) {
212 const MachineOperand MOp1 = MI->getOperand(1);
213 const MachineOperand MOp2 = MI->getOperand(2);
214 if (MOp1.isImm() && MOp2.isFI()) {
215 FrameIndex = MOp2.getIndex();
216 return MI->getOperand(0).getReg();
225 SPUInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
226 int &FrameIndex) const {
227 switch (MI->getOpcode()) {
239 const MachineOperand MOp1 = MI->getOperand(1);
240 const MachineOperand MOp2 = MI->getOperand(2);
241 if (MOp1.isImm() && MOp2.isFI()) {
242 FrameIndex = MOp2.getIndex();
243 return MI->getOperand(0).getReg();
251 bool SPUInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
252 MachineBasicBlock::iterator MI,
253 unsigned DestReg, unsigned SrcReg,
254 const TargetRegisterClass *DestRC,
255 const TargetRegisterClass *SrcRC) const
257 // We support cross register class moves for our aliases, such as R3 in any
258 // reg class to any other reg class containing R3. This is required because
259 // we instruction select bitconvert i64 -> f64 as a noop for example, so our
260 // types have no specific meaning.
262 if (DestRC == SPU::R8CRegisterClass) {
263 BuildMI(MBB, MI, get(SPU::LRr8), DestReg).addReg(SrcReg);
264 } else if (DestRC == SPU::R16CRegisterClass) {
265 BuildMI(MBB, MI, get(SPU::LRr16), DestReg).addReg(SrcReg);
266 } else if (DestRC == SPU::R32CRegisterClass) {
267 BuildMI(MBB, MI, get(SPU::LRr32), DestReg).addReg(SrcReg);
268 } else if (DestRC == SPU::R32FPRegisterClass) {
269 BuildMI(MBB, MI, get(SPU::LRf32), DestReg).addReg(SrcReg);
270 } else if (DestRC == SPU::R64CRegisterClass) {
271 BuildMI(MBB, MI, get(SPU::LRr64), DestReg).addReg(SrcReg);
272 } else if (DestRC == SPU::R64FPRegisterClass) {
273 BuildMI(MBB, MI, get(SPU::LRf64), DestReg).addReg(SrcReg);
274 } else if (DestRC == SPU::GPRCRegisterClass) {
275 BuildMI(MBB, MI, get(SPU::LRr128), DestReg).addReg(SrcReg);
276 } else if (DestRC == SPU::VECREGRegisterClass) {
277 BuildMI(MBB, MI, get(SPU::LRv16i8), DestReg).addReg(SrcReg);
279 // Attempt to copy unknown/unsupported register class!
287 SPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
288 MachineBasicBlock::iterator MI,
289 unsigned SrcReg, bool isKill, int FrameIdx,
290 const TargetRegisterClass *RC) const
293 bool isValidFrameIdx = (FrameIdx < SPUFrameInfo::maxFrameOffset());
294 if (RC == SPU::GPRCRegisterClass) {
295 opc = (isValidFrameIdx ? SPU::STQDr128 : SPU::STQXr128);
296 } else if (RC == SPU::R64CRegisterClass) {
297 opc = (isValidFrameIdx ? SPU::STQDr64 : SPU::STQXr64);
298 } else if (RC == SPU::R64FPRegisterClass) {
299 opc = (isValidFrameIdx ? SPU::STQDr64 : SPU::STQXr64);
300 } else if (RC == SPU::R32CRegisterClass) {
301 opc = (isValidFrameIdx ? SPU::STQDr32 : SPU::STQXr32);
302 } else if (RC == SPU::R32FPRegisterClass) {
303 opc = (isValidFrameIdx ? SPU::STQDr32 : SPU::STQXr32);
304 } else if (RC == SPU::R16CRegisterClass) {
305 opc = (isValidFrameIdx ? SPU::STQDr16 : SPU::STQXr16);
306 } else if (RC == SPU::R8CRegisterClass) {
307 opc = (isValidFrameIdx ? SPU::STQDr8 : SPU::STQXr8);
308 } else if (RC == SPU::VECREGRegisterClass) {
309 opc = (isValidFrameIdx) ? SPU::STQDv16i8 : SPU::STQXv16i8;
311 assert(0 && "Unknown regclass!");
315 addFrameReference(BuildMI(MBB, MI, get(opc))
316 .addReg(SrcReg, false, false, isKill), FrameIdx);
319 void SPUInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
321 SmallVectorImpl<MachineOperand> &Addr,
322 const TargetRegisterClass *RC,
323 SmallVectorImpl<MachineInstr*> &NewMIs) const {
324 cerr << "storeRegToAddr() invoked!\n";
327 if (Addr[0].isFI()) {
328 /* do what storeRegToStackSlot does here */
331 if (RC == SPU::GPRCRegisterClass) {
332 /* Opc = PPC::STW; */
333 } else if (RC == SPU::R16CRegisterClass) {
334 /* Opc = PPC::STD; */
335 } else if (RC == SPU::R32CRegisterClass) {
336 /* Opc = PPC::STFD; */
337 } else if (RC == SPU::R32FPRegisterClass) {
338 /* Opc = PPC::STFD; */
339 } else if (RC == SPU::R64FPRegisterClass) {
340 /* Opc = PPC::STFS; */
341 } else if (RC == SPU::VECREGRegisterClass) {
342 /* Opc = PPC::STVX; */
344 assert(0 && "Unknown regclass!");
347 MachineInstrBuilder MIB = BuildMI(MF, get(Opc))
348 .addReg(SrcReg, false, false, isKill);
349 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
350 MachineOperand &MO = Addr[i];
352 MIB.addReg(MO.getReg());
354 MIB.addImm(MO.getImm());
356 MIB.addFrameIndex(MO.getIndex());
358 NewMIs.push_back(MIB);
363 SPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
364 MachineBasicBlock::iterator MI,
365 unsigned DestReg, int FrameIdx,
366 const TargetRegisterClass *RC) const
369 bool isValidFrameIdx = (FrameIdx < SPUFrameInfo::maxFrameOffset());
370 if (RC == SPU::GPRCRegisterClass) {
371 opc = (isValidFrameIdx ? SPU::LQDr128 : SPU::LQXr128);
372 } else if (RC == SPU::R64CRegisterClass) {
373 opc = (isValidFrameIdx ? SPU::LQDr64 : SPU::LQXr64);
374 } else if (RC == SPU::R64FPRegisterClass) {
375 opc = (isValidFrameIdx ? SPU::LQDr64 : SPU::LQXr64);
376 } else if (RC == SPU::R32CRegisterClass) {
377 opc = (isValidFrameIdx ? SPU::LQDr32 : SPU::LQXr32);
378 } else if (RC == SPU::R32FPRegisterClass) {
379 opc = (isValidFrameIdx ? SPU::LQDr32 : SPU::LQXr32);
380 } else if (RC == SPU::R16CRegisterClass) {
381 opc = (isValidFrameIdx ? SPU::LQDr16 : SPU::LQXr16);
382 } else if (RC == SPU::R8CRegisterClass) {
383 opc = (isValidFrameIdx ? SPU::LQDr8 : SPU::LQXr8);
384 } else if (RC == SPU::VECREGRegisterClass) {
385 opc = (isValidFrameIdx) ? SPU::LQDv16i8 : SPU::LQXv16i8;
387 assert(0 && "Unknown regclass in loadRegFromStackSlot!");
391 addFrameReference(BuildMI(MBB, MI, get(opc)).addReg(DestReg), FrameIdx);
395 \note We are really pessimistic here about what kind of a load we're doing.
397 void SPUInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
398 SmallVectorImpl<MachineOperand> &Addr,
399 const TargetRegisterClass *RC,
400 SmallVectorImpl<MachineInstr*> &NewMIs)
402 cerr << "loadRegToAddr() invoked!\n";
405 if (Addr[0].isFI()) {
406 /* do what loadRegFromStackSlot does here... */
409 if (RC == SPU::R8CRegisterClass) {
410 /* do brilliance here */
411 } else if (RC == SPU::R16CRegisterClass) {
412 /* Opc = PPC::LWZ; */
413 } else if (RC == SPU::R32CRegisterClass) {
415 } else if (RC == SPU::R32FPRegisterClass) {
416 /* Opc = PPC::LFD; */
417 } else if (RC == SPU::R64FPRegisterClass) {
418 /* Opc = PPC::LFS; */
419 } else if (RC == SPU::VECREGRegisterClass) {
420 /* Opc = PPC::LVX; */
421 } else if (RC == SPU::GPRCRegisterClass) {
422 /* Opc = something else! */
424 assert(0 && "Unknown regclass!");
427 MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
428 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
429 MachineOperand &MO = Addr[i];
431 MIB.addReg(MO.getReg());
433 MIB.addImm(MO.getImm());
435 MIB.addFrameIndex(MO.getIndex());
437 NewMIs.push_back(MIB);
441 //! Return true if the specified load or store can be folded
443 SPUInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
444 const SmallVectorImpl<unsigned> &Ops) const {
445 if (Ops.size() != 1) return false;
447 // Make sure this is a reg-reg copy.
448 unsigned Opc = MI->getOpcode();
461 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
469 /// foldMemoryOperand - SPU, like PPC, can only fold spills into
470 /// copy instructions, turning them into load/store instructions.
472 SPUInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
474 const SmallVectorImpl<unsigned> &Ops,
475 int FrameIndex) const
477 if (Ops.size() != 1) return 0;
479 unsigned OpNum = Ops[0];
480 unsigned Opc = MI->getOpcode();
481 MachineInstr *NewMI = 0;
494 if (OpNum == 0) { // move -> store
495 unsigned InReg = MI->getOperand(1).getReg();
496 bool isKill = MI->getOperand(1).isKill();
497 if (FrameIndex < SPUFrameInfo::maxFrameOffset()) {
498 MachineInstrBuilder MIB = BuildMI(MF, get(SPU::STQDr32));
500 MIB.addReg(InReg, false, false, isKill);
501 NewMI = addFrameReference(MIB, FrameIndex);
503 } else { // move -> load
504 unsigned OutReg = MI->getOperand(0).getReg();
505 bool isDead = MI->getOperand(0).isDead();
506 MachineInstrBuilder MIB = BuildMI(MF, get(Opc));
508 MIB.addReg(OutReg, true, false, false, isDead);
509 Opc = (FrameIndex < SPUFrameInfo::maxFrameOffset())
510 ? SPU::STQDr32 : SPU::STQXr32;
511 NewMI = addFrameReference(MIB, FrameIndex);
521 \note This code was kiped from PPC. There may be more branch analysis for
522 CellSPU than what's currently done here.
525 SPUInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
526 MachineBasicBlock *&FBB,
527 SmallVectorImpl<MachineOperand> &Cond) const {
528 // If the block has no terminators, it just falls into the block after it.
529 MachineBasicBlock::iterator I = MBB.end();
530 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
533 // Get the last instruction in the block.
534 MachineInstr *LastInst = I;
536 // If there is only one terminator instruction, process it.
537 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
538 if (isUncondBranch(LastInst)) {
539 TBB = LastInst->getOperand(0).getMBB();
541 } else if (isCondBranch(LastInst)) {
542 // Block ends with fall-through condbranch.
543 TBB = LastInst->getOperand(1).getMBB();
544 DEBUG(cerr << "Pushing LastInst: ");
545 DEBUG(LastInst->dump());
546 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
547 Cond.push_back(LastInst->getOperand(0));
550 // Otherwise, don't know what this is.
554 // Get the instruction before it if it's a terminator.
555 MachineInstr *SecondLastInst = I;
557 // If there are three terminators, we don't know what sort of block this is.
558 if (SecondLastInst && I != MBB.begin() &&
559 isUnpredicatedTerminator(--I))
562 // If the block ends with a conditional and unconditional branch, handle it.
563 if (isCondBranch(SecondLastInst) && isUncondBranch(LastInst)) {
564 TBB = SecondLastInst->getOperand(1).getMBB();
565 DEBUG(cerr << "Pushing SecondLastInst: ");
566 DEBUG(SecondLastInst->dump());
567 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
568 Cond.push_back(SecondLastInst->getOperand(0));
569 FBB = LastInst->getOperand(0).getMBB();
573 // If the block ends with two unconditional branches, handle it. The second
574 // one is not executed, so remove it.
575 if (isUncondBranch(SecondLastInst) && isUncondBranch(LastInst)) {
576 TBB = SecondLastInst->getOperand(0).getMBB();
578 I->eraseFromParent();
582 // Otherwise, can't handle this.
587 SPUInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
588 MachineBasicBlock::iterator I = MBB.end();
589 if (I == MBB.begin())
592 if (!isCondBranch(I) && !isUncondBranch(I))
595 // Remove the first branch.
596 DEBUG(cerr << "Removing branch: ");
598 I->eraseFromParent();
600 if (I == MBB.begin())
604 if (!(isCondBranch(I) || isUncondBranch(I)))
607 // Remove the second branch.
608 DEBUG(cerr << "Removing second branch: ");
610 I->eraseFromParent();
615 SPUInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
616 MachineBasicBlock *FBB,
617 const SmallVectorImpl<MachineOperand> &Cond) const {
618 // Shouldn't be a fall through.
619 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
620 assert((Cond.size() == 2 || Cond.size() == 0) &&
621 "SPU branch conditions have two components!");
626 // Unconditional branch
627 MachineInstrBuilder MIB = BuildMI(&MBB, get(SPU::BR));
630 DEBUG(cerr << "Inserted one-way uncond branch: ");
631 DEBUG((*MIB).dump());
633 // Conditional branch
634 MachineInstrBuilder MIB = BuildMI(&MBB, get(Cond[0].getImm()));
635 MIB.addReg(Cond[1].getReg()).addMBB(TBB);
637 DEBUG(cerr << "Inserted one-way cond branch: ");
638 DEBUG((*MIB).dump());
642 MachineInstrBuilder MIB = BuildMI(&MBB, get(Cond[0].getImm()));
643 MachineInstrBuilder MIB2 = BuildMI(&MBB, get(SPU::BR));
645 // Two-way Conditional Branch.
646 MIB.addReg(Cond[1].getReg()).addMBB(TBB);
649 DEBUG(cerr << "Inserted conditional branch: ");
650 DEBUG((*MIB).dump());
651 DEBUG(cerr << "part 2: ");
652 DEBUG((*MIB2).dump());
658 SPUInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
659 return (!MBB.empty() && isUncondBranch(&MBB.back()));
661 //! Reverses a branch's condition, returning false on success.
663 SPUInstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond)
665 // Pretty brainless way of inverting the condition, but it works, considering
666 // there are only two conditions...
668 unsigned Opc; //! The incoming opcode
669 unsigned RevCondOpc; //! The reversed condition opcode
671 { SPU::BRNZr32, SPU::BRZr32 },
672 { SPU::BRNZv4i32, SPU::BRZv4i32 },
673 { SPU::BRZr32, SPU::BRNZr32 },
674 { SPU::BRZv4i32, SPU::BRNZv4i32 },
675 { SPU::BRHNZr16, SPU::BRHZr16 },
676 { SPU::BRHNZv8i16, SPU::BRHZv8i16 },
677 { SPU::BRHZr16, SPU::BRHNZr16 },
678 { SPU::BRHZv8i16, SPU::BRHNZv8i16 }
681 unsigned Opc = unsigned(Cond[0].getImm());
682 // Pretty dull mapping between the two conditions that SPU can generate:
683 for (int i = sizeof(revconds)/sizeof(revconds[0]) - 1; i >= 0; --i) {
684 if (revconds[i].Opc == Opc) {
685 Cond[0].setImm(revconds[i].RevCondOpc);