2 //===-- SPUISelLowering.cpp - Cell SPU DAG Lowering Implementation --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SPUTargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "SPURegisterNames.h"
15 #include "SPUISelLowering.h"
16 #include "SPUTargetMachine.h"
17 #include "SPUFrameInfo.h"
18 #include "SPUMachineFunction.h"
19 #include "llvm/Constants.h"
20 #include "llvm/Function.h"
21 #include "llvm/Intrinsics.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/ADT/VectorExtras.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/Support/raw_ostream.h"
40 // Used in getTargetNodeName() below
42 std::map<unsigned, const char *> node_names;
44 //! EVT mapping to useful data for Cell SPU
45 struct valtype_map_s {
50 const valtype_map_s valtype_map[] = {
61 const size_t n_valtype_map = sizeof(valtype_map) / sizeof(valtype_map[0]);
63 const valtype_map_s *getValueTypeMapEntry(EVT VT) {
64 const valtype_map_s *retval = 0;
66 for (size_t i = 0; i < n_valtype_map; ++i) {
67 if (valtype_map[i].valtype == VT) {
68 retval = valtype_map + i;
75 report_fatal_error("getValueTypeMapEntry returns NULL for " +
76 Twine(VT.getEVTString()));
83 //! Expand a library call into an actual call DAG node
86 This code is taken from SelectionDAGLegalize, since it is not exposed as
87 part of the LLVM SelectionDAG API.
91 ExpandLibCall(RTLIB::Libcall LC, SDValue Op, SelectionDAG &DAG,
92 bool isSigned, SDValue &Hi, const SPUTargetLowering &TLI) {
93 // The input chain to this libcall is the entry node of the function.
94 // Legalizing the call will automatically add the previous call to the
96 SDValue InChain = DAG.getEntryNode();
98 TargetLowering::ArgListTy Args;
99 TargetLowering::ArgListEntry Entry;
100 for (unsigned i = 0, e = Op.getNumOperands(); i != e; ++i) {
101 EVT ArgVT = Op.getOperand(i).getValueType();
102 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
103 Entry.Node = Op.getOperand(i);
105 Entry.isSExt = isSigned;
106 Entry.isZExt = !isSigned;
107 Args.push_back(Entry);
109 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
112 // Splice the libcall in wherever FindInputOutputChains tells us to.
114 Op.getNode()->getValueType(0).getTypeForEVT(*DAG.getContext());
115 std::pair<SDValue, SDValue> CallInfo =
116 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
117 0, TLI.getLibcallCallingConv(LC), false,
118 /*isReturnValueUsed=*/true,
119 Callee, Args, DAG, Op.getDebugLoc());
121 return CallInfo.first;
125 SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
126 : TargetLowering(TM, new TargetLoweringObjectFileELF()),
128 // Fold away setcc operations if possible.
131 // Use _setjmp/_longjmp instead of setjmp/longjmp.
132 setUseUnderscoreSetJmp(true);
133 setUseUnderscoreLongJmp(true);
135 // Set RTLIB libcall names as used by SPU:
136 setLibcallName(RTLIB::DIV_F64, "__fast_divdf3");
138 // Set up the SPU's register classes:
139 addRegisterClass(MVT::i8, SPU::R8CRegisterClass);
140 addRegisterClass(MVT::i16, SPU::R16CRegisterClass);
141 addRegisterClass(MVT::i32, SPU::R32CRegisterClass);
142 addRegisterClass(MVT::i64, SPU::R64CRegisterClass);
143 addRegisterClass(MVT::f32, SPU::R32FPRegisterClass);
144 addRegisterClass(MVT::f64, SPU::R64FPRegisterClass);
145 addRegisterClass(MVT::i128, SPU::GPRCRegisterClass);
147 // SPU has no sign or zero extended loads for i1, i8, i16:
148 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
149 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
150 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
152 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
153 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand);
155 setTruncStoreAction(MVT::i128, MVT::i64, Expand);
156 setTruncStoreAction(MVT::i128, MVT::i32, Expand);
157 setTruncStoreAction(MVT::i128, MVT::i16, Expand);
158 setTruncStoreAction(MVT::i128, MVT::i8, Expand);
160 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
162 // SPU constant load actions are custom lowered:
163 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
164 setOperationAction(ISD::ConstantFP, MVT::f64, Custom);
166 // SPU's loads and stores have to be custom lowered:
167 for (unsigned sctype = (unsigned) MVT::i8; sctype < (unsigned) MVT::i128;
169 MVT::SimpleValueType VT = (MVT::SimpleValueType)sctype;
171 setOperationAction(ISD::LOAD, VT, Custom);
172 setOperationAction(ISD::STORE, VT, Custom);
173 setLoadExtAction(ISD::EXTLOAD, VT, Custom);
174 setLoadExtAction(ISD::ZEXTLOAD, VT, Custom);
175 setLoadExtAction(ISD::SEXTLOAD, VT, Custom);
177 for (unsigned stype = sctype - 1; stype >= (unsigned) MVT::i8; --stype) {
178 MVT::SimpleValueType StoreVT = (MVT::SimpleValueType) stype;
179 setTruncStoreAction(VT, StoreVT, Expand);
183 for (unsigned sctype = (unsigned) MVT::f32; sctype < (unsigned) MVT::f64;
185 MVT::SimpleValueType VT = (MVT::SimpleValueType) sctype;
187 setOperationAction(ISD::LOAD, VT, Custom);
188 setOperationAction(ISD::STORE, VT, Custom);
190 for (unsigned stype = sctype - 1; stype >= (unsigned) MVT::f32; --stype) {
191 MVT::SimpleValueType StoreVT = (MVT::SimpleValueType) stype;
192 setTruncStoreAction(VT, StoreVT, Expand);
196 // Expand the jumptable branches
197 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
198 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
200 // Custom lower SELECT_CC for most cases, but expand by default
201 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
202 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom);
203 setOperationAction(ISD::SELECT_CC, MVT::i16, Custom);
204 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
205 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
207 // SPU has no intrinsics for these particular operations:
208 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
210 // SPU has no division/remainder instructions
211 setOperationAction(ISD::SREM, MVT::i8, Expand);
212 setOperationAction(ISD::UREM, MVT::i8, Expand);
213 setOperationAction(ISD::SDIV, MVT::i8, Expand);
214 setOperationAction(ISD::UDIV, MVT::i8, Expand);
215 setOperationAction(ISD::SDIVREM, MVT::i8, Expand);
216 setOperationAction(ISD::UDIVREM, MVT::i8, Expand);
217 setOperationAction(ISD::SREM, MVT::i16, Expand);
218 setOperationAction(ISD::UREM, MVT::i16, Expand);
219 setOperationAction(ISD::SDIV, MVT::i16, Expand);
220 setOperationAction(ISD::UDIV, MVT::i16, Expand);
221 setOperationAction(ISD::SDIVREM, MVT::i16, Expand);
222 setOperationAction(ISD::UDIVREM, MVT::i16, Expand);
223 setOperationAction(ISD::SREM, MVT::i32, Expand);
224 setOperationAction(ISD::UREM, MVT::i32, Expand);
225 setOperationAction(ISD::SDIV, MVT::i32, Expand);
226 setOperationAction(ISD::UDIV, MVT::i32, Expand);
227 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
228 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
229 setOperationAction(ISD::SREM, MVT::i64, Expand);
230 setOperationAction(ISD::UREM, MVT::i64, Expand);
231 setOperationAction(ISD::SDIV, MVT::i64, Expand);
232 setOperationAction(ISD::UDIV, MVT::i64, Expand);
233 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
234 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
235 setOperationAction(ISD::SREM, MVT::i128, Expand);
236 setOperationAction(ISD::UREM, MVT::i128, Expand);
237 setOperationAction(ISD::SDIV, MVT::i128, Expand);
238 setOperationAction(ISD::UDIV, MVT::i128, Expand);
239 setOperationAction(ISD::SDIVREM, MVT::i128, Expand);
240 setOperationAction(ISD::UDIVREM, MVT::i128, Expand);
242 // We don't support sin/cos/sqrt/fmod
243 setOperationAction(ISD::FSIN , MVT::f64, Expand);
244 setOperationAction(ISD::FCOS , MVT::f64, Expand);
245 setOperationAction(ISD::FREM , MVT::f64, Expand);
246 setOperationAction(ISD::FSIN , MVT::f32, Expand);
247 setOperationAction(ISD::FCOS , MVT::f32, Expand);
248 setOperationAction(ISD::FREM , MVT::f32, Expand);
250 // Expand fsqrt to the appropriate libcall (NOTE: should use h/w fsqrt
252 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
253 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
255 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
256 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
258 // SPU can do rotate right and left, so legalize it... but customize for i8
259 // because instructions don't exist.
261 // FIXME: Change from "expand" to appropriate type once ROTR is supported in
263 setOperationAction(ISD::ROTR, MVT::i32, Expand /*Legal*/);
264 setOperationAction(ISD::ROTR, MVT::i16, Expand /*Legal*/);
265 setOperationAction(ISD::ROTR, MVT::i8, Expand /*Custom*/);
267 setOperationAction(ISD::ROTL, MVT::i32, Legal);
268 setOperationAction(ISD::ROTL, MVT::i16, Legal);
269 setOperationAction(ISD::ROTL, MVT::i8, Custom);
271 // SPU has no native version of shift left/right for i8
272 setOperationAction(ISD::SHL, MVT::i8, Custom);
273 setOperationAction(ISD::SRL, MVT::i8, Custom);
274 setOperationAction(ISD::SRA, MVT::i8, Custom);
276 // Make these operations legal and handle them during instruction selection:
277 setOperationAction(ISD::SHL, MVT::i64, Legal);
278 setOperationAction(ISD::SRL, MVT::i64, Legal);
279 setOperationAction(ISD::SRA, MVT::i64, Legal);
281 // Custom lower i8, i32 and i64 multiplications
282 setOperationAction(ISD::MUL, MVT::i8, Custom);
283 setOperationAction(ISD::MUL, MVT::i32, Legal);
284 setOperationAction(ISD::MUL, MVT::i64, Legal);
286 // Expand double-width multiplication
287 // FIXME: It would probably be reasonable to support some of these operations
288 setOperationAction(ISD::UMUL_LOHI, MVT::i8, Expand);
289 setOperationAction(ISD::SMUL_LOHI, MVT::i8, Expand);
290 setOperationAction(ISD::MULHU, MVT::i8, Expand);
291 setOperationAction(ISD::MULHS, MVT::i8, Expand);
292 setOperationAction(ISD::UMUL_LOHI, MVT::i16, Expand);
293 setOperationAction(ISD::SMUL_LOHI, MVT::i16, Expand);
294 setOperationAction(ISD::MULHU, MVT::i16, Expand);
295 setOperationAction(ISD::MULHS, MVT::i16, Expand);
296 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
297 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
298 setOperationAction(ISD::MULHU, MVT::i32, Expand);
299 setOperationAction(ISD::MULHS, MVT::i32, Expand);
300 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
301 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
302 setOperationAction(ISD::MULHU, MVT::i64, Expand);
303 setOperationAction(ISD::MULHS, MVT::i64, Expand);
305 // Need to custom handle (some) common i8, i64 math ops
306 setOperationAction(ISD::ADD, MVT::i8, Custom);
307 setOperationAction(ISD::ADD, MVT::i64, Legal);
308 setOperationAction(ISD::SUB, MVT::i8, Custom);
309 setOperationAction(ISD::SUB, MVT::i64, Legal);
311 // SPU does not have BSWAP. It does have i32 support CTLZ.
312 // CTPOP has to be custom lowered.
313 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
314 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
316 setOperationAction(ISD::CTPOP, MVT::i8, Custom);
317 setOperationAction(ISD::CTPOP, MVT::i16, Custom);
318 setOperationAction(ISD::CTPOP, MVT::i32, Custom);
319 setOperationAction(ISD::CTPOP, MVT::i64, Custom);
320 setOperationAction(ISD::CTPOP, MVT::i128, Expand);
322 setOperationAction(ISD::CTTZ , MVT::i8, Expand);
323 setOperationAction(ISD::CTTZ , MVT::i16, Expand);
324 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
325 setOperationAction(ISD::CTTZ , MVT::i64, Expand);
326 setOperationAction(ISD::CTTZ , MVT::i128, Expand);
328 setOperationAction(ISD::CTLZ , MVT::i8, Promote);
329 setOperationAction(ISD::CTLZ , MVT::i16, Promote);
330 setOperationAction(ISD::CTLZ , MVT::i32, Legal);
331 setOperationAction(ISD::CTLZ , MVT::i64, Expand);
332 setOperationAction(ISD::CTLZ , MVT::i128, Expand);
334 // SPU has a version of select that implements (a&~c)|(b&c), just like
335 // select ought to work:
336 setOperationAction(ISD::SELECT, MVT::i8, Legal);
337 setOperationAction(ISD::SELECT, MVT::i16, Legal);
338 setOperationAction(ISD::SELECT, MVT::i32, Legal);
339 setOperationAction(ISD::SELECT, MVT::i64, Legal);
341 setOperationAction(ISD::SETCC, MVT::i8, Legal);
342 setOperationAction(ISD::SETCC, MVT::i16, Legal);
343 setOperationAction(ISD::SETCC, MVT::i32, Legal);
344 setOperationAction(ISD::SETCC, MVT::i64, Legal);
345 setOperationAction(ISD::SETCC, MVT::f64, Custom);
347 // Custom lower i128 -> i64 truncates
348 setOperationAction(ISD::TRUNCATE, MVT::i64, Custom);
350 // Custom lower i32/i64 -> i128 sign extend
351 setOperationAction(ISD::SIGN_EXTEND, MVT::i128, Custom);
353 setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote);
354 setOperationAction(ISD::FP_TO_UINT, MVT::i8, Promote);
355 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote);
356 setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote);
357 // SPU has a legal FP -> signed INT instruction for f32, but for f64, need
358 // to expand to a libcall, hence the custom lowering:
359 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
360 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
361 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Expand);
362 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
363 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Expand);
364 setOperationAction(ISD::FP_TO_UINT, MVT::i128, Expand);
366 // FDIV on SPU requires custom lowering
367 setOperationAction(ISD::FDIV, MVT::f64, Expand); // to libcall
369 // SPU has [U|S]INT_TO_FP for f32->i32, but not for f64->i32, f64->i64:
370 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
371 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote);
372 setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote);
373 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
374 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Promote);
375 setOperationAction(ISD::UINT_TO_FP, MVT::i8, Promote);
376 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
377 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
379 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Legal);
380 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Legal);
381 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Legal);
382 setOperationAction(ISD::BIT_CONVERT, MVT::f64, Legal);
384 // We cannot sextinreg(i1). Expand to shifts.
385 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
387 // We want to legalize GlobalAddress and ConstantPool nodes into the
388 // appropriate instructions to materialize the address.
389 for (unsigned sctype = (unsigned) MVT::i8; sctype < (unsigned) MVT::f128;
391 MVT::SimpleValueType VT = (MVT::SimpleValueType)sctype;
393 setOperationAction(ISD::GlobalAddress, VT, Custom);
394 setOperationAction(ISD::ConstantPool, VT, Custom);
395 setOperationAction(ISD::JumpTable, VT, Custom);
398 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
399 setOperationAction(ISD::VASTART , MVT::Other, Custom);
401 // Use the default implementation.
402 setOperationAction(ISD::VAARG , MVT::Other, Expand);
403 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
404 setOperationAction(ISD::VAEND , MVT::Other, Expand);
405 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
406 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
407 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand);
408 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Expand);
410 // Cell SPU has instructions for converting between i64 and fp.
411 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
412 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
414 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT
415 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote);
417 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
418 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
420 // First set operation action for all vector types to expand. Then we
421 // will selectively turn on ones that can be effectively codegen'd.
422 addRegisterClass(MVT::v16i8, SPU::VECREGRegisterClass);
423 addRegisterClass(MVT::v8i16, SPU::VECREGRegisterClass);
424 addRegisterClass(MVT::v4i32, SPU::VECREGRegisterClass);
425 addRegisterClass(MVT::v2i64, SPU::VECREGRegisterClass);
426 addRegisterClass(MVT::v4f32, SPU::VECREGRegisterClass);
427 addRegisterClass(MVT::v2f64, SPU::VECREGRegisterClass);
429 // "Odd size" vector classes that we're willing to support:
430 addRegisterClass(MVT::v2i32, SPU::VECREGRegisterClass);
432 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
433 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
434 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
436 // add/sub are legal for all supported vector VT's.
437 setOperationAction(ISD::ADD, VT, Legal);
438 setOperationAction(ISD::SUB, VT, Legal);
439 // mul has to be custom lowered.
440 setOperationAction(ISD::MUL, VT, Legal);
442 setOperationAction(ISD::AND, VT, Legal);
443 setOperationAction(ISD::OR, VT, Legal);
444 setOperationAction(ISD::XOR, VT, Legal);
445 setOperationAction(ISD::LOAD, VT, Legal);
446 setOperationAction(ISD::SELECT, VT, Legal);
447 setOperationAction(ISD::STORE, VT, Legal);
449 // These operations need to be expanded:
450 setOperationAction(ISD::SDIV, VT, Expand);
451 setOperationAction(ISD::SREM, VT, Expand);
452 setOperationAction(ISD::UDIV, VT, Expand);
453 setOperationAction(ISD::UREM, VT, Expand);
455 // Custom lower build_vector, constant pool spills, insert and
456 // extract vector elements:
457 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
458 setOperationAction(ISD::ConstantPool, VT, Custom);
459 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
460 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
461 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
462 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
465 setOperationAction(ISD::AND, MVT::v16i8, Custom);
466 setOperationAction(ISD::OR, MVT::v16i8, Custom);
467 setOperationAction(ISD::XOR, MVT::v16i8, Custom);
468 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
470 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
472 setShiftAmountType(MVT::i32);
473 setBooleanContents(ZeroOrNegativeOneBooleanContent);
475 setStackPointerRegisterToSaveRestore(SPU::R1);
477 // We have target-specific dag combine patterns for the following nodes:
478 setTargetDAGCombine(ISD::ADD);
479 setTargetDAGCombine(ISD::ZERO_EXTEND);
480 setTargetDAGCombine(ISD::SIGN_EXTEND);
481 setTargetDAGCombine(ISD::ANY_EXTEND);
483 computeRegisterProperties();
485 // Set pre-RA register scheduler default to BURR, which produces slightly
486 // better code than the default (could also be TDRR, but TargetLowering.h
487 // needs a mod to support that model):
488 setSchedulingPreference(Sched::RegPressure);
492 SPUTargetLowering::getTargetNodeName(unsigned Opcode) const
494 if (node_names.empty()) {
495 node_names[(unsigned) SPUISD::RET_FLAG] = "SPUISD::RET_FLAG";
496 node_names[(unsigned) SPUISD::Hi] = "SPUISD::Hi";
497 node_names[(unsigned) SPUISD::Lo] = "SPUISD::Lo";
498 node_names[(unsigned) SPUISD::PCRelAddr] = "SPUISD::PCRelAddr";
499 node_names[(unsigned) SPUISD::AFormAddr] = "SPUISD::AFormAddr";
500 node_names[(unsigned) SPUISD::IndirectAddr] = "SPUISD::IndirectAddr";
501 node_names[(unsigned) SPUISD::LDRESULT] = "SPUISD::LDRESULT";
502 node_names[(unsigned) SPUISD::CALL] = "SPUISD::CALL";
503 node_names[(unsigned) SPUISD::SHUFB] = "SPUISD::SHUFB";
504 node_names[(unsigned) SPUISD::SHUFFLE_MASK] = "SPUISD::SHUFFLE_MASK";
505 node_names[(unsigned) SPUISD::CNTB] = "SPUISD::CNTB";
506 node_names[(unsigned) SPUISD::PREFSLOT2VEC] = "SPUISD::PREFSLOT2VEC";
507 node_names[(unsigned) SPUISD::VEC2PREFSLOT] = "SPUISD::VEC2PREFSLOT";
508 node_names[(unsigned) SPUISD::SHLQUAD_L_BITS] = "SPUISD::SHLQUAD_L_BITS";
509 node_names[(unsigned) SPUISD::SHLQUAD_L_BYTES] = "SPUISD::SHLQUAD_L_BYTES";
510 node_names[(unsigned) SPUISD::VEC_ROTL] = "SPUISD::VEC_ROTL";
511 node_names[(unsigned) SPUISD::VEC_ROTR] = "SPUISD::VEC_ROTR";
512 node_names[(unsigned) SPUISD::ROTBYTES_LEFT] = "SPUISD::ROTBYTES_LEFT";
513 node_names[(unsigned) SPUISD::ROTBYTES_LEFT_BITS] =
514 "SPUISD::ROTBYTES_LEFT_BITS";
515 node_names[(unsigned) SPUISD::SELECT_MASK] = "SPUISD::SELECT_MASK";
516 node_names[(unsigned) SPUISD::SELB] = "SPUISD::SELB";
517 node_names[(unsigned) SPUISD::ADD64_MARKER] = "SPUISD::ADD64_MARKER";
518 node_names[(unsigned) SPUISD::SUB64_MARKER] = "SPUISD::SUB64_MARKER";
519 node_names[(unsigned) SPUISD::MUL64_MARKER] = "SPUISD::MUL64_MARKER";
522 std::map<unsigned, const char *>::iterator i = node_names.find(Opcode);
524 return ((i != node_names.end()) ? i->second : 0);
527 /// getFunctionAlignment - Return the Log2 alignment of this function.
528 unsigned SPUTargetLowering::getFunctionAlignment(const Function *) const {
532 //===----------------------------------------------------------------------===//
533 // Return the Cell SPU's SETCC result type
534 //===----------------------------------------------------------------------===//
536 MVT::SimpleValueType SPUTargetLowering::getSetCCResultType(EVT VT) const {
537 // i16 and i32 are valid SETCC result types
538 return ((VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) ?
539 VT.getSimpleVT().SimpleTy :
543 //===----------------------------------------------------------------------===//
544 // Calling convention code:
545 //===----------------------------------------------------------------------===//
547 #include "SPUGenCallingConv.inc"
549 //===----------------------------------------------------------------------===//
550 // LowerOperation implementation
551 //===----------------------------------------------------------------------===//
553 /// Custom lower loads for CellSPU
555 All CellSPU loads and stores are aligned to 16-byte boundaries, so for elements
556 within a 16-byte block, we have to rotate to extract the requested element.
558 For extending loads, we also want to ensure that the following sequence is
559 emitted, e.g. for MVT::f32 extending load to MVT::f64:
563 %2 v16i8,ch = rotate %1
564 %3 v4f8, ch = bitconvert %2
565 %4 f32 = vec2perfslot %3
566 %5 f64 = fp_extend %4
570 LowerLOAD(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
571 LoadSDNode *LN = cast<LoadSDNode>(Op);
572 SDValue the_chain = LN->getChain();
573 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
574 EVT InVT = LN->getMemoryVT();
575 EVT OutVT = Op.getValueType();
576 ISD::LoadExtType ExtType = LN->getExtensionType();
577 unsigned alignment = LN->getAlignment();
578 const valtype_map_s *vtm = getValueTypeMapEntry(InVT);
579 DebugLoc dl = Op.getDebugLoc();
581 switch (LN->getAddressingMode()) {
582 case ISD::UNINDEXED: {
584 SDValue basePtr = LN->getBasePtr();
587 if (alignment == 16) {
590 // Special cases for a known aligned load to simplify the base pointer
591 // and the rotation amount:
592 if (basePtr.getOpcode() == ISD::ADD
593 && (CN = dyn_cast<ConstantSDNode > (basePtr.getOperand(1))) != 0) {
594 // Known offset into basePtr
595 int64_t offset = CN->getSExtValue();
596 int64_t rotamt = int64_t((offset & 0xf) - vtm->prefslot_byte);
601 rotate = DAG.getConstant(rotamt, MVT::i16);
603 // Simplify the base pointer for this case:
604 basePtr = basePtr.getOperand(0);
605 if ((offset & ~0xf) > 0) {
606 basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT,
608 DAG.getConstant((offset & ~0xf), PtrVT));
610 } else if ((basePtr.getOpcode() == SPUISD::AFormAddr)
611 || (basePtr.getOpcode() == SPUISD::IndirectAddr
612 && basePtr.getOperand(0).getOpcode() == SPUISD::Hi
613 && basePtr.getOperand(1).getOpcode() == SPUISD::Lo)) {
614 // Plain aligned a-form address: rotate into preferred slot
615 // Same for (SPUindirect (SPUhi ...), (SPUlo ...))
616 int64_t rotamt = -vtm->prefslot_byte;
619 rotate = DAG.getConstant(rotamt, MVT::i16);
621 // Offset the rotate amount by the basePtr and the preferred slot
623 int64_t rotamt = -vtm->prefslot_byte;
626 rotate = DAG.getNode(ISD::ADD, dl, PtrVT,
628 DAG.getConstant(rotamt, PtrVT));
631 // Unaligned load: must be more pessimistic about addressing modes:
632 if (basePtr.getOpcode() == ISD::ADD) {
633 MachineFunction &MF = DAG.getMachineFunction();
634 MachineRegisterInfo &RegInfo = MF.getRegInfo();
635 unsigned VReg = RegInfo.createVirtualRegister(&SPU::R32CRegClass);
638 SDValue Op0 = basePtr.getOperand(0);
639 SDValue Op1 = basePtr.getOperand(1);
641 if (isa<ConstantSDNode>(Op1)) {
642 // Convert the (add <ptr>, <const>) to an indirect address contained
643 // in a register. Note that this is done because we need to avoid
644 // creating a 0(reg) d-form address due to the SPU's block loads.
645 basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Op0, Op1);
646 the_chain = DAG.getCopyToReg(the_chain, dl, VReg, basePtr, Flag);
647 basePtr = DAG.getCopyFromReg(the_chain, dl, VReg, PtrVT);
649 // Convert the (add <arg1>, <arg2>) to an indirect address, which
650 // will likely be lowered as a reg(reg) x-form address.
651 basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Op0, Op1);
654 basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT,
656 DAG.getConstant(0, PtrVT));
659 // Offset the rotate amount by the basePtr and the preferred slot
661 rotate = DAG.getNode(ISD::ADD, dl, PtrVT,
663 DAG.getConstant(-vtm->prefslot_byte, PtrVT));
666 // Re-emit as a v16i8 vector load
667 result = DAG.getLoad(MVT::v16i8, dl, the_chain, basePtr,
668 LN->getSrcValue(), LN->getSrcValueOffset(),
669 LN->isVolatile(), LN->isNonTemporal(), 16);
672 the_chain = result.getValue(1);
674 // Rotate into the preferred slot:
675 result = DAG.getNode(SPUISD::ROTBYTES_LEFT, dl, MVT::v16i8,
676 result.getValue(0), rotate);
678 // Convert the loaded v16i8 vector to the appropriate vector type
679 // specified by the operand:
680 EVT vecVT = EVT::getVectorVT(*DAG.getContext(),
681 InVT, (128 / InVT.getSizeInBits()));
682 result = DAG.getNode(SPUISD::VEC2PREFSLOT, dl, InVT,
683 DAG.getNode(ISD::BIT_CONVERT, dl, vecVT, result));
685 // Handle extending loads by extending the scalar result:
686 if (ExtType == ISD::SEXTLOAD) {
687 result = DAG.getNode(ISD::SIGN_EXTEND, dl, OutVT, result);
688 } else if (ExtType == ISD::ZEXTLOAD) {
689 result = DAG.getNode(ISD::ZERO_EXTEND, dl, OutVT, result);
690 } else if (ExtType == ISD::EXTLOAD) {
691 unsigned NewOpc = ISD::ANY_EXTEND;
693 if (OutVT.isFloatingPoint())
694 NewOpc = ISD::FP_EXTEND;
696 result = DAG.getNode(NewOpc, dl, OutVT, result);
699 SDVTList retvts = DAG.getVTList(OutVT, MVT::Other);
700 SDValue retops[2] = {
705 result = DAG.getNode(SPUISD::LDRESULT, dl, retvts,
706 retops, sizeof(retops) / sizeof(retops[0]));
713 case ISD::LAST_INDEXED_MODE:
715 report_fatal_error("LowerLOAD: Got a LoadSDNode with an addr mode other "
717 Twine((unsigned)LN->getAddressingMode()));
725 /// Custom lower stores for CellSPU
727 All CellSPU stores are aligned to 16-byte boundaries, so for elements
728 within a 16-byte block, we have to generate a shuffle to insert the
729 requested element into its place, then store the resulting block.
732 LowerSTORE(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
733 StoreSDNode *SN = cast<StoreSDNode>(Op);
734 SDValue Value = SN->getValue();
735 EVT VT = Value.getValueType();
736 EVT StVT = (!SN->isTruncatingStore() ? VT : SN->getMemoryVT());
737 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
738 DebugLoc dl = Op.getDebugLoc();
739 unsigned alignment = SN->getAlignment();
741 switch (SN->getAddressingMode()) {
742 case ISD::UNINDEXED: {
743 // The vector type we really want to load from the 16-byte chunk.
744 EVT vecVT = EVT::getVectorVT(*DAG.getContext(),
745 VT, (128 / VT.getSizeInBits()));
747 SDValue alignLoadVec;
748 SDValue basePtr = SN->getBasePtr();
749 SDValue the_chain = SN->getChain();
750 SDValue insertEltOffs;
752 if (alignment == 16) {
755 // Special cases for a known aligned load to simplify the base pointer
756 // and insertion byte:
757 if (basePtr.getOpcode() == ISD::ADD
758 && (CN = dyn_cast<ConstantSDNode>(basePtr.getOperand(1))) != 0) {
759 // Known offset into basePtr
760 int64_t offset = CN->getSExtValue();
762 // Simplify the base pointer for this case:
763 basePtr = basePtr.getOperand(0);
764 insertEltOffs = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT,
766 DAG.getConstant((offset & 0xf), PtrVT));
768 if ((offset & ~0xf) > 0) {
769 basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT,
771 DAG.getConstant((offset & ~0xf), PtrVT));
774 // Otherwise, assume it's at byte 0 of basePtr
775 insertEltOffs = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT,
777 DAG.getConstant(0, PtrVT));
780 // Unaligned load: must be more pessimistic about addressing modes:
781 if (basePtr.getOpcode() == ISD::ADD) {
782 MachineFunction &MF = DAG.getMachineFunction();
783 MachineRegisterInfo &RegInfo = MF.getRegInfo();
784 unsigned VReg = RegInfo.createVirtualRegister(&SPU::R32CRegClass);
787 SDValue Op0 = basePtr.getOperand(0);
788 SDValue Op1 = basePtr.getOperand(1);
790 if (isa<ConstantSDNode>(Op1)) {
791 // Convert the (add <ptr>, <const>) to an indirect address contained
792 // in a register. Note that this is done because we need to avoid
793 // creating a 0(reg) d-form address due to the SPU's block loads.
794 basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Op0, Op1);
795 the_chain = DAG.getCopyToReg(the_chain, dl, VReg, basePtr, Flag);
796 basePtr = DAG.getCopyFromReg(the_chain, dl, VReg, PtrVT);
798 // Convert the (add <arg1>, <arg2>) to an indirect address, which
799 // will likely be lowered as a reg(reg) x-form address.
800 basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Op0, Op1);
803 basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT,
805 DAG.getConstant(0, PtrVT));
808 // Insertion point is solely determined by basePtr's contents
809 insertEltOffs = DAG.getNode(ISD::ADD, dl, PtrVT,
811 DAG.getConstant(0, PtrVT));
814 // Re-emit as a v16i8 vector load
815 alignLoadVec = DAG.getLoad(MVT::v16i8, dl, the_chain, basePtr,
816 SN->getSrcValue(), SN->getSrcValueOffset(),
817 SN->isVolatile(), SN->isNonTemporal(), 16);
820 the_chain = alignLoadVec.getValue(1);
822 LoadSDNode *LN = cast<LoadSDNode>(alignLoadVec);
823 SDValue theValue = SN->getValue();
827 && (theValue.getOpcode() == ISD::AssertZext
828 || theValue.getOpcode() == ISD::AssertSext)) {
829 // Drill down and get the value for zero- and sign-extended
831 theValue = theValue.getOperand(0);
834 // If the base pointer is already a D-form address, then just create
835 // a new D-form address with a slot offset and the orignal base pointer.
836 // Otherwise generate a D-form address with the slot offset relative
837 // to the stack pointer, which is always aligned.
839 if (DebugFlag && isCurrentDebugType(DEBUG_TYPE)) {
840 errs() << "CellSPU LowerSTORE: basePtr = ";
841 basePtr.getNode()->dump(&DAG);
846 SDValue insertEltOp =
847 DAG.getNode(SPUISD::SHUFFLE_MASK, dl, vecVT, insertEltOffs);
848 SDValue vectorizeOp =
849 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, vecVT, theValue);
851 result = DAG.getNode(SPUISD::SHUFB, dl, vecVT,
852 vectorizeOp, alignLoadVec,
853 DAG.getNode(ISD::BIT_CONVERT, dl,
854 MVT::v4i32, insertEltOp));
856 result = DAG.getStore(the_chain, dl, result, basePtr,
857 LN->getSrcValue(), LN->getSrcValueOffset(),
858 LN->isVolatile(), LN->isNonTemporal(),
861 #if 0 && !defined(NDEBUG)
862 if (DebugFlag && isCurrentDebugType(DEBUG_TYPE)) {
863 const SDValue ¤tRoot = DAG.getRoot();
866 errs() << "------- CellSPU:LowerStore result:\n";
868 errs() << "-------\n";
869 DAG.setRoot(currentRoot);
880 case ISD::LAST_INDEXED_MODE:
882 report_fatal_error("LowerLOAD: Got a LoadSDNode with an addr mode other "
884 Twine((unsigned)SN->getAddressingMode()));
892 //! Generate the address of a constant pool entry.
894 LowerConstantPool(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
895 EVT PtrVT = Op.getValueType();
896 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
897 const Constant *C = CP->getConstVal();
898 SDValue CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment());
899 SDValue Zero = DAG.getConstant(0, PtrVT);
900 const TargetMachine &TM = DAG.getTarget();
901 // FIXME there is no actual debug info here
902 DebugLoc dl = Op.getDebugLoc();
904 if (TM.getRelocationModel() == Reloc::Static) {
905 if (!ST->usingLargeMem()) {
906 // Just return the SDValue with the constant pool address in it.
907 return DAG.getNode(SPUISD::AFormAddr, dl, PtrVT, CPI, Zero);
909 SDValue Hi = DAG.getNode(SPUISD::Hi, dl, PtrVT, CPI, Zero);
910 SDValue Lo = DAG.getNode(SPUISD::Lo, dl, PtrVT, CPI, Zero);
911 return DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Hi, Lo);
915 llvm_unreachable("LowerConstantPool: Relocation model other than static"
920 //! Alternate entry point for generating the address of a constant pool entry
922 SPU::LowerConstantPool(SDValue Op, SelectionDAG &DAG, const SPUTargetMachine &TM) {
923 return ::LowerConstantPool(Op, DAG, TM.getSubtargetImpl());
927 LowerJumpTable(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
928 EVT PtrVT = Op.getValueType();
929 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
930 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
931 SDValue Zero = DAG.getConstant(0, PtrVT);
932 const TargetMachine &TM = DAG.getTarget();
933 // FIXME there is no actual debug info here
934 DebugLoc dl = Op.getDebugLoc();
936 if (TM.getRelocationModel() == Reloc::Static) {
937 if (!ST->usingLargeMem()) {
938 return DAG.getNode(SPUISD::AFormAddr, dl, PtrVT, JTI, Zero);
940 SDValue Hi = DAG.getNode(SPUISD::Hi, dl, PtrVT, JTI, Zero);
941 SDValue Lo = DAG.getNode(SPUISD::Lo, dl, PtrVT, JTI, Zero);
942 return DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Hi, Lo);
946 llvm_unreachable("LowerJumpTable: Relocation model other than static"
952 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
953 EVT PtrVT = Op.getValueType();
954 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
955 const GlobalValue *GV = GSDN->getGlobal();
956 SDValue GA = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
957 PtrVT, GSDN->getOffset());
958 const TargetMachine &TM = DAG.getTarget();
959 SDValue Zero = DAG.getConstant(0, PtrVT);
960 // FIXME there is no actual debug info here
961 DebugLoc dl = Op.getDebugLoc();
963 if (TM.getRelocationModel() == Reloc::Static) {
964 if (!ST->usingLargeMem()) {
965 return DAG.getNode(SPUISD::AFormAddr, dl, PtrVT, GA, Zero);
967 SDValue Hi = DAG.getNode(SPUISD::Hi, dl, PtrVT, GA, Zero);
968 SDValue Lo = DAG.getNode(SPUISD::Lo, dl, PtrVT, GA, Zero);
969 return DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Hi, Lo);
972 report_fatal_error("LowerGlobalAddress: Relocation model other than static"
980 //! Custom lower double precision floating point constants
982 LowerConstantFP(SDValue Op, SelectionDAG &DAG) {
983 EVT VT = Op.getValueType();
984 // FIXME there is no actual debug info here
985 DebugLoc dl = Op.getDebugLoc();
987 if (VT == MVT::f64) {
988 ConstantFPSDNode *FP = cast<ConstantFPSDNode>(Op.getNode());
991 "LowerConstantFP: Node is not ConstantFPSDNode");
993 uint64_t dbits = DoubleToBits(FP->getValueAPF().convertToDouble());
994 SDValue T = DAG.getConstant(dbits, MVT::i64);
995 SDValue Tvec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, T, T);
996 return DAG.getNode(SPUISD::VEC2PREFSLOT, dl, VT,
997 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Tvec));
1004 SPUTargetLowering::LowerFormalArguments(SDValue Chain,
1005 CallingConv::ID CallConv, bool isVarArg,
1006 const SmallVectorImpl<ISD::InputArg>
1008 DebugLoc dl, SelectionDAG &DAG,
1009 SmallVectorImpl<SDValue> &InVals)
1012 MachineFunction &MF = DAG.getMachineFunction();
1013 MachineFrameInfo *MFI = MF.getFrameInfo();
1014 MachineRegisterInfo &RegInfo = MF.getRegInfo();
1015 SPUFunctionInfo *FuncInfo = MF.getInfo<SPUFunctionInfo>();
1017 const unsigned *ArgRegs = SPURegisterInfo::getArgRegs();
1018 const unsigned NumArgRegs = SPURegisterInfo::getNumArgRegs();
1020 unsigned ArgOffset = SPUFrameInfo::minStackSize();
1021 unsigned ArgRegIdx = 0;
1022 unsigned StackSlotSize = SPUFrameInfo::stackSlotSize();
1024 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1026 // Add DAG nodes to load the arguments or copy them out of registers.
1027 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
1028 EVT ObjectVT = Ins[ArgNo].VT;
1029 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
1032 if (ArgRegIdx < NumArgRegs) {
1033 const TargetRegisterClass *ArgRegClass;
1035 switch (ObjectVT.getSimpleVT().SimpleTy) {
1037 report_fatal_error("LowerFormalArguments Unhandled argument type: " +
1038 Twine(ObjectVT.getEVTString()));
1040 ArgRegClass = &SPU::R8CRegClass;
1043 ArgRegClass = &SPU::R16CRegClass;
1046 ArgRegClass = &SPU::R32CRegClass;
1049 ArgRegClass = &SPU::R64CRegClass;
1052 ArgRegClass = &SPU::GPRCRegClass;
1055 ArgRegClass = &SPU::R32FPRegClass;
1058 ArgRegClass = &SPU::R64FPRegClass;
1066 ArgRegClass = &SPU::VECREGRegClass;
1070 unsigned VReg = RegInfo.createVirtualRegister(ArgRegClass);
1071 RegInfo.addLiveIn(ArgRegs[ArgRegIdx], VReg);
1072 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
1075 // We need to load the argument to a virtual register if we determined
1076 // above that we ran out of physical registers of the appropriate type
1077 // or we're forced to do vararg
1078 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset, true);
1079 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1080 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, NULL, 0, false, false, 0);
1081 ArgOffset += StackSlotSize;
1084 InVals.push_back(ArgVal);
1086 Chain = ArgVal.getOperand(0);
1091 // unsigned int ptr_size = PtrVT.getSizeInBits() / 8;
1092 // We will spill (79-3)+1 registers to the stack
1093 SmallVector<SDValue, 79-3+1> MemOps;
1095 // Create the frame slot
1097 for (; ArgRegIdx != NumArgRegs; ++ArgRegIdx) {
1098 FuncInfo->setVarArgsFrameIndex(
1099 MFI->CreateFixedObject(StackSlotSize, ArgOffset, true));
1100 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1101 unsigned VReg = MF.addLiveIn(ArgRegs[ArgRegIdx], &SPU::R32CRegClass);
1102 SDValue ArgVal = DAG.getRegister(VReg, MVT::v16i8);
1103 SDValue Store = DAG.getStore(Chain, dl, ArgVal, FIN, NULL, 0,
1105 Chain = Store.getOperand(0);
1106 MemOps.push_back(Store);
1108 // Increment address by stack slot size for the next stored argument
1109 ArgOffset += StackSlotSize;
1111 if (!MemOps.empty())
1112 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1113 &MemOps[0], MemOps.size());
1119 /// isLSAAddress - Return the immediate to use if the specified
1120 /// value is representable as a LSA address.
1121 static SDNode *isLSAAddress(SDValue Op, SelectionDAG &DAG) {
1122 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
1125 int Addr = C->getZExtValue();
1126 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
1127 (Addr << 14 >> 14) != Addr)
1128 return 0; // Top 14 bits have to be sext of immediate.
1130 return DAG.getConstant((int)C->getZExtValue() >> 2, MVT::i32).getNode();
1134 SPUTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1135 CallingConv::ID CallConv, bool isVarArg,
1137 const SmallVectorImpl<ISD::OutputArg> &Outs,
1138 const SmallVectorImpl<ISD::InputArg> &Ins,
1139 DebugLoc dl, SelectionDAG &DAG,
1140 SmallVectorImpl<SDValue> &InVals) const {
1141 // CellSPU target does not yet support tail call optimization.
1144 const SPUSubtarget *ST = SPUTM.getSubtargetImpl();
1145 unsigned NumOps = Outs.size();
1146 unsigned StackSlotSize = SPUFrameInfo::stackSlotSize();
1147 const unsigned *ArgRegs = SPURegisterInfo::getArgRegs();
1148 const unsigned NumArgRegs = SPURegisterInfo::getNumArgRegs();
1150 // Handy pointer type
1151 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1153 // Set up a copy of the stack pointer for use loading and storing any
1154 // arguments that may not fit in the registers available for argument
1156 SDValue StackPtr = DAG.getRegister(SPU::R1, MVT::i32);
1158 // Figure out which arguments are going to go in registers, and which in
1160 unsigned ArgOffset = SPUFrameInfo::minStackSize(); // Just below [LR]
1161 unsigned ArgRegIdx = 0;
1163 // Keep track of registers passing arguments
1164 std::vector<std::pair<unsigned, SDValue> > RegsToPass;
1165 // And the arguments passed on the stack
1166 SmallVector<SDValue, 8> MemOpChains;
1168 for (unsigned i = 0; i != NumOps; ++i) {
1169 SDValue Arg = Outs[i].Val;
1171 // PtrOff will be used to store the current argument to the stack if a
1172 // register cannot be found for it.
1173 SDValue PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
1174 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
1176 switch (Arg.getValueType().getSimpleVT().SimpleTy) {
1177 default: llvm_unreachable("Unexpected ValueType for argument!");
1191 if (ArgRegIdx != NumArgRegs) {
1192 RegsToPass.push_back(std::make_pair(ArgRegs[ArgRegIdx++], Arg));
1194 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0,
1196 ArgOffset += StackSlotSize;
1202 // Accumulate how many bytes are to be pushed on the stack, including the
1203 // linkage area, and parameter passing area. According to the SPU ABI,
1204 // we minimally need space for [LR] and [SP].
1205 unsigned NumStackBytes = ArgOffset - SPUFrameInfo::minStackSize();
1207 // Insert a call sequence start
1208 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumStackBytes,
1211 if (!MemOpChains.empty()) {
1212 // Adjust the stack pointer for the stack arguments.
1213 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1214 &MemOpChains[0], MemOpChains.size());
1217 // Build a sequence of copy-to-reg nodes chained together with token chain
1218 // and flag operands which copy the outgoing args into the appropriate regs.
1220 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1221 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1222 RegsToPass[i].second, InFlag);
1223 InFlag = Chain.getValue(1);
1226 SmallVector<SDValue, 8> Ops;
1227 unsigned CallOpc = SPUISD::CALL;
1229 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1230 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1231 // node so that legalize doesn't hack it.
1232 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1233 const GlobalValue *GV = G->getGlobal();
1234 EVT CalleeVT = Callee.getValueType();
1235 SDValue Zero = DAG.getConstant(0, PtrVT);
1236 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, CalleeVT);
1238 if (!ST->usingLargeMem()) {
1239 // Turn calls to targets that are defined (i.e., have bodies) into BRSL
1240 // style calls, otherwise, external symbols are BRASL calls. This assumes
1241 // that declared/defined symbols are in the same compilation unit and can
1242 // be reached through PC-relative jumps.
1245 // This may be an unsafe assumption for JIT and really large compilation
1247 if (GV->isDeclaration()) {
1248 Callee = DAG.getNode(SPUISD::AFormAddr, dl, CalleeVT, GA, Zero);
1250 Callee = DAG.getNode(SPUISD::PCRelAddr, dl, CalleeVT, GA, Zero);
1253 // "Large memory" mode: Turn all calls into indirect calls with a X-form
1255 Callee = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, GA, Zero);
1257 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1258 EVT CalleeVT = Callee.getValueType();
1259 SDValue Zero = DAG.getConstant(0, PtrVT);
1260 SDValue ExtSym = DAG.getTargetExternalSymbol(S->getSymbol(),
1261 Callee.getValueType());
1263 if (!ST->usingLargeMem()) {
1264 Callee = DAG.getNode(SPUISD::AFormAddr, dl, CalleeVT, ExtSym, Zero);
1266 Callee = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, ExtSym, Zero);
1268 } else if (SDNode *Dest = isLSAAddress(Callee, DAG)) {
1269 // If this is an absolute destination address that appears to be a legal
1270 // local store address, use the munged value.
1271 Callee = SDValue(Dest, 0);
1274 Ops.push_back(Chain);
1275 Ops.push_back(Callee);
1277 // Add argument registers to the end of the list so that they are known live
1279 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1280 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1281 RegsToPass[i].second.getValueType()));
1283 if (InFlag.getNode())
1284 Ops.push_back(InFlag);
1285 // Returns a chain and a flag for retval copy to use.
1286 Chain = DAG.getNode(CallOpc, dl, DAG.getVTList(MVT::Other, MVT::Flag),
1287 &Ops[0], Ops.size());
1288 InFlag = Chain.getValue(1);
1290 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumStackBytes, true),
1291 DAG.getIntPtrConstant(0, true), InFlag);
1293 InFlag = Chain.getValue(1);
1295 // If the function returns void, just return the chain.
1299 // If the call has results, copy the values out of the ret val registers.
1300 switch (Ins[0].VT.getSimpleVT().SimpleTy) {
1301 default: llvm_unreachable("Unexpected ret value!");
1302 case MVT::Other: break;
1304 if (Ins.size() > 1 && Ins[1].VT == MVT::i32) {
1305 Chain = DAG.getCopyFromReg(Chain, dl, SPU::R4,
1306 MVT::i32, InFlag).getValue(1);
1307 InVals.push_back(Chain.getValue(0));
1308 Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, MVT::i32,
1309 Chain.getValue(2)).getValue(1);
1310 InVals.push_back(Chain.getValue(0));
1312 Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, MVT::i32,
1313 InFlag).getValue(1);
1314 InVals.push_back(Chain.getValue(0));
1329 Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, Ins[0].VT,
1330 InFlag).getValue(1);
1331 InVals.push_back(Chain.getValue(0));
1339 SPUTargetLowering::LowerReturn(SDValue Chain,
1340 CallingConv::ID CallConv, bool isVarArg,
1341 const SmallVectorImpl<ISD::OutputArg> &Outs,
1342 DebugLoc dl, SelectionDAG &DAG) const {
1344 SmallVector<CCValAssign, 16> RVLocs;
1345 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1346 RVLocs, *DAG.getContext());
1347 CCInfo.AnalyzeReturn(Outs, RetCC_SPU);
1349 // If this is the first return lowered for this function, add the regs to the
1350 // liveout set for the function.
1351 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1352 for (unsigned i = 0; i != RVLocs.size(); ++i)
1353 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1358 // Copy the result values into the output registers.
1359 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1360 CCValAssign &VA = RVLocs[i];
1361 assert(VA.isRegLoc() && "Can only return in registers!");
1362 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1364 Flag = Chain.getValue(1);
1368 return DAG.getNode(SPUISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
1370 return DAG.getNode(SPUISD::RET_FLAG, dl, MVT::Other, Chain);
1374 //===----------------------------------------------------------------------===//
1375 // Vector related lowering:
1376 //===----------------------------------------------------------------------===//
1378 static ConstantSDNode *
1379 getVecImm(SDNode *N) {
1380 SDValue OpVal(0, 0);
1382 // Check to see if this buildvec has a single non-undef value in its elements.
1383 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1384 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1385 if (OpVal.getNode() == 0)
1386 OpVal = N->getOperand(i);
1387 else if (OpVal != N->getOperand(i))
1391 if (OpVal.getNode() != 0) {
1392 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1400 /// get_vec_i18imm - Test if this vector is a vector filled with the same value
1401 /// and the value fits into an unsigned 18-bit constant, and if so, return the
1403 SDValue SPU::get_vec_u18imm(SDNode *N, SelectionDAG &DAG,
1405 if (ConstantSDNode *CN = getVecImm(N)) {
1406 uint64_t Value = CN->getZExtValue();
1407 if (ValueType == MVT::i64) {
1408 uint64_t UValue = CN->getZExtValue();
1409 uint32_t upper = uint32_t(UValue >> 32);
1410 uint32_t lower = uint32_t(UValue);
1413 Value = Value >> 32;
1415 if (Value <= 0x3ffff)
1416 return DAG.getTargetConstant(Value, ValueType);
1422 /// get_vec_i16imm - Test if this vector is a vector filled with the same value
1423 /// and the value fits into a signed 16-bit constant, and if so, return the
1425 SDValue SPU::get_vec_i16imm(SDNode *N, SelectionDAG &DAG,
1427 if (ConstantSDNode *CN = getVecImm(N)) {
1428 int64_t Value = CN->getSExtValue();
1429 if (ValueType == MVT::i64) {
1430 uint64_t UValue = CN->getZExtValue();
1431 uint32_t upper = uint32_t(UValue >> 32);
1432 uint32_t lower = uint32_t(UValue);
1435 Value = Value >> 32;
1437 if (Value >= -(1 << 15) && Value <= ((1 << 15) - 1)) {
1438 return DAG.getTargetConstant(Value, ValueType);
1445 /// get_vec_i10imm - Test if this vector is a vector filled with the same value
1446 /// and the value fits into a signed 10-bit constant, and if so, return the
1448 SDValue SPU::get_vec_i10imm(SDNode *N, SelectionDAG &DAG,
1450 if (ConstantSDNode *CN = getVecImm(N)) {
1451 int64_t Value = CN->getSExtValue();
1452 if (ValueType == MVT::i64) {
1453 uint64_t UValue = CN->getZExtValue();
1454 uint32_t upper = uint32_t(UValue >> 32);
1455 uint32_t lower = uint32_t(UValue);
1458 Value = Value >> 32;
1460 if (isInt<10>(Value))
1461 return DAG.getTargetConstant(Value, ValueType);
1467 /// get_vec_i8imm - Test if this vector is a vector filled with the same value
1468 /// and the value fits into a signed 8-bit constant, and if so, return the
1471 /// @note: The incoming vector is v16i8 because that's the only way we can load
1472 /// constant vectors. Thus, we test to see if the upper and lower bytes are the
1474 SDValue SPU::get_vec_i8imm(SDNode *N, SelectionDAG &DAG,
1476 if (ConstantSDNode *CN = getVecImm(N)) {
1477 int Value = (int) CN->getZExtValue();
1478 if (ValueType == MVT::i16
1479 && Value <= 0xffff /* truncated from uint64_t */
1480 && ((short) Value >> 8) == ((short) Value & 0xff))
1481 return DAG.getTargetConstant(Value & 0xff, ValueType);
1482 else if (ValueType == MVT::i8
1483 && (Value & 0xff) == Value)
1484 return DAG.getTargetConstant(Value, ValueType);
1490 /// get_ILHUvec_imm - Test if this vector is a vector filled with the same value
1491 /// and the value fits into a signed 16-bit constant, and if so, return the
1493 SDValue SPU::get_ILHUvec_imm(SDNode *N, SelectionDAG &DAG,
1495 if (ConstantSDNode *CN = getVecImm(N)) {
1496 uint64_t Value = CN->getZExtValue();
1497 if ((ValueType == MVT::i32
1498 && ((unsigned) Value & 0xffff0000) == (unsigned) Value)
1499 || (ValueType == MVT::i64 && (Value & 0xffff0000) == Value))
1500 return DAG.getTargetConstant(Value >> 16, ValueType);
1506 /// get_v4i32_imm - Catch-all for general 32-bit constant vectors
1507 SDValue SPU::get_v4i32_imm(SDNode *N, SelectionDAG &DAG) {
1508 if (ConstantSDNode *CN = getVecImm(N)) {
1509 return DAG.getTargetConstant((unsigned) CN->getZExtValue(), MVT::i32);
1515 /// get_v4i32_imm - Catch-all for general 64-bit constant vectors
1516 SDValue SPU::get_v2i64_imm(SDNode *N, SelectionDAG &DAG) {
1517 if (ConstantSDNode *CN = getVecImm(N)) {
1518 return DAG.getTargetConstant((unsigned) CN->getZExtValue(), MVT::i64);
1524 //! Lower a BUILD_VECTOR instruction creatively:
1526 LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
1527 EVT VT = Op.getValueType();
1528 EVT EltVT = VT.getVectorElementType();
1529 DebugLoc dl = Op.getDebugLoc();
1530 BuildVectorSDNode *BCN = dyn_cast<BuildVectorSDNode>(Op.getNode());
1531 assert(BCN != 0 && "Expected BuildVectorSDNode in SPU LowerBUILD_VECTOR");
1532 unsigned minSplatBits = EltVT.getSizeInBits();
1534 if (minSplatBits < 16)
1537 APInt APSplatBits, APSplatUndef;
1538 unsigned SplatBitSize;
1541 if (!BCN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
1542 HasAnyUndefs, minSplatBits)
1543 || minSplatBits < SplatBitSize)
1544 return SDValue(); // Wasn't a constant vector or splat exceeded min
1546 uint64_t SplatBits = APSplatBits.getZExtValue();
1548 switch (VT.getSimpleVT().SimpleTy) {
1550 report_fatal_error("CellSPU: Unhandled VT in LowerBUILD_VECTOR, VT = " +
1551 Twine(VT.getEVTString()));
1554 uint32_t Value32 = uint32_t(SplatBits);
1555 assert(SplatBitSize == 32
1556 && "LowerBUILD_VECTOR: Unexpected floating point vector element.");
1557 // NOTE: pretend the constant is an integer. LLVM won't load FP constants
1558 SDValue T = DAG.getConstant(Value32, MVT::i32);
1559 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32,
1560 DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, T,T,T,T));
1564 uint64_t f64val = uint64_t(SplatBits);
1565 assert(SplatBitSize == 64
1566 && "LowerBUILD_VECTOR: 64-bit float vector size > 8 bytes.");
1567 // NOTE: pretend the constant is an integer. LLVM won't load FP constants
1568 SDValue T = DAG.getConstant(f64val, MVT::i64);
1569 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64,
1570 DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, T, T));
1574 // 8-bit constants have to be expanded to 16-bits
1575 unsigned short Value16 = SplatBits /* | (SplatBits << 8) */;
1576 SmallVector<SDValue, 8> Ops;
1578 Ops.assign(8, DAG.getConstant(Value16, MVT::i16));
1579 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
1580 DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i16, &Ops[0], Ops.size()));
1583 unsigned short Value16 = SplatBits;
1584 SDValue T = DAG.getConstant(Value16, EltVT);
1585 SmallVector<SDValue, 8> Ops;
1588 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
1591 SDValue T = DAG.getConstant(unsigned(SplatBits), VT.getVectorElementType());
1592 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, T, T, T, T);
1595 SDValue T = DAG.getConstant(unsigned(SplatBits), VT.getVectorElementType());
1596 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, T, T);
1599 return SPU::LowerV2I64Splat(VT, DAG, SplatBits, dl);
1609 SPU::LowerV2I64Splat(EVT OpVT, SelectionDAG& DAG, uint64_t SplatVal,
1611 uint32_t upper = uint32_t(SplatVal >> 32);
1612 uint32_t lower = uint32_t(SplatVal);
1614 if (upper == lower) {
1615 // Magic constant that can be matched by IL, ILA, et. al.
1616 SDValue Val = DAG.getTargetConstant(upper, MVT::i32);
1617 return DAG.getNode(ISD::BIT_CONVERT, dl, OpVT,
1618 DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
1619 Val, Val, Val, Val));
1621 bool upper_special, lower_special;
1623 // NOTE: This code creates common-case shuffle masks that can be easily
1624 // detected as common expressions. It is not attempting to create highly
1625 // specialized masks to replace any and all 0's, 0xff's and 0x80's.
1627 // Detect if the upper or lower half is a special shuffle mask pattern:
1628 upper_special = (upper == 0 || upper == 0xffffffff || upper == 0x80000000);
1629 lower_special = (lower == 0 || lower == 0xffffffff || lower == 0x80000000);
1631 // Both upper and lower are special, lower to a constant pool load:
1632 if (lower_special && upper_special) {
1633 SDValue SplatValCN = DAG.getConstant(SplatVal, MVT::i64);
1634 return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64,
1635 SplatValCN, SplatValCN);
1640 SmallVector<SDValue, 16> ShufBytes;
1643 // Create lower vector if not a special pattern
1644 if (!lower_special) {
1645 SDValue LO32C = DAG.getConstant(lower, MVT::i32);
1646 LO32 = DAG.getNode(ISD::BIT_CONVERT, dl, OpVT,
1647 DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
1648 LO32C, LO32C, LO32C, LO32C));
1651 // Create upper vector if not a special pattern
1652 if (!upper_special) {
1653 SDValue HI32C = DAG.getConstant(upper, MVT::i32);
1654 HI32 = DAG.getNode(ISD::BIT_CONVERT, dl, OpVT,
1655 DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
1656 HI32C, HI32C, HI32C, HI32C));
1659 // If either upper or lower are special, then the two input operands are
1660 // the same (basically, one of them is a "don't care")
1666 for (int i = 0; i < 4; ++i) {
1668 for (int j = 0; j < 4; ++j) {
1670 bool process_upper, process_lower;
1672 process_upper = (upper_special && (i & 1) == 0);
1673 process_lower = (lower_special && (i & 1) == 1);
1675 if (process_upper || process_lower) {
1676 if ((process_upper && upper == 0)
1677 || (process_lower && lower == 0))
1679 else if ((process_upper && upper == 0xffffffff)
1680 || (process_lower && lower == 0xffffffff))
1682 else if ((process_upper && upper == 0x80000000)
1683 || (process_lower && lower == 0x80000000))
1684 val |= (j == 0 ? 0xe0 : 0x80);
1686 val |= i * 4 + j + ((i & 1) * 16);
1689 ShufBytes.push_back(DAG.getConstant(val, MVT::i32));
1692 return DAG.getNode(SPUISD::SHUFB, dl, OpVT, HI32, LO32,
1693 DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
1694 &ShufBytes[0], ShufBytes.size()));
1698 /// LowerVECTOR_SHUFFLE - Lower a vector shuffle (V1, V2, V3) to something on
1699 /// which the Cell can operate. The code inspects V3 to ascertain whether the
1700 /// permutation vector, V3, is monotonically increasing with one "exception"
1701 /// element, e.g., (0, 1, _, 3). If this is the case, then generate a
1702 /// SHUFFLE_MASK synthetic instruction. Otherwise, spill V3 to the constant pool.
1703 /// In either case, the net result is going to eventually invoke SHUFB to
1704 /// permute/shuffle the bytes from V1 and V2.
1706 /// SHUFFLE_MASK is eventually selected as one of the C*D instructions, generate
1707 /// control word for byte/halfword/word insertion. This takes care of a single
1708 /// element move from V2 into V1.
1710 /// SPUISD::SHUFB is eventually selected as Cell's <i>shufb</i> instructions.
1711 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
1712 const ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op);
1713 SDValue V1 = Op.getOperand(0);
1714 SDValue V2 = Op.getOperand(1);
1715 DebugLoc dl = Op.getDebugLoc();
1717 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
1719 // If we have a single element being moved from V1 to V2, this can be handled
1720 // using the C*[DX] compute mask instructions, but the vector elements have
1721 // to be monotonically increasing with one exception element.
1722 EVT VecVT = V1.getValueType();
1723 EVT EltVT = VecVT.getVectorElementType();
1724 unsigned EltsFromV2 = 0;
1726 unsigned V2EltIdx0 = 0;
1727 unsigned CurrElt = 0;
1728 unsigned MaxElts = VecVT.getVectorNumElements();
1729 unsigned PrevElt = 0;
1731 bool monotonic = true;
1733 EVT maskVT; // which of the c?d instructions to use
1735 if (EltVT == MVT::i8) {
1737 maskVT = MVT::v16i8;
1738 } else if (EltVT == MVT::i16) {
1740 maskVT = MVT::v8i16;
1741 } else if (EltVT == MVT::i32 || EltVT == MVT::f32) {
1743 maskVT = MVT::v4i32;
1744 } else if (EltVT == MVT::i64 || EltVT == MVT::f64) {
1746 maskVT = MVT::v2i64;
1748 llvm_unreachable("Unhandled vector type in LowerVECTOR_SHUFFLE");
1750 for (unsigned i = 0; i != MaxElts; ++i) {
1751 if (SVN->getMaskElt(i) < 0)
1754 unsigned SrcElt = SVN->getMaskElt(i);
1757 if (SrcElt >= V2EltIdx0) {
1758 if (1 >= (++EltsFromV2)) {
1759 V2Elt = (V2EltIdx0 - SrcElt) << 2;
1761 } else if (CurrElt != SrcElt) {
1769 if (PrevElt > 0 && SrcElt < MaxElts) {
1770 if ((PrevElt == SrcElt - 1)
1771 || (PrevElt == MaxElts - 1 && SrcElt == 0)) {
1778 } else if (i == 0) {
1779 // First time through, need to keep track of previous element
1782 // This isn't a rotation, takes elements from vector 2
1788 if (EltsFromV2 == 1 && monotonic) {
1789 // Compute mask and shuffle
1790 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1792 // As SHUFFLE_MASK becomes a c?d instruction, feed it an address
1793 // R1 ($sp) is used here only as it is guaranteed to have last bits zero
1794 SDValue Pointer = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT,
1795 DAG.getRegister(SPU::R1, PtrVT),
1796 DAG.getConstant(V2Elt, MVT::i32));
1797 SDValue ShufMaskOp = DAG.getNode(SPUISD::SHUFFLE_MASK, dl,
1800 // Use shuffle mask in SHUFB synthetic instruction:
1801 return DAG.getNode(SPUISD::SHUFB, dl, V1.getValueType(), V2, V1,
1803 } else if (rotate) {
1804 int rotamt = (MaxElts - V0Elt) * EltVT.getSizeInBits()/8;
1806 return DAG.getNode(SPUISD::ROTBYTES_LEFT, dl, V1.getValueType(),
1807 V1, DAG.getConstant(rotamt, MVT::i16));
1809 // Convert the SHUFFLE_VECTOR mask's input element units to the
1811 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
1813 SmallVector<SDValue, 16> ResultMask;
1814 for (unsigned i = 0, e = MaxElts; i != e; ++i) {
1815 unsigned SrcElt = SVN->getMaskElt(i) < 0 ? 0 : SVN->getMaskElt(i);
1817 for (unsigned j = 0; j < BytesPerElement; ++j)
1818 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,MVT::i8));
1821 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
1822 &ResultMask[0], ResultMask.size());
1823 return DAG.getNode(SPUISD::SHUFB, dl, V1.getValueType(), V1, V2, VPermMask);
1827 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
1828 SDValue Op0 = Op.getOperand(0); // Op0 = the scalar
1829 DebugLoc dl = Op.getDebugLoc();
1831 if (Op0.getNode()->getOpcode() == ISD::Constant) {
1832 // For a constant, build the appropriate constant vector, which will
1833 // eventually simplify to a vector register load.
1835 ConstantSDNode *CN = cast<ConstantSDNode>(Op0.getNode());
1836 SmallVector<SDValue, 16> ConstVecValues;
1840 // Create a constant vector:
1841 switch (Op.getValueType().getSimpleVT().SimpleTy) {
1842 default: llvm_unreachable("Unexpected constant value type in "
1843 "LowerSCALAR_TO_VECTOR");
1844 case MVT::v16i8: n_copies = 16; VT = MVT::i8; break;
1845 case MVT::v8i16: n_copies = 8; VT = MVT::i16; break;
1846 case MVT::v4i32: n_copies = 4; VT = MVT::i32; break;
1847 case MVT::v4f32: n_copies = 4; VT = MVT::f32; break;
1848 case MVT::v2i64: n_copies = 2; VT = MVT::i64; break;
1849 case MVT::v2f64: n_copies = 2; VT = MVT::f64; break;
1852 SDValue CValue = DAG.getConstant(CN->getZExtValue(), VT);
1853 for (size_t j = 0; j < n_copies; ++j)
1854 ConstVecValues.push_back(CValue);
1856 return DAG.getNode(ISD::BUILD_VECTOR, dl, Op.getValueType(),
1857 &ConstVecValues[0], ConstVecValues.size());
1859 // Otherwise, copy the value from one register to another:
1860 switch (Op0.getValueType().getSimpleVT().SimpleTy) {
1861 default: llvm_unreachable("Unexpected value type in LowerSCALAR_TO_VECTOR");
1868 return DAG.getNode(SPUISD::PREFSLOT2VEC, dl, Op.getValueType(), Op0, Op0);
1875 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
1876 EVT VT = Op.getValueType();
1877 SDValue N = Op.getOperand(0);
1878 SDValue Elt = Op.getOperand(1);
1879 DebugLoc dl = Op.getDebugLoc();
1882 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
1883 // Constant argument:
1884 int EltNo = (int) C->getZExtValue();
1887 if (VT == MVT::i8 && EltNo >= 16)
1888 llvm_unreachable("SPU LowerEXTRACT_VECTOR_ELT: i8 extraction slot > 15");
1889 else if (VT == MVT::i16 && EltNo >= 8)
1890 llvm_unreachable("SPU LowerEXTRACT_VECTOR_ELT: i16 extraction slot > 7");
1891 else if (VT == MVT::i32 && EltNo >= 4)
1892 llvm_unreachable("SPU LowerEXTRACT_VECTOR_ELT: i32 extraction slot > 4");
1893 else if (VT == MVT::i64 && EltNo >= 2)
1894 llvm_unreachable("SPU LowerEXTRACT_VECTOR_ELT: i64 extraction slot > 2");
1896 if (EltNo == 0 && (VT == MVT::i32 || VT == MVT::i64)) {
1897 // i32 and i64: Element 0 is the preferred slot
1898 return DAG.getNode(SPUISD::VEC2PREFSLOT, dl, VT, N);
1901 // Need to generate shuffle mask and extract:
1902 int prefslot_begin = -1, prefslot_end = -1;
1903 int elt_byte = EltNo * VT.getSizeInBits() / 8;
1905 switch (VT.getSimpleVT().SimpleTy) {
1907 assert(false && "Invalid value type!");
1909 prefslot_begin = prefslot_end = 3;
1913 prefslot_begin = 2; prefslot_end = 3;
1918 prefslot_begin = 0; prefslot_end = 3;
1923 prefslot_begin = 0; prefslot_end = 7;
1928 assert(prefslot_begin != -1 && prefslot_end != -1 &&
1929 "LowerEXTRACT_VECTOR_ELT: preferred slots uninitialized");
1931 unsigned int ShufBytes[16] = {
1932 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
1934 for (int i = 0; i < 16; ++i) {
1935 // zero fill uppper part of preferred slot, don't care about the
1937 unsigned int mask_val;
1938 if (i <= prefslot_end) {
1940 ((i < prefslot_begin)
1942 : elt_byte + (i - prefslot_begin));
1944 ShufBytes[i] = mask_val;
1946 ShufBytes[i] = ShufBytes[i % (prefslot_end + 1)];
1949 SDValue ShufMask[4];
1950 for (unsigned i = 0; i < sizeof(ShufMask)/sizeof(ShufMask[0]); ++i) {
1951 unsigned bidx = i * 4;
1952 unsigned int bits = ((ShufBytes[bidx] << 24) |
1953 (ShufBytes[bidx+1] << 16) |
1954 (ShufBytes[bidx+2] << 8) |
1956 ShufMask[i] = DAG.getConstant(bits, MVT::i32);
1959 SDValue ShufMaskVec =
1960 DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
1961 &ShufMask[0], sizeof(ShufMask)/sizeof(ShufMask[0]));
1963 retval = DAG.getNode(SPUISD::VEC2PREFSLOT, dl, VT,
1964 DAG.getNode(SPUISD::SHUFB, dl, N.getValueType(),
1965 N, N, ShufMaskVec));
1967 // Variable index: Rotate the requested element into slot 0, then replicate
1968 // slot 0 across the vector
1969 EVT VecVT = N.getValueType();
1970 if (!VecVT.isSimple() || !VecVT.isVector() || !VecVT.is128BitVector()) {
1971 report_fatal_error("LowerEXTRACT_VECTOR_ELT: Must have a simple, 128-bit"
1975 // Make life easier by making sure the index is zero-extended to i32
1976 if (Elt.getValueType() != MVT::i32)
1977 Elt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Elt);
1979 // Scale the index to a bit/byte shift quantity
1981 APInt(32, uint64_t(16 / N.getValueType().getVectorNumElements()), false);
1982 unsigned scaleShift = scaleFactor.logBase2();
1985 if (scaleShift > 0) {
1986 // Scale the shift factor:
1987 Elt = DAG.getNode(ISD::SHL, dl, MVT::i32, Elt,
1988 DAG.getConstant(scaleShift, MVT::i32));
1991 vecShift = DAG.getNode(SPUISD::SHLQUAD_L_BYTES, dl, VecVT, N, Elt);
1993 // Replicate the bytes starting at byte 0 across the entire vector (for
1994 // consistency with the notion of a unified register set)
1997 switch (VT.getSimpleVT().SimpleTy) {
1999 report_fatal_error("LowerEXTRACT_VECTOR_ELT(varable): Unhandled vector"
2003 SDValue factor = DAG.getConstant(0x00000000, MVT::i32);
2004 replicate = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
2005 factor, factor, factor, factor);
2009 SDValue factor = DAG.getConstant(0x00010001, MVT::i32);
2010 replicate = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
2011 factor, factor, factor, factor);
2016 SDValue factor = DAG.getConstant(0x00010203, MVT::i32);
2017 replicate = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
2018 factor, factor, factor, factor);
2023 SDValue loFactor = DAG.getConstant(0x00010203, MVT::i32);
2024 SDValue hiFactor = DAG.getConstant(0x04050607, MVT::i32);
2025 replicate = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
2026 loFactor, hiFactor, loFactor, hiFactor);
2031 retval = DAG.getNode(SPUISD::VEC2PREFSLOT, dl, VT,
2032 DAG.getNode(SPUISD::SHUFB, dl, VecVT,
2033 vecShift, vecShift, replicate));
2039 static SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
2040 SDValue VecOp = Op.getOperand(0);
2041 SDValue ValOp = Op.getOperand(1);
2042 SDValue IdxOp = Op.getOperand(2);
2043 DebugLoc dl = Op.getDebugLoc();
2044 EVT VT = Op.getValueType();
2046 // use 0 when the lane to insert to is 'undef'
2048 if (IdxOp.getOpcode() != ISD::UNDEF) {
2049 ConstantSDNode *CN = cast<ConstantSDNode>(IdxOp);
2050 assert(CN != 0 && "LowerINSERT_VECTOR_ELT: Index is not constant!");
2051 Idx = (CN->getSExtValue());
2054 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2055 // Use $sp ($1) because it's always 16-byte aligned and it's available:
2056 SDValue Pointer = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT,
2057 DAG.getRegister(SPU::R1, PtrVT),
2058 DAG.getConstant(Idx, PtrVT));
2059 SDValue ShufMask = DAG.getNode(SPUISD::SHUFFLE_MASK, dl, VT, Pointer);
2062 DAG.getNode(SPUISD::SHUFB, dl, VT,
2063 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, ValOp),
2065 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, ShufMask));
2070 static SDValue LowerI8Math(SDValue Op, SelectionDAG &DAG, unsigned Opc,
2071 const TargetLowering &TLI)
2073 SDValue N0 = Op.getOperand(0); // Everything has at least one operand
2074 DebugLoc dl = Op.getDebugLoc();
2075 EVT ShiftVT = TLI.getShiftAmountTy();
2077 assert(Op.getValueType() == MVT::i8);
2080 llvm_unreachable("Unhandled i8 math operator");
2084 // 8-bit addition: Promote the arguments up to 16-bits and truncate
2086 SDValue N1 = Op.getOperand(1);
2087 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N0);
2088 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N1);
2089 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8,
2090 DAG.getNode(Opc, dl, MVT::i16, N0, N1));
2095 // 8-bit subtraction: Promote the arguments up to 16-bits and truncate
2097 SDValue N1 = Op.getOperand(1);
2098 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N0);
2099 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N1);
2100 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8,
2101 DAG.getNode(Opc, dl, MVT::i16, N0, N1));
2105 SDValue N1 = Op.getOperand(1);
2106 EVT N1VT = N1.getValueType();
2108 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, N0);
2109 if (!N1VT.bitsEq(ShiftVT)) {
2110 unsigned N1Opc = N1.getValueType().bitsLT(ShiftVT)
2113 N1 = DAG.getNode(N1Opc, dl, ShiftVT, N1);
2116 // Replicate lower 8-bits into upper 8:
2118 DAG.getNode(ISD::OR, dl, MVT::i16, N0,
2119 DAG.getNode(ISD::SHL, dl, MVT::i16,
2120 N0, DAG.getConstant(8, MVT::i32)));
2122 // Truncate back down to i8
2123 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8,
2124 DAG.getNode(Opc, dl, MVT::i16, ExpandArg, N1));
2128 SDValue N1 = Op.getOperand(1);
2129 EVT N1VT = N1.getValueType();
2131 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, N0);
2132 if (!N1VT.bitsEq(ShiftVT)) {
2133 unsigned N1Opc = ISD::ZERO_EXTEND;
2135 if (N1.getValueType().bitsGT(ShiftVT))
2136 N1Opc = ISD::TRUNCATE;
2138 N1 = DAG.getNode(N1Opc, dl, ShiftVT, N1);
2141 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8,
2142 DAG.getNode(Opc, dl, MVT::i16, N0, N1));
2145 SDValue N1 = Op.getOperand(1);
2146 EVT N1VT = N1.getValueType();
2148 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N0);
2149 if (!N1VT.bitsEq(ShiftVT)) {
2150 unsigned N1Opc = ISD::SIGN_EXTEND;
2152 if (N1VT.bitsGT(ShiftVT))
2153 N1Opc = ISD::TRUNCATE;
2154 N1 = DAG.getNode(N1Opc, dl, ShiftVT, N1);
2157 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8,
2158 DAG.getNode(Opc, dl, MVT::i16, N0, N1));
2161 SDValue N1 = Op.getOperand(1);
2163 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N0);
2164 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N1);
2165 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8,
2166 DAG.getNode(Opc, dl, MVT::i16, N0, N1));
2174 //! Lower byte immediate operations for v16i8 vectors:
2176 LowerByteImmed(SDValue Op, SelectionDAG &DAG) {
2179 EVT VT = Op.getValueType();
2180 DebugLoc dl = Op.getDebugLoc();
2182 ConstVec = Op.getOperand(0);
2183 Arg = Op.getOperand(1);
2184 if (ConstVec.getNode()->getOpcode() != ISD::BUILD_VECTOR) {
2185 if (ConstVec.getNode()->getOpcode() == ISD::BIT_CONVERT) {
2186 ConstVec = ConstVec.getOperand(0);
2188 ConstVec = Op.getOperand(1);
2189 Arg = Op.getOperand(0);
2190 if (ConstVec.getNode()->getOpcode() == ISD::BIT_CONVERT) {
2191 ConstVec = ConstVec.getOperand(0);
2196 if (ConstVec.getNode()->getOpcode() == ISD::BUILD_VECTOR) {
2197 BuildVectorSDNode *BCN = dyn_cast<BuildVectorSDNode>(ConstVec.getNode());
2198 assert(BCN != 0 && "Expected BuildVectorSDNode in SPU LowerByteImmed");
2200 APInt APSplatBits, APSplatUndef;
2201 unsigned SplatBitSize;
2203 unsigned minSplatBits = VT.getVectorElementType().getSizeInBits();
2205 if (BCN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
2206 HasAnyUndefs, minSplatBits)
2207 && minSplatBits <= SplatBitSize) {
2208 uint64_t SplatBits = APSplatBits.getZExtValue();
2209 SDValue tc = DAG.getTargetConstant(SplatBits & 0xff, MVT::i8);
2211 SmallVector<SDValue, 16> tcVec;
2212 tcVec.assign(16, tc);
2213 return DAG.getNode(Op.getNode()->getOpcode(), dl, VT, Arg,
2214 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &tcVec[0], tcVec.size()));
2218 // These operations (AND, OR, XOR) are legal, they just couldn't be custom
2219 // lowered. Return the operation, rather than a null SDValue.
2223 //! Custom lowering for CTPOP (count population)
2225 Custom lowering code that counts the number ones in the input
2226 operand. SPU has such an instruction, but it counts the number of
2227 ones per byte, which then have to be accumulated.
2229 static SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) {
2230 EVT VT = Op.getValueType();
2231 EVT vecVT = EVT::getVectorVT(*DAG.getContext(),
2232 VT, (128 / VT.getSizeInBits()));
2233 DebugLoc dl = Op.getDebugLoc();
2235 switch (VT.getSimpleVT().SimpleTy) {
2237 assert(false && "Invalid value type!");
2239 SDValue N = Op.getOperand(0);
2240 SDValue Elt0 = DAG.getConstant(0, MVT::i32);
2242 SDValue Promote = DAG.getNode(SPUISD::PREFSLOT2VEC, dl, vecVT, N, N);
2243 SDValue CNTB = DAG.getNode(SPUISD::CNTB, dl, vecVT, Promote);
2245 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i8, CNTB, Elt0);
2249 MachineFunction &MF = DAG.getMachineFunction();
2250 MachineRegisterInfo &RegInfo = MF.getRegInfo();
2252 unsigned CNTB_reg = RegInfo.createVirtualRegister(&SPU::R16CRegClass);
2254 SDValue N = Op.getOperand(0);
2255 SDValue Elt0 = DAG.getConstant(0, MVT::i16);
2256 SDValue Mask0 = DAG.getConstant(0x0f, MVT::i16);
2257 SDValue Shift1 = DAG.getConstant(8, MVT::i32);
2259 SDValue Promote = DAG.getNode(SPUISD::PREFSLOT2VEC, dl, vecVT, N, N);
2260 SDValue CNTB = DAG.getNode(SPUISD::CNTB, dl, vecVT, Promote);
2262 // CNTB_result becomes the chain to which all of the virtual registers
2263 // CNTB_reg, SUM1_reg become associated:
2264 SDValue CNTB_result =
2265 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, CNTB, Elt0);
2267 SDValue CNTB_rescopy =
2268 DAG.getCopyToReg(CNTB_result, dl, CNTB_reg, CNTB_result);
2270 SDValue Tmp1 = DAG.getCopyFromReg(CNTB_rescopy, dl, CNTB_reg, MVT::i16);
2272 return DAG.getNode(ISD::AND, dl, MVT::i16,
2273 DAG.getNode(ISD::ADD, dl, MVT::i16,
2274 DAG.getNode(ISD::SRL, dl, MVT::i16,
2281 MachineFunction &MF = DAG.getMachineFunction();
2282 MachineRegisterInfo &RegInfo = MF.getRegInfo();
2284 unsigned CNTB_reg = RegInfo.createVirtualRegister(&SPU::R32CRegClass);
2285 unsigned SUM1_reg = RegInfo.createVirtualRegister(&SPU::R32CRegClass);
2287 SDValue N = Op.getOperand(0);
2288 SDValue Elt0 = DAG.getConstant(0, MVT::i32);
2289 SDValue Mask0 = DAG.getConstant(0xff, MVT::i32);
2290 SDValue Shift1 = DAG.getConstant(16, MVT::i32);
2291 SDValue Shift2 = DAG.getConstant(8, MVT::i32);
2293 SDValue Promote = DAG.getNode(SPUISD::PREFSLOT2VEC, dl, vecVT, N, N);
2294 SDValue CNTB = DAG.getNode(SPUISD::CNTB, dl, vecVT, Promote);
2296 // CNTB_result becomes the chain to which all of the virtual registers
2297 // CNTB_reg, SUM1_reg become associated:
2298 SDValue CNTB_result =
2299 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, CNTB, Elt0);
2301 SDValue CNTB_rescopy =
2302 DAG.getCopyToReg(CNTB_result, dl, CNTB_reg, CNTB_result);
2305 DAG.getNode(ISD::SRL, dl, MVT::i32,
2306 DAG.getCopyFromReg(CNTB_rescopy, dl, CNTB_reg, MVT::i32),
2310 DAG.getNode(ISD::ADD, dl, MVT::i32, Comp1,
2311 DAG.getCopyFromReg(CNTB_rescopy, dl, CNTB_reg, MVT::i32));
2313 SDValue Sum1_rescopy =
2314 DAG.getCopyToReg(CNTB_result, dl, SUM1_reg, Sum1);
2317 DAG.getNode(ISD::SRL, dl, MVT::i32,
2318 DAG.getCopyFromReg(Sum1_rescopy, dl, SUM1_reg, MVT::i32),
2321 DAG.getNode(ISD::ADD, dl, MVT::i32, Comp2,
2322 DAG.getCopyFromReg(Sum1_rescopy, dl, SUM1_reg, MVT::i32));
2324 return DAG.getNode(ISD::AND, dl, MVT::i32, Sum2, Mask0);
2334 //! Lower ISD::FP_TO_SINT, ISD::FP_TO_UINT for i32
2336 f32->i32 passes through unchanged, whereas f64->i32 expands to a libcall.
2337 All conversions to i64 are expanded to a libcall.
2339 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
2340 const SPUTargetLowering &TLI) {
2341 EVT OpVT = Op.getValueType();
2342 SDValue Op0 = Op.getOperand(0);
2343 EVT Op0VT = Op0.getValueType();
2345 if ((OpVT == MVT::i32 && Op0VT == MVT::f64)
2346 || OpVT == MVT::i64) {
2347 // Convert f32 / f64 to i32 / i64 via libcall.
2349 (Op.getOpcode() == ISD::FP_TO_SINT)
2350 ? RTLIB::getFPTOSINT(Op0VT, OpVT)
2351 : RTLIB::getFPTOUINT(Op0VT, OpVT);
2352 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpectd fp-to-int conversion!");
2354 return ExpandLibCall(LC, Op, DAG, false, Dummy, TLI);
2360 //! Lower ISD::SINT_TO_FP, ISD::UINT_TO_FP for i32
2362 i32->f32 passes through unchanged, whereas i32->f64 is expanded to a libcall.
2363 All conversions from i64 are expanded to a libcall.
2365 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG,
2366 const SPUTargetLowering &TLI) {
2367 EVT OpVT = Op.getValueType();
2368 SDValue Op0 = Op.getOperand(0);
2369 EVT Op0VT = Op0.getValueType();
2371 if ((OpVT == MVT::f64 && Op0VT == MVT::i32)
2372 || Op0VT == MVT::i64) {
2373 // Convert i32, i64 to f64 via libcall:
2375 (Op.getOpcode() == ISD::SINT_TO_FP)
2376 ? RTLIB::getSINTTOFP(Op0VT, OpVT)
2377 : RTLIB::getUINTTOFP(Op0VT, OpVT);
2378 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpectd int-to-fp conversion!");
2380 return ExpandLibCall(LC, Op, DAG, false, Dummy, TLI);
2386 //! Lower ISD::SETCC
2388 This handles MVT::f64 (double floating point) condition lowering
2390 static SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG,
2391 const TargetLowering &TLI) {
2392 CondCodeSDNode *CC = dyn_cast<CondCodeSDNode>(Op.getOperand(2));
2393 DebugLoc dl = Op.getDebugLoc();
2394 assert(CC != 0 && "LowerSETCC: CondCodeSDNode should not be null here!\n");
2396 SDValue lhs = Op.getOperand(0);
2397 SDValue rhs = Op.getOperand(1);
2398 EVT lhsVT = lhs.getValueType();
2399 assert(lhsVT == MVT::f64 && "LowerSETCC: type other than MVT::64\n");
2401 EVT ccResultVT = TLI.getSetCCResultType(lhs.getValueType());
2402 APInt ccResultOnes = APInt::getAllOnesValue(ccResultVT.getSizeInBits());
2403 EVT IntVT(MVT::i64);
2405 // Take advantage of the fact that (truncate (sra arg, 32)) is efficiently
2406 // selected to a NOP:
2407 SDValue i64lhs = DAG.getNode(ISD::BIT_CONVERT, dl, IntVT, lhs);
2409 DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
2410 DAG.getNode(ISD::SRL, dl, IntVT,
2411 i64lhs, DAG.getConstant(32, MVT::i32)));
2412 SDValue lhsHi32abs =
2413 DAG.getNode(ISD::AND, dl, MVT::i32,
2414 lhsHi32, DAG.getConstant(0x7fffffff, MVT::i32));
2416 DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, i64lhs);
2418 // SETO and SETUO only use the lhs operand:
2419 if (CC->get() == ISD::SETO) {
2420 // Evaluates to true if Op0 is not [SQ]NaN - lowers to the inverse of
2422 APInt ccResultAllOnes = APInt::getAllOnesValue(ccResultVT.getSizeInBits());
2423 return DAG.getNode(ISD::XOR, dl, ccResultVT,
2424 DAG.getSetCC(dl, ccResultVT,
2425 lhs, DAG.getConstantFP(0.0, lhsVT),
2427 DAG.getConstant(ccResultAllOnes, ccResultVT));
2428 } else if (CC->get() == ISD::SETUO) {
2429 // Evaluates to true if Op0 is [SQ]NaN
2430 return DAG.getNode(ISD::AND, dl, ccResultVT,
2431 DAG.getSetCC(dl, ccResultVT,
2433 DAG.getConstant(0x7ff00000, MVT::i32),
2435 DAG.getSetCC(dl, ccResultVT,
2437 DAG.getConstant(0, MVT::i32),
2441 SDValue i64rhs = DAG.getNode(ISD::BIT_CONVERT, dl, IntVT, rhs);
2443 DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
2444 DAG.getNode(ISD::SRL, dl, IntVT,
2445 i64rhs, DAG.getConstant(32, MVT::i32)));
2447 // If a value is negative, subtract from the sign magnitude constant:
2448 SDValue signMag2TC = DAG.getConstant(0x8000000000000000ULL, IntVT);
2450 // Convert the sign-magnitude representation into 2's complement:
2451 SDValue lhsSelectMask = DAG.getNode(ISD::SRA, dl, ccResultVT,
2452 lhsHi32, DAG.getConstant(31, MVT::i32));
2453 SDValue lhsSignMag2TC = DAG.getNode(ISD::SUB, dl, IntVT, signMag2TC, i64lhs);
2455 DAG.getNode(ISD::SELECT, dl, IntVT,
2456 lhsSelectMask, lhsSignMag2TC, i64lhs);
2458 SDValue rhsSelectMask = DAG.getNode(ISD::SRA, dl, ccResultVT,
2459 rhsHi32, DAG.getConstant(31, MVT::i32));
2460 SDValue rhsSignMag2TC = DAG.getNode(ISD::SUB, dl, IntVT, signMag2TC, i64rhs);
2462 DAG.getNode(ISD::SELECT, dl, IntVT,
2463 rhsSelectMask, rhsSignMag2TC, i64rhs);
2467 switch (CC->get()) {
2470 compareOp = ISD::SETEQ; break;
2473 compareOp = ISD::SETGT; break;
2476 compareOp = ISD::SETGE; break;
2479 compareOp = ISD::SETLT; break;
2482 compareOp = ISD::SETLE; break;
2485 compareOp = ISD::SETNE; break;
2487 report_fatal_error("CellSPU ISel Select: unimplemented f64 condition");
2491 DAG.getSetCC(dl, ccResultVT, lhsSelect, rhsSelect,
2492 (ISD::CondCode) compareOp);
2494 if ((CC->get() & 0x8) == 0) {
2495 // Ordered comparison:
2496 SDValue lhsNaN = DAG.getSetCC(dl, ccResultVT,
2497 lhs, DAG.getConstantFP(0.0, MVT::f64),
2499 SDValue rhsNaN = DAG.getSetCC(dl, ccResultVT,
2500 rhs, DAG.getConstantFP(0.0, MVT::f64),
2502 SDValue ordered = DAG.getNode(ISD::AND, dl, ccResultVT, lhsNaN, rhsNaN);
2504 result = DAG.getNode(ISD::AND, dl, ccResultVT, ordered, result);
2510 //! Lower ISD::SELECT_CC
2512 ISD::SELECT_CC can (generally) be implemented directly on the SPU using the
2515 \note Need to revisit this in the future: if the code path through the true
2516 and false value computations is longer than the latency of a branch (6
2517 cycles), then it would be more advantageous to branch and insert a new basic
2518 block and branch on the condition. However, this code does not make that
2519 assumption, given the simplisitc uses so far.
2522 static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
2523 const TargetLowering &TLI) {
2524 EVT VT = Op.getValueType();
2525 SDValue lhs = Op.getOperand(0);
2526 SDValue rhs = Op.getOperand(1);
2527 SDValue trueval = Op.getOperand(2);
2528 SDValue falseval = Op.getOperand(3);
2529 SDValue condition = Op.getOperand(4);
2530 DebugLoc dl = Op.getDebugLoc();
2532 // NOTE: SELB's arguments: $rA, $rB, $mask
2534 // SELB selects bits from $rA where bits in $mask are 0, bits from $rB
2535 // where bits in $mask are 1. CCond will be inverted, having 1s where the
2536 // condition was true and 0s where the condition was false. Hence, the
2537 // arguments to SELB get reversed.
2539 // Note: Really should be ISD::SELECT instead of SPUISD::SELB, but LLVM's
2540 // legalizer insists on combining SETCC/SELECT into SELECT_CC, so we end up
2541 // with another "cannot select select_cc" assert:
2543 SDValue compare = DAG.getNode(ISD::SETCC, dl,
2544 TLI.getSetCCResultType(Op.getValueType()),
2545 lhs, rhs, condition);
2546 return DAG.getNode(SPUISD::SELB, dl, VT, falseval, trueval, compare);
2549 //! Custom lower ISD::TRUNCATE
2550 static SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG)
2552 // Type to truncate to
2553 EVT VT = Op.getValueType();
2554 MVT simpleVT = VT.getSimpleVT();
2555 EVT VecVT = EVT::getVectorVT(*DAG.getContext(),
2556 VT, (128 / VT.getSizeInBits()));
2557 DebugLoc dl = Op.getDebugLoc();
2559 // Type to truncate from
2560 SDValue Op0 = Op.getOperand(0);
2561 EVT Op0VT = Op0.getValueType();
2563 if (Op0VT.getSimpleVT() == MVT::i128 && simpleVT == MVT::i64) {
2564 // Create shuffle mask, least significant doubleword of quadword
2565 unsigned maskHigh = 0x08090a0b;
2566 unsigned maskLow = 0x0c0d0e0f;
2567 // Use a shuffle to perform the truncation
2568 SDValue shufMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
2569 DAG.getConstant(maskHigh, MVT::i32),
2570 DAG.getConstant(maskLow, MVT::i32),
2571 DAG.getConstant(maskHigh, MVT::i32),
2572 DAG.getConstant(maskLow, MVT::i32));
2574 SDValue truncShuffle = DAG.getNode(SPUISD::SHUFB, dl, VecVT,
2575 Op0, Op0, shufMask);
2577 return DAG.getNode(SPUISD::VEC2PREFSLOT, dl, VT, truncShuffle);
2580 return SDValue(); // Leave the truncate unmolested
2584 * Emit the instruction sequence for i64/i32 -> i128 sign extend. The basic
2585 * algorithm is to duplicate the sign bit using rotmai to generate at
2586 * least one byte full of sign bits. Then propagate the "sign-byte" into
2587 * the leftmost words and the i64/i32 into the rightmost words using shufb.
2589 * @param Op The sext operand
2590 * @param DAG The current DAG
2591 * @return The SDValue with the entire instruction sequence
2593 static SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG)
2595 DebugLoc dl = Op.getDebugLoc();
2597 // Type to extend to
2598 MVT OpVT = Op.getValueType().getSimpleVT();
2600 // Type to extend from
2601 SDValue Op0 = Op.getOperand(0);
2602 MVT Op0VT = Op0.getValueType().getSimpleVT();
2604 // The type to extend to needs to be a i128 and
2605 // the type to extend from needs to be i64 or i32.
2606 assert((OpVT == MVT::i128 && (Op0VT == MVT::i64 || Op0VT == MVT::i32)) &&
2607 "LowerSIGN_EXTEND: input and/or output operand have wrong size");
2609 // Create shuffle mask
2610 unsigned mask1 = 0x10101010; // byte 0 - 3 and 4 - 7
2611 unsigned mask2 = Op0VT == MVT::i64 ? 0x00010203 : 0x10101010; // byte 8 - 11
2612 unsigned mask3 = Op0VT == MVT::i64 ? 0x04050607 : 0x00010203; // byte 12 - 15
2613 SDValue shufMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
2614 DAG.getConstant(mask1, MVT::i32),
2615 DAG.getConstant(mask1, MVT::i32),
2616 DAG.getConstant(mask2, MVT::i32),
2617 DAG.getConstant(mask3, MVT::i32));
2619 // Word wise arithmetic right shift to generate at least one byte
2620 // that contains sign bits.
2621 MVT mvt = Op0VT == MVT::i64 ? MVT::v2i64 : MVT::v4i32;
2622 SDValue sraVal = DAG.getNode(ISD::SRA,
2625 DAG.getNode(SPUISD::PREFSLOT2VEC, dl, mvt, Op0, Op0),
2626 DAG.getConstant(31, MVT::i32));
2628 // Shuffle bytes - Copy the sign bits into the upper 64 bits
2629 // and the input value into the lower 64 bits.
2630 SDValue extShuffle = DAG.getNode(SPUISD::SHUFB, dl, mvt,
2631 DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i128, Op0), sraVal, shufMask);
2633 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i128, extShuffle);
2636 //! Custom (target-specific) lowering entry point
2638 This is where LLVM's DAG selection process calls to do target-specific
2642 SPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
2644 unsigned Opc = (unsigned) Op.getOpcode();
2645 EVT VT = Op.getValueType();
2650 errs() << "SPUTargetLowering::LowerOperation(): need to lower this!\n";
2651 errs() << "Op.getOpcode() = " << Opc << "\n";
2652 errs() << "*Op.getNode():\n";
2653 Op.getNode()->dump();
2655 llvm_unreachable(0);
2661 return LowerLOAD(Op, DAG, SPUTM.getSubtargetImpl());
2663 return LowerSTORE(Op, DAG, SPUTM.getSubtargetImpl());
2664 case ISD::ConstantPool:
2665 return LowerConstantPool(Op, DAG, SPUTM.getSubtargetImpl());
2666 case ISD::GlobalAddress:
2667 return LowerGlobalAddress(Op, DAG, SPUTM.getSubtargetImpl());
2668 case ISD::JumpTable:
2669 return LowerJumpTable(Op, DAG, SPUTM.getSubtargetImpl());
2670 case ISD::ConstantFP:
2671 return LowerConstantFP(Op, DAG);
2673 // i8, i64 math ops:
2682 return LowerI8Math(Op, DAG, Opc, *this);
2686 case ISD::FP_TO_SINT:
2687 case ISD::FP_TO_UINT:
2688 return LowerFP_TO_INT(Op, DAG, *this);
2690 case ISD::SINT_TO_FP:
2691 case ISD::UINT_TO_FP:
2692 return LowerINT_TO_FP(Op, DAG, *this);
2694 // Vector-related lowering.
2695 case ISD::BUILD_VECTOR:
2696 return LowerBUILD_VECTOR(Op, DAG);
2697 case ISD::SCALAR_TO_VECTOR:
2698 return LowerSCALAR_TO_VECTOR(Op, DAG);
2699 case ISD::VECTOR_SHUFFLE:
2700 return LowerVECTOR_SHUFFLE(Op, DAG);
2701 case ISD::EXTRACT_VECTOR_ELT:
2702 return LowerEXTRACT_VECTOR_ELT(Op, DAG);
2703 case ISD::INSERT_VECTOR_ELT:
2704 return LowerINSERT_VECTOR_ELT(Op, DAG);
2706 // Look for ANDBI, ORBI and XORBI opportunities and lower appropriately:
2710 return LowerByteImmed(Op, DAG);
2712 // Vector and i8 multiply:
2715 return LowerI8Math(Op, DAG, Opc, *this);
2718 return LowerCTPOP(Op, DAG);
2720 case ISD::SELECT_CC:
2721 return LowerSELECT_CC(Op, DAG, *this);
2724 return LowerSETCC(Op, DAG, *this);
2727 return LowerTRUNCATE(Op, DAG);
2729 case ISD::SIGN_EXTEND:
2730 return LowerSIGN_EXTEND(Op, DAG);
2736 void SPUTargetLowering::ReplaceNodeResults(SDNode *N,
2737 SmallVectorImpl<SDValue>&Results,
2738 SelectionDAG &DAG) const
2741 unsigned Opc = (unsigned) N->getOpcode();
2742 EVT OpVT = N->getValueType(0);
2746 errs() << "SPUTargetLowering::ReplaceNodeResults(): need to fix this!\n";
2747 errs() << "Op.getOpcode() = " << Opc << "\n";
2748 errs() << "*Op.getNode():\n";
2756 /* Otherwise, return unchanged */
2759 //===----------------------------------------------------------------------===//
2760 // Target Optimization Hooks
2761 //===----------------------------------------------------------------------===//
2764 SPUTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const
2767 TargetMachine &TM = getTargetMachine();
2769 const SPUSubtarget *ST = SPUTM.getSubtargetImpl();
2770 SelectionDAG &DAG = DCI.DAG;
2771 SDValue Op0 = N->getOperand(0); // everything has at least one operand
2772 EVT NodeVT = N->getValueType(0); // The node's value type
2773 EVT Op0VT = Op0.getValueType(); // The first operand's result
2774 SDValue Result; // Initially, empty result
2775 DebugLoc dl = N->getDebugLoc();
2777 switch (N->getOpcode()) {
2780 SDValue Op1 = N->getOperand(1);
2782 if (Op0.getOpcode() == SPUISD::IndirectAddr
2783 || Op1.getOpcode() == SPUISD::IndirectAddr) {
2784 // Normalize the operands to reduce repeated code
2785 SDValue IndirectArg = Op0, AddArg = Op1;
2787 if (Op1.getOpcode() == SPUISD::IndirectAddr) {
2792 if (isa<ConstantSDNode>(AddArg)) {
2793 ConstantSDNode *CN0 = cast<ConstantSDNode > (AddArg);
2794 SDValue IndOp1 = IndirectArg.getOperand(1);
2796 if (CN0->isNullValue()) {
2797 // (add (SPUindirect <arg>, <arg>), 0) ->
2798 // (SPUindirect <arg>, <arg>)
2800 #if !defined(NDEBUG)
2801 if (DebugFlag && isCurrentDebugType(DEBUG_TYPE)) {
2803 << "Replace: (add (SPUindirect <arg>, <arg>), 0)\n"
2804 << "With: (SPUindirect <arg>, <arg>)\n";
2809 } else if (isa<ConstantSDNode>(IndOp1)) {
2810 // (add (SPUindirect <arg>, <const>), <const>) ->
2811 // (SPUindirect <arg>, <const + const>)
2812 ConstantSDNode *CN1 = cast<ConstantSDNode > (IndOp1);
2813 int64_t combinedConst = CN0->getSExtValue() + CN1->getSExtValue();
2814 SDValue combinedValue = DAG.getConstant(combinedConst, Op0VT);
2816 #if !defined(NDEBUG)
2817 if (DebugFlag && isCurrentDebugType(DEBUG_TYPE)) {
2819 << "Replace: (add (SPUindirect <arg>, " << CN1->getSExtValue()
2820 << "), " << CN0->getSExtValue() << ")\n"
2821 << "With: (SPUindirect <arg>, "
2822 << combinedConst << ")\n";
2826 return DAG.getNode(SPUISD::IndirectAddr, dl, Op0VT,
2827 IndirectArg, combinedValue);
2833 case ISD::SIGN_EXTEND:
2834 case ISD::ZERO_EXTEND:
2835 case ISD::ANY_EXTEND: {
2836 if (Op0.getOpcode() == SPUISD::VEC2PREFSLOT && NodeVT == Op0VT) {
2837 // (any_extend (SPUextract_elt0 <arg>)) ->
2838 // (SPUextract_elt0 <arg>)
2839 // Types must match, however...
2840 #if !defined(NDEBUG)
2841 if (DebugFlag && isCurrentDebugType(DEBUG_TYPE)) {
2842 errs() << "\nReplace: ";
2844 errs() << "\nWith: ";
2845 Op0.getNode()->dump(&DAG);
2854 case SPUISD::IndirectAddr: {
2855 if (!ST->usingLargeMem() && Op0.getOpcode() == SPUISD::AFormAddr) {
2856 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1));
2857 if (CN != 0 && CN->isNullValue()) {
2858 // (SPUindirect (SPUaform <addr>, 0), 0) ->
2859 // (SPUaform <addr>, 0)
2861 DEBUG(errs() << "Replace: ");
2862 DEBUG(N->dump(&DAG));
2863 DEBUG(errs() << "\nWith: ");
2864 DEBUG(Op0.getNode()->dump(&DAG));
2865 DEBUG(errs() << "\n");
2869 } else if (Op0.getOpcode() == ISD::ADD) {
2870 SDValue Op1 = N->getOperand(1);
2871 if (ConstantSDNode *CN1 = dyn_cast<ConstantSDNode>(Op1)) {
2872 // (SPUindirect (add <arg>, <arg>), 0) ->
2873 // (SPUindirect <arg>, <arg>)
2874 if (CN1->isNullValue()) {
2876 #if !defined(NDEBUG)
2877 if (DebugFlag && isCurrentDebugType(DEBUG_TYPE)) {
2879 << "Replace: (SPUindirect (add <arg>, <arg>), 0)\n"
2880 << "With: (SPUindirect <arg>, <arg>)\n";
2884 return DAG.getNode(SPUISD::IndirectAddr, dl, Op0VT,
2885 Op0.getOperand(0), Op0.getOperand(1));
2891 case SPUISD::SHLQUAD_L_BITS:
2892 case SPUISD::SHLQUAD_L_BYTES:
2893 case SPUISD::ROTBYTES_LEFT: {
2894 SDValue Op1 = N->getOperand(1);
2896 // Kill degenerate vector shifts:
2897 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op1)) {
2898 if (CN->isNullValue()) {
2904 case SPUISD::PREFSLOT2VEC: {
2905 switch (Op0.getOpcode()) {
2908 case ISD::ANY_EXTEND:
2909 case ISD::ZERO_EXTEND:
2910 case ISD::SIGN_EXTEND: {
2911 // (SPUprefslot2vec (any|zero|sign_extend (SPUvec2prefslot <arg>))) ->
2913 // but only if the SPUprefslot2vec and <arg> types match.
2914 SDValue Op00 = Op0.getOperand(0);
2915 if (Op00.getOpcode() == SPUISD::VEC2PREFSLOT) {
2916 SDValue Op000 = Op00.getOperand(0);
2917 if (Op000.getValueType() == NodeVT) {
2923 case SPUISD::VEC2PREFSLOT: {
2924 // (SPUprefslot2vec (SPUvec2prefslot <arg>)) ->
2926 Result = Op0.getOperand(0);
2934 // Otherwise, return unchanged.
2936 if (Result.getNode()) {
2937 DEBUG(errs() << "\nReplace.SPU: ");
2938 DEBUG(N->dump(&DAG));
2939 DEBUG(errs() << "\nWith: ");
2940 DEBUG(Result.getNode()->dump(&DAG));
2941 DEBUG(errs() << "\n");
2948 //===----------------------------------------------------------------------===//
2949 // Inline Assembly Support
2950 //===----------------------------------------------------------------------===//
2952 /// getConstraintType - Given a constraint letter, return the type of
2953 /// constraint it is for this target.
2954 SPUTargetLowering::ConstraintType
2955 SPUTargetLowering::getConstraintType(const std::string &ConstraintLetter) const {
2956 if (ConstraintLetter.size() == 1) {
2957 switch (ConstraintLetter[0]) {
2964 return C_RegisterClass;
2967 return TargetLowering::getConstraintType(ConstraintLetter);
2970 std::pair<unsigned, const TargetRegisterClass*>
2971 SPUTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
2974 if (Constraint.size() == 1) {
2975 // GCC RS6000 Constraint Letters
2976 switch (Constraint[0]) {
2980 return std::make_pair(0U, SPU::R64CRegisterClass);
2981 return std::make_pair(0U, SPU::R32CRegisterClass);
2984 return std::make_pair(0U, SPU::R32FPRegisterClass);
2985 else if (VT == MVT::f64)
2986 return std::make_pair(0U, SPU::R64FPRegisterClass);
2989 return std::make_pair(0U, SPU::GPRCRegisterClass);
2993 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
2996 //! Compute used/known bits for a SPU operand
2998 SPUTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
3002 const SelectionDAG &DAG,
3003 unsigned Depth ) const {
3005 const uint64_t uint64_sizebits = sizeof(uint64_t) * CHAR_BIT;
3007 switch (Op.getOpcode()) {
3009 // KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
3015 case SPUISD::PREFSLOT2VEC:
3016 case SPUISD::LDRESULT:
3017 case SPUISD::VEC2PREFSLOT:
3018 case SPUISD::SHLQUAD_L_BITS:
3019 case SPUISD::SHLQUAD_L_BYTES:
3020 case SPUISD::VEC_ROTL:
3021 case SPUISD::VEC_ROTR:
3022 case SPUISD::ROTBYTES_LEFT:
3023 case SPUISD::SELECT_MASK:
3030 SPUTargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
3031 unsigned Depth) const {
3032 switch (Op.getOpcode()) {
3037 EVT VT = Op.getValueType();
3039 if (VT != MVT::i8 && VT != MVT::i16 && VT != MVT::i32) {
3042 return VT.getSizeInBits();
3047 // LowerAsmOperandForConstraint
3049 SPUTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
3050 char ConstraintLetter,
3051 std::vector<SDValue> &Ops,
3052 SelectionDAG &DAG) const {
3053 // Default, for the time being, to the base class handler
3054 TargetLowering::LowerAsmOperandForConstraint(Op, ConstraintLetter, Ops, DAG);
3057 /// isLegalAddressImmediate - Return true if the integer value can be used
3058 /// as the offset of the target addressing mode.
3059 bool SPUTargetLowering::isLegalAddressImmediate(int64_t V,
3060 const Type *Ty) const {
3061 // SPU's addresses are 256K:
3062 return (V > -(1 << 18) && V < (1 << 18) - 1);
3065 bool SPUTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const {
3070 SPUTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
3071 // The SPU target isn't yet aware of offsets.