1 //===- SPUCallingConv.td - Calling Conventions for CellSPU ------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by a team from the Computer Systems Research
6 // Department at The Aerospace Corporation and is distributed under the
7 // University of Illinois Open Source License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 // This describes the calling conventions for the STI Cell SPU architecture.
13 //===----------------------------------------------------------------------===//
15 /// CCIfSubtarget - Match if the current subtarget has a feature F.
16 class CCIfSubtarget<string F, CCAction A>
17 : CCIf<!strconcat("State.getTarget().getSubtarget<PPCSubtarget>().", F), A>;
19 //===----------------------------------------------------------------------===//
20 // Return Value Calling Convention
21 //===----------------------------------------------------------------------===//
23 // Return-value convention for Cell SPU: Everything can be passed back via $3:
24 def RetCC_SPU : CallingConv<[
25 CCIfType<[i32], CCAssignToReg<[R3]>>,
26 CCIfType<[i64], CCAssignToReg<[R3]>>,
27 CCIfType<[f32, f64], CCAssignToReg<[R3]>>,
28 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToReg<[R3]>>
32 //===----------------------------------------------------------------------===//
33 // CellSPU Argument Calling Conventions
35 //===----------------------------------------------------------------------===//
37 def CC_SPU : CallingConv<[
38 // The first 8 integer arguments are passed in integer registers.
39 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
40 CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6, X7, X8, X9, X10]>>,
42 // SPU can pass back arguments in all
43 CCIfType<[f32, f64], CCIfSubtarget<"isMachoABI()",
44 CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8,F9,F10,F11,F12,F13]>>>,
45 // Other sub-targets pass FP values in F1-10.
46 CCIfType<[f32, f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8, F9,F10]>>,
48 // The first 12 Vector arguments are passed in altivec registers.
49 CCIfType<[v16i8, v8i16, v4i32, v4f32],
50 CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9, V10,V11,V12,V13]>>
53 // Integer/FP values get stored in stack slots that are 8 bytes in size and
54 // 8-byte aligned if there are no more registers to hold them.
55 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
57 // Vectors get 16-byte stack slots that are 16-byte aligned.
58 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
59 CCAssignToStack<16, 16>>