1 //===-- SPUAsmPrinter.cpp - Print machine instrs to Cell SPU assembly -------=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to Cell SPU assembly language. This printer
12 // is the output mechanism used by `llc'.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "asmprinter"
18 #include "SPUTargetMachine.h"
19 #include "llvm/Constants.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/Module.h"
22 #include "llvm/CodeGen/AsmPrinter.h"
23 #include "llvm/CodeGen/MachineModuleInfo.h"
24 #include "llvm/MC/MCStreamer.h"
25 #include "llvm/MC/MCAsmInfo.h"
26 #include "llvm/MC/MCSymbol.h"
27 #include "llvm/Target/Mangler.h"
28 #include "llvm/Target/TargetLoweringObjectFile.h"
29 #include "llvm/Target/TargetInstrInfo.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/Target/TargetRegisterInfo.h"
32 #include "llvm/Target/TargetRegistry.h"
33 #include "llvm/ADT/StringExtras.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/FormattedStream.h"
39 class SPUAsmPrinter : public AsmPrinter {
41 explicit SPUAsmPrinter(formatted_raw_ostream &O, TargetMachine &TM,
42 MCStreamer &Streamer) :
43 AsmPrinter(O, TM, Streamer) {}
45 virtual const char *getPassName() const {
46 return "STI CBEA SPU Assembly Printer";
49 SPUTargetMachine &getTM() {
50 return static_cast<SPUTargetMachine&>(TM);
53 /// printInstruction - This method is automatically generated by tablegen
54 /// from the instruction set description.
55 void printInstruction(const MachineInstr *MI, raw_ostream &OS);
56 static const char *getRegisterName(unsigned RegNo);
59 void EmitInstruction(const MachineInstr *MI) {
60 printInstruction(MI, O);
61 OutStreamer.AddBlankLine();
63 void printOp(const MachineOperand &MO, raw_ostream &OS);
65 /// printRegister - Print register according to target requirements.
67 void printRegister(const MachineOperand &MO, bool R0AsZero, raw_ostream &O){
68 unsigned RegNo = MO.getReg();
69 assert(TargetRegisterInfo::isPhysicalRegister(RegNo) &&
71 O << getRegisterName(RegNo);
74 void printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) {
75 const MachineOperand &MO = MI->getOperand(OpNo);
77 O << getRegisterName(MO.getReg());
78 } else if (MO.isImm()) {
85 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
86 unsigned AsmVariant, const char *ExtraCode);
87 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
88 unsigned AsmVariant, const char *ExtraCode);
92 printS7ImmOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O)
94 int value = MI->getOperand(OpNo).getImm();
95 value = (value << (32 - 7)) >> (32 - 7);
97 assert((value >= -(1 << 8) && value <= (1 << 7) - 1)
98 && "Invalid s7 argument");
103 printU7ImmOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O)
105 unsigned int value = MI->getOperand(OpNo).getImm();
106 assert(value < (1 << 8) && "Invalid u7 argument");
111 printShufAddr(const MachineInstr *MI, unsigned OpNo, raw_ostream &O)
113 char value = MI->getOperand(OpNo).getImm();
116 printOperand(MI, OpNo+1, O);
121 printS16ImmOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O)
123 O << (short) MI->getOperand(OpNo).getImm();
127 printU16ImmOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O)
129 O << (unsigned short)MI->getOperand(OpNo).getImm();
133 printU32ImmOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O)
135 O << (unsigned)MI->getOperand(OpNo).getImm();
139 printMemRegReg(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) {
140 // When used as the base register, r0 reads constant zero rather than
141 // the value contained in the register. For this reason, the darwin
142 // assembler requires that we print r0 as 0 (no r) when used as the base.
143 const MachineOperand &MO = MI->getOperand(OpNo);
144 O << getRegisterName(MO.getReg()) << ", ";
145 printOperand(MI, OpNo+1, O);
149 printU18ImmOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O)
151 unsigned int value = MI->getOperand(OpNo).getImm();
152 assert(value <= (1 << 19) - 1 && "Invalid u18 argument");
157 printS10ImmOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O)
159 short value = (short) (((int) MI->getOperand(OpNo).getImm() << 16)
161 assert((value >= -(1 << 9) && value <= (1 << 9) - 1)
162 && "Invalid s10 argument");
167 printU10ImmOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O)
169 short value = (short) (((int) MI->getOperand(OpNo).getImm() << 16)
171 assert((value <= (1 << 10) - 1) && "Invalid u10 argument");
176 printDFormAddr(const MachineInstr *MI, unsigned OpNo, raw_ostream &O)
178 assert(MI->getOperand(OpNo).isImm() &&
179 "printDFormAddr first operand is not immediate");
180 int64_t value = int64_t(MI->getOperand(OpNo).getImm());
181 int16_t value16 = int16_t(value);
182 assert((value16 >= -(1 << (9+4)) && value16 <= (1 << (9+4)) - 1)
183 && "Invalid dform s10 offset argument");
184 O << (value16 & ~0xf) << "(";
185 printOperand(MI, OpNo+1, O);
190 printAddr256K(const MachineInstr *MI, unsigned OpNo, raw_ostream &O)
192 /* Note: operand 1 is an offset or symbol name. */
193 if (MI->getOperand(OpNo).isImm()) {
194 printS16ImmOperand(MI, OpNo, O);
196 printOp(MI->getOperand(OpNo), O);
197 if (MI->getOperand(OpNo+1).isImm()) {
198 int displ = int(MI->getOperand(OpNo+1).getImm());
207 void printCallOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) {
208 printOp(MI->getOperand(OpNo), O);
211 void printPCRelativeOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) {
212 // Used to generate a ".-<target>", but it turns out that the assembler
213 // really wants the target.
215 // N.B.: This operand is used for call targets. Branch hints are another
217 printOp(MI->getOperand(OpNo), O);
220 void printHBROperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) {
221 // HBR operands are generated in front of branches, hence, the
222 // program counter plus the target.
224 printOp(MI->getOperand(OpNo), O);
227 void printSymbolHi(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) {
228 if (MI->getOperand(OpNo).isImm()) {
229 printS16ImmOperand(MI, OpNo, O);
231 printOp(MI->getOperand(OpNo), O);
236 void printSymbolLo(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) {
237 if (MI->getOperand(OpNo).isImm()) {
238 printS16ImmOperand(MI, OpNo, O);
240 printOp(MI->getOperand(OpNo), O);
245 /// Print local store address
246 void printSymbolLSA(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) {
247 printOp(MI->getOperand(OpNo), O);
250 void printROTHNeg7Imm(const MachineInstr *MI, unsigned OpNo,
252 if (MI->getOperand(OpNo).isImm()) {
253 int value = (int) MI->getOperand(OpNo).getImm();
254 assert((value >= 0 && value < 16)
255 && "Invalid negated immediate rotate 7-bit argument");
258 llvm_unreachable("Invalid/non-immediate rotate amount in printRotateNeg7Imm");
262 void printROTNeg7Imm(const MachineInstr *MI, unsigned OpNo, raw_ostream &O){
263 assert(MI->getOperand(OpNo).isImm() &&
264 "Invalid/non-immediate rotate amount in printRotateNeg7Imm");
265 int value = (int) MI->getOperand(OpNo).getImm();
266 assert((value >= 0 && value <= 32)
267 && "Invalid negated immediate rotate 7-bit argument");
271 } // end of anonymous namespace
273 // Include the auto-generated portion of the assembly writer
274 #include "SPUGenAsmWriter.inc"
276 void SPUAsmPrinter::printOp(const MachineOperand &MO, raw_ostream &O) {
277 switch (MO.getType()) {
278 case MachineOperand::MO_Immediate:
279 llvm_report_error("printOp() does not handle immediate values");
282 case MachineOperand::MO_MachineBasicBlock:
283 O << *MO.getMBB()->getSymbol();
285 case MachineOperand::MO_JumpTableIndex:
286 O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
287 << '_' << MO.getIndex();
289 case MachineOperand::MO_ConstantPoolIndex:
290 O << MAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber()
291 << '_' << MO.getIndex();
293 case MachineOperand::MO_ExternalSymbol:
294 // Computing the address of an external symbol, not calling it.
295 if (TM.getRelocationModel() != Reloc::Static) {
296 O << "L" << MAI->getGlobalPrefix() << MO.getSymbolName()
300 O << *GetExternalSymbolSymbol(MO.getSymbolName());
302 case MachineOperand::MO_GlobalAddress:
303 // External or weakly linked global variables need non-lazily-resolved
305 if (TM.getRelocationModel() != Reloc::Static) {
306 GlobalValue *GV = MO.getGlobal();
307 if (((GV->isDeclaration() || GV->hasWeakLinkage() ||
308 GV->hasLinkOnceLinkage() || GV->hasCommonLinkage()))) {
309 O << *GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
313 O << *Mang->getSymbol(MO.getGlobal());
316 O << "<unknown operand type: " << MO.getType() << ">";
321 /// PrintAsmOperand - Print out an operand for an inline asm expression.
323 bool SPUAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
325 const char *ExtraCode) {
326 // Does this asm operand have a single letter operand modifier?
327 if (ExtraCode && ExtraCode[0]) {
328 if (ExtraCode[1] != 0) return true; // Unknown modifier.
330 switch (ExtraCode[0]) {
331 default: return true; // Unknown modifier.
332 case 'L': // Write second word of DImode reference.
333 // Verify that this operand has two consecutive registers.
334 if (!MI->getOperand(OpNo).isReg() ||
335 OpNo+1 == MI->getNumOperands() ||
336 !MI->getOperand(OpNo+1).isReg())
338 ++OpNo; // Return the high-part.
343 printOperand(MI, OpNo, O);
347 bool SPUAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
350 const char *ExtraCode) {
351 if (ExtraCode && ExtraCode[0])
352 return true; // Unknown modifier.
353 printMemRegReg(MI, OpNo, O);
357 // Force static initialization.
358 extern "C" void LLVMInitializeCellSPUAsmPrinter() {
359 RegisterAsmPrinter<SPUAsmPrinter> X(TheCellSPUTarget);