1 //===- AlphaRegisterInfo.cpp - Alpha Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Alpha implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "reginfo"
16 #include "AlphaRegisterInfo.h"
17 #include "llvm/Constants.h"
18 #include "llvm/Type.h"
19 #include "llvm/Function.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineLocation.h"
25 #include "llvm/Target/TargetFrameLowering.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include "llvm/Target/TargetOptions.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/raw_ostream.h"
33 #include "llvm/ADT/BitVector.h"
34 #include "llvm/ADT/STLExtras.h"
38 AlphaRegisterInfo::AlphaRegisterInfo(const TargetInstrInfo &tii)
39 : AlphaGenRegisterInfo(Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP),
43 static long getUpper16(long l) {
44 long y = l / Alpha::IMM_MULT;
45 if (l % Alpha::IMM_MULT > Alpha::IMM_HIGH)
50 static long getLower16(long l) {
51 long h = getUpper16(l);
52 return l - h * Alpha::IMM_MULT;
55 const unsigned* AlphaRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
57 static const unsigned CalleeSavedRegs[] = {
58 Alpha::R9, Alpha::R10,
59 Alpha::R11, Alpha::R12,
60 Alpha::R13, Alpha::R14,
64 Alpha::F8, Alpha::F9, 0
66 return CalleeSavedRegs;
69 BitVector AlphaRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
70 BitVector Reserved(getNumRegs());
71 Reserved.set(Alpha::R15);
72 Reserved.set(Alpha::R29);
73 Reserved.set(Alpha::R30);
74 Reserved.set(Alpha::R31);
78 //===----------------------------------------------------------------------===//
79 // Stack Frame Processing methods
80 //===----------------------------------------------------------------------===//
82 void AlphaRegisterInfo::
83 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
84 MachineBasicBlock::iterator I) const {
85 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
88 // If we have a frame pointer, turn the adjcallstackup instruction into a
89 // 'sub ESP, <amt>' and the adjcallstackdown instruction into 'add ESP,
91 MachineInstr *Old = I;
92 uint64_t Amount = Old->getOperand(0).getImm();
94 // We need to keep the stack aligned properly. To do this, we round the
95 // amount of space needed for the outgoing arguments up to the next
96 // alignment boundary.
97 unsigned Align = TFI->getStackAlignment();
98 Amount = (Amount+Align-1)/Align*Align;
101 if (Old->getOpcode() == Alpha::ADJUSTSTACKDOWN) {
102 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Alpha::LDA), Alpha::R30)
103 .addImm(-Amount).addReg(Alpha::R30);
105 assert(Old->getOpcode() == Alpha::ADJUSTSTACKUP);
106 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Alpha::LDA), Alpha::R30)
107 .addImm(Amount).addReg(Alpha::R30);
110 // Replace the pseudo instruction with a new instruction...
118 //Alpha has a slightly funny stack:
121 //fixed locals (and spills, callee saved, etc)
127 AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
128 int SPAdj, RegScavenger *RS) const {
129 assert(SPAdj == 0 && "Unexpected");
132 MachineInstr &MI = *II;
133 MachineBasicBlock &MBB = *MI.getParent();
134 MachineFunction &MF = *MBB.getParent();
135 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
137 bool FP = TFI->hasFP(MF);
139 while (!MI.getOperand(i).isFI()) {
141 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
144 int FrameIndex = MI.getOperand(i).getIndex();
146 // Add the base register of R30 (SP) or R15 (FP).
147 MI.getOperand(i + 1).ChangeToRegister(FP ? Alpha::R15 : Alpha::R30, false);
149 // Now add the frame object offset to the offset from the virtual frame index.
150 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
152 DEBUG(errs() << "FI: " << FrameIndex << " Offset: " << Offset << "\n");
154 Offset += MF.getFrameInfo()->getStackSize();
156 DEBUG(errs() << "Corrected Offset " << Offset
157 << " for stack size: " << MF.getFrameInfo()->getStackSize() << "\n");
159 if (Offset > Alpha::IMM_HIGH || Offset < Alpha::IMM_LOW) {
160 DEBUG(errs() << "Unconditionally using R28 for evil purposes Offset: "
162 //so in this case, we need to use a temporary register, and move the
163 //original inst off the SP/FP
165 MI.getOperand(i + 1).ChangeToRegister(Alpha::R28, false);
166 MI.getOperand(i).ChangeToImmediate(getLower16(Offset));
168 MachineInstr* nMI=BuildMI(MF, MI.getDebugLoc(),
169 TII.get(Alpha::LDAH), Alpha::R28)
170 .addImm(getUpper16(Offset)).addReg(FP ? Alpha::R15 : Alpha::R30);
173 MI.getOperand(i).ChangeToImmediate(Offset);
177 unsigned AlphaRegisterInfo::getRARegister() const {
181 unsigned AlphaRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
182 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
184 return TFI->hasFP(MF) ? Alpha::R15 : Alpha::R30;
187 unsigned AlphaRegisterInfo::getEHExceptionRegister() const {
188 llvm_unreachable("What is the exception register");
192 unsigned AlphaRegisterInfo::getEHHandlerRegister() const {
193 llvm_unreachable("What is the exception handler register");
197 int AlphaRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
198 llvm_unreachable("What is the dwarf register number");
202 int AlphaRegisterInfo::getLLVMRegNum(unsigned DwarfRegNum, bool isEH) const {
203 llvm_unreachable("What is the dwarf register number");
207 #include "AlphaGenRegisterInfo.inc"
209 std::string AlphaRegisterInfo::getPrettyName(unsigned reg)
211 std::string s(RegisterDescriptors[reg].Name);