1 //===-- AlphaISelLowering.cpp - Alpha DAG Lowering Implementation ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AlphaISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "AlphaISelLowering.h"
15 #include "AlphaTargetMachine.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Module.h"
25 #include "llvm/Support/CommandLine.h"
28 /// AddLiveIn - This helper function adds the specified physical register to the
29 /// MachineFunction as a live in value. It also creates a corresponding virtual
31 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
32 TargetRegisterClass *RC) {
33 assert(RC->contains(PReg) && "Not the correct regclass!");
34 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
35 MF.getRegInfo().addLiveIn(PReg, VReg);
39 AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM) {
40 // Set up the TargetLowering object.
41 //I am having problems with shr n ubyte 1
42 setShiftAmountType(MVT::i64);
43 setSetCCResultType(MVT::i64);
44 setSetCCResultContents(ZeroOrOneSetCCResult);
46 setUsesGlobalOffsetTable(true);
48 addRegisterClass(MVT::i64, Alpha::GPRCRegisterClass);
49 addRegisterClass(MVT::f64, Alpha::F8RCRegisterClass);
50 addRegisterClass(MVT::f32, Alpha::F4RCRegisterClass);
52 setLoadXAction(ISD::EXTLOAD, MVT::i1, Promote);
53 setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand);
55 setLoadXAction(ISD::ZEXTLOAD, MVT::i1, Promote);
56 setLoadXAction(ISD::ZEXTLOAD, MVT::i32, Expand);
58 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
59 setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand);
60 setLoadXAction(ISD::SEXTLOAD, MVT::i16, Expand);
62 // setOperationAction(ISD::BRIND, MVT::Other, Expand);
63 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
64 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
65 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
67 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
69 setOperationAction(ISD::FREM, MVT::f32, Expand);
70 setOperationAction(ISD::FREM, MVT::f64, Expand);
72 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
73 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
74 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
75 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
77 if (!TM.getSubtarget<AlphaSubtarget>().hasCT()) {
78 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
79 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
80 setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
82 setOperationAction(ISD::BSWAP , MVT::i64, Expand);
83 setOperationAction(ISD::ROTL , MVT::i64, Expand);
84 setOperationAction(ISD::ROTR , MVT::i64, Expand);
86 setOperationAction(ISD::SREM , MVT::i64, Custom);
87 setOperationAction(ISD::UREM , MVT::i64, Custom);
88 setOperationAction(ISD::SDIV , MVT::i64, Custom);
89 setOperationAction(ISD::UDIV , MVT::i64, Custom);
91 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
92 setOperationAction(ISD::MEMSET , MVT::Other, Expand);
93 setOperationAction(ISD::MEMCPY , MVT::Other, Expand);
95 // We don't support sin/cos/sqrt/pow
96 setOperationAction(ISD::FSIN , MVT::f64, Expand);
97 setOperationAction(ISD::FCOS , MVT::f64, Expand);
98 setOperationAction(ISD::FSIN , MVT::f32, Expand);
99 setOperationAction(ISD::FCOS , MVT::f32, Expand);
101 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
102 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
104 setOperationAction(ISD::FPOW , MVT::f32, Expand);
105 setOperationAction(ISD::FPOW , MVT::f64, Expand);
107 setOperationAction(ISD::SETCC, MVT::f32, Promote);
109 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Promote);
111 // We don't have line number support yet.
112 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
113 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
114 setOperationAction(ISD::LABEL, MVT::Other, Expand);
116 // Not implemented yet.
117 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
118 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
119 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
121 // We want to legalize GlobalAddress and ConstantPool and
122 // ExternalSymbols nodes into the appropriate instructions to
123 // materialize the address.
124 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
125 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
126 setOperationAction(ISD::ExternalSymbol, MVT::i64, Custom);
127 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
129 setOperationAction(ISD::VASTART, MVT::Other, Custom);
130 setOperationAction(ISD::VAEND, MVT::Other, Expand);
131 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
132 setOperationAction(ISD::VAARG, MVT::Other, Custom);
133 setOperationAction(ISD::VAARG, MVT::i32, Custom);
135 setOperationAction(ISD::RET, MVT::Other, Custom);
137 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
138 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
140 setStackPointerRegisterToSaveRestore(Alpha::R30);
142 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
143 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
144 addLegalFPImmediate(APFloat(+0.0)); //F31
145 addLegalFPImmediate(APFloat(+0.0f)); //F31
146 addLegalFPImmediate(APFloat(-0.0)); //-F31
147 addLegalFPImmediate(APFloat(-0.0f)); //-F31
150 setJumpBufAlignment(16);
152 computeRegisterProperties();
155 const char *AlphaTargetLowering::getTargetNodeName(unsigned Opcode) const {
158 case AlphaISD::CVTQT_: return "Alpha::CVTQT_";
159 case AlphaISD::CVTQS_: return "Alpha::CVTQS_";
160 case AlphaISD::CVTTQ_: return "Alpha::CVTTQ_";
161 case AlphaISD::GPRelHi: return "Alpha::GPRelHi";
162 case AlphaISD::GPRelLo: return "Alpha::GPRelLo";
163 case AlphaISD::RelLit: return "Alpha::RelLit";
164 case AlphaISD::GlobalRetAddr: return "Alpha::GlobalRetAddr";
165 case AlphaISD::CALL: return "Alpha::CALL";
166 case AlphaISD::DivCall: return "Alpha::DivCall";
167 case AlphaISD::RET_FLAG: return "Alpha::RET_FLAG";
168 case AlphaISD::COND_BRANCH_I: return "Alpha::COND_BRANCH_I";
169 case AlphaISD::COND_BRANCH_F: return "Alpha::COND_BRANCH_F";
173 static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
174 MVT::ValueType PtrVT = Op.getValueType();
175 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
176 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
177 SDOperand Zero = DAG.getConstant(0, PtrVT);
179 SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, JTI,
180 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
181 SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, JTI, Hi);
185 //http://www.cs.arizona.edu/computer.help/policy/DIGITAL_unix/
186 //AA-PY8AC-TET1_html/callCH3.html#BLOCK21
188 //For now, just use variable size stack frame format
190 //In a standard call, the first six items are passed in registers $16
191 //- $21 and/or registers $f16 - $f21. (See Section 4.1.2 for details
192 //of argument-to-register correspondence.) The remaining items are
193 //collected in a memory argument list that is a naturally aligned
194 //array of quadwords. In a standard call, this list, if present, must
195 //be passed at 0(SP).
196 //7 ... n 0(SP) ... (n-7)*8(SP)
204 static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
206 int &VarArgsOffset) {
207 MachineFunction &MF = DAG.getMachineFunction();
208 MachineFrameInfo *MFI = MF.getFrameInfo();
209 std::vector<SDOperand> ArgValues;
210 SDOperand Root = Op.getOperand(0);
212 AddLiveIn(MF, Alpha::R29, &Alpha::GPRCRegClass); //GP
213 AddLiveIn(MF, Alpha::R26, &Alpha::GPRCRegClass); //RA
215 unsigned args_int[] = {
216 Alpha::R16, Alpha::R17, Alpha::R18, Alpha::R19, Alpha::R20, Alpha::R21};
217 unsigned args_float[] = {
218 Alpha::F16, Alpha::F17, Alpha::F18, Alpha::F19, Alpha::F20, Alpha::F21};
220 for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
222 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
228 cerr << "Unknown Type " << ObjectVT << "\n";
231 args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
232 &Alpha::F8RCRegClass);
233 ArgVal = DAG.getCopyFromReg(Root, args_float[ArgNo], ObjectVT);
236 args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
237 &Alpha::F4RCRegClass);
238 ArgVal = DAG.getCopyFromReg(Root, args_float[ArgNo], ObjectVT);
241 args_int[ArgNo] = AddLiveIn(MF, args_int[ArgNo],
242 &Alpha::GPRCRegClass);
243 ArgVal = DAG.getCopyFromReg(Root, args_int[ArgNo], MVT::i64);
247 // Create the frame index object for this incoming parameter...
248 int FI = MFI->CreateFixedObject(8, 8 * (ArgNo - 6));
250 // Create the SelectionDAG nodes corresponding to a load
251 //from this parameter
252 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
253 ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
255 ArgValues.push_back(ArgVal);
258 // If the functions takes variable number of arguments, copy all regs to stack
259 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
261 VarArgsOffset = (Op.Val->getNumValues()-1) * 8;
262 std::vector<SDOperand> LS;
263 for (int i = 0; i < 6; ++i) {
264 if (MRegisterInfo::isPhysicalRegister(args_int[i]))
265 args_int[i] = AddLiveIn(MF, args_int[i], &Alpha::GPRCRegClass);
266 SDOperand argt = DAG.getCopyFromReg(Root, args_int[i], MVT::i64);
267 int FI = MFI->CreateFixedObject(8, -8 * (6 - i));
268 if (i == 0) VarArgsBase = FI;
269 SDOperand SDFI = DAG.getFrameIndex(FI, MVT::i64);
270 LS.push_back(DAG.getStore(Root, argt, SDFI, NULL, 0));
272 if (MRegisterInfo::isPhysicalRegister(args_float[i]))
273 args_float[i] = AddLiveIn(MF, args_float[i], &Alpha::F8RCRegClass);
274 argt = DAG.getCopyFromReg(Root, args_float[i], MVT::f64);
275 FI = MFI->CreateFixedObject(8, - 8 * (12 - i));
276 SDFI = DAG.getFrameIndex(FI, MVT::i64);
277 LS.push_back(DAG.getStore(Root, argt, SDFI, NULL, 0));
280 //Set up a token factor with all the stack traffic
281 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, &LS[0], LS.size());
284 ArgValues.push_back(Root);
286 // Return the new list of results.
287 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
288 Op.Val->value_end());
289 return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size());
292 static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
293 SDOperand Copy = DAG.getCopyToReg(Op.getOperand(0), Alpha::R26,
294 DAG.getNode(AlphaISD::GlobalRetAddr,
297 switch (Op.getNumOperands()) {
299 assert(0 && "Do not know how to return this many arguments!");
303 //return SDOperand(); // ret void is legal
305 MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
307 if (MVT::isInteger(ArgVT))
310 assert(MVT::isFloatingPoint(ArgVT));
313 Copy = DAG.getCopyToReg(Copy, ArgReg, Op.getOperand(1), Copy.getValue(1));
314 if (DAG.getMachineFunction().getRegInfo().liveout_empty())
315 DAG.getMachineFunction().getRegInfo().addLiveOut(ArgReg);
319 return DAG.getNode(AlphaISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
322 std::pair<SDOperand, SDOperand>
323 AlphaTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
324 bool RetTyIsSigned, bool isVarArg,
325 unsigned CallingConv, bool isTailCall,
326 SDOperand Callee, ArgListTy &Args,
330 NumBytes = (Args.size() - 6) * 8;
332 Chain = DAG.getCALLSEQ_START(Chain,
333 DAG.getConstant(NumBytes, getPointerTy()));
334 std::vector<SDOperand> args_to_use;
335 for (unsigned i = 0, e = Args.size(); i != e; ++i)
337 switch (getValueType(Args[i].Ty)) {
338 default: assert(0 && "Unexpected ValueType for argument!");
343 // Promote the integer to 64 bits. If the input type is signed use a
344 // sign extend, otherwise use a zero extend.
346 Args[i].Node = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64, Args[i].Node);
347 else if (Args[i].isZExt)
348 Args[i].Node = DAG.getNode(ISD::ZERO_EXTEND, MVT::i64, Args[i].Node);
350 Args[i].Node = DAG.getNode(ISD::ANY_EXTEND, MVT::i64, Args[i].Node);
357 args_to_use.push_back(Args[i].Node);
360 std::vector<MVT::ValueType> RetVals;
361 MVT::ValueType RetTyVT = getValueType(RetTy);
362 MVT::ValueType ActualRetTyVT = RetTyVT;
363 if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i32)
364 ActualRetTyVT = MVT::i64;
366 if (RetTyVT != MVT::isVoid)
367 RetVals.push_back(ActualRetTyVT);
368 RetVals.push_back(MVT::Other);
370 std::vector<SDOperand> Ops;
371 Ops.push_back(Chain);
372 Ops.push_back(Callee);
373 Ops.insert(Ops.end(), args_to_use.begin(), args_to_use.end());
374 SDOperand TheCall = DAG.getNode(AlphaISD::CALL, RetVals, &Ops[0], Ops.size());
375 Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
376 Chain = DAG.getCALLSEQ_END(Chain,
377 DAG.getConstant(NumBytes, getPointerTy()),
378 DAG.getConstant(0, getPointerTy()),
380 SDOperand RetVal = TheCall;
382 if (RetTyVT != ActualRetTyVT) {
383 RetVal = DAG.getNode(RetTyIsSigned ? ISD::AssertSext : ISD::AssertZext,
384 MVT::i64, RetVal, DAG.getValueType(RetTyVT));
385 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
388 return std::make_pair(RetVal, Chain);
391 /// LowerOperation - Provide custom lowering hooks for some operations.
393 SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
394 switch (Op.getOpcode()) {
395 default: assert(0 && "Wasn't expecting to be able to lower this!");
396 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG,
400 case ISD::RET: return LowerRET(Op,DAG);
401 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
403 case ISD::SINT_TO_FP: {
404 assert(MVT::i64 == Op.getOperand(0).getValueType() &&
405 "Unhandled SINT_TO_FP type in custom expander!");
407 bool isDouble = MVT::f64 == Op.getValueType();
408 LD = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0));
409 SDOperand FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_,
410 isDouble?MVT::f64:MVT::f32, LD);
413 case ISD::FP_TO_SINT: {
414 bool isDouble = MVT::f64 == Op.getOperand(0).getValueType();
415 SDOperand src = Op.getOperand(0);
417 if (!isDouble) //Promote
418 src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, src);
420 src = DAG.getNode(AlphaISD::CVTTQ_, MVT::f64, src);
422 return DAG.getNode(ISD::BIT_CONVERT, MVT::i64, src);
424 case ISD::ConstantPool: {
425 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
426 Constant *C = CP->getConstVal();
427 SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i64, CP->getAlignment());
429 SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, CPI,
430 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
431 SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, CPI, Hi);
434 case ISD::GlobalTLSAddress:
435 assert(0 && "TLS not implemented for Alpha.");
436 case ISD::GlobalAddress: {
437 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
438 GlobalValue *GV = GSDN->getGlobal();
439 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i64, GSDN->getOffset());
441 // if (!GV->hasWeakLinkage() && !GV->isDeclaration() && !GV->hasLinkOnceLinkage()) {
442 if (GV->hasInternalLinkage()) {
443 SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, GA,
444 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
445 SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, GA, Hi);
448 return DAG.getNode(AlphaISD::RelLit, MVT::i64, GA,
449 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
451 case ISD::ExternalSymbol: {
452 return DAG.getNode(AlphaISD::RelLit, MVT::i64,
453 DAG.getTargetExternalSymbol(cast<ExternalSymbolSDNode>(Op)
454 ->getSymbol(), MVT::i64),
455 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
460 //Expand only on constant case
461 if (Op.getOperand(1).getOpcode() == ISD::Constant) {
462 MVT::ValueType VT = Op.Val->getValueType(0);
463 SDOperand Tmp1 = Op.Val->getOpcode() == ISD::UREM ?
464 BuildUDIV(Op.Val, DAG, NULL) :
465 BuildSDIV(Op.Val, DAG, NULL);
466 Tmp1 = DAG.getNode(ISD::MUL, VT, Tmp1, Op.getOperand(1));
467 Tmp1 = DAG.getNode(ISD::SUB, VT, Op.getOperand(0), Tmp1);
473 if (MVT::isInteger(Op.getValueType())) {
474 if (Op.getOperand(1).getOpcode() == ISD::Constant)
475 return Op.getOpcode() == ISD::SDIV ? BuildSDIV(Op.Val, DAG, NULL)
476 : BuildUDIV(Op.Val, DAG, NULL);
477 const char* opstr = 0;
478 switch (Op.getOpcode()) {
479 case ISD::UREM: opstr = "__remqu"; break;
480 case ISD::SREM: opstr = "__remq"; break;
481 case ISD::UDIV: opstr = "__divqu"; break;
482 case ISD::SDIV: opstr = "__divq"; break;
484 SDOperand Tmp1 = Op.getOperand(0),
485 Tmp2 = Op.getOperand(1),
486 Addr = DAG.getExternalSymbol(opstr, MVT::i64);
487 return DAG.getNode(AlphaISD::DivCall, MVT::i64, Addr, Tmp1, Tmp2);
492 SDOperand Chain = Op.getOperand(0);
493 SDOperand VAListP = Op.getOperand(1);
494 SrcValueSDNode *VAListS = cast<SrcValueSDNode>(Op.getOperand(2));
496 SDOperand Base = DAG.getLoad(MVT::i64, Chain, VAListP, VAListS->getValue(),
497 VAListS->getOffset());
498 SDOperand Tmp = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
499 DAG.getConstant(8, MVT::i64));
500 SDOperand Offset = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Base.getValue(1),
501 Tmp, NULL, 0, MVT::i32);
502 SDOperand DataPtr = DAG.getNode(ISD::ADD, MVT::i64, Base, Offset);
503 if (MVT::isFloatingPoint(Op.getValueType()))
505 //if fp && Offset < 6*8, then subtract 6*8 from DataPtr
506 SDOperand FPDataPtr = DAG.getNode(ISD::SUB, MVT::i64, DataPtr,
507 DAG.getConstant(8*6, MVT::i64));
508 SDOperand CC = DAG.getSetCC(MVT::i64, Offset,
509 DAG.getConstant(8*6, MVT::i64), ISD::SETLT);
510 DataPtr = DAG.getNode(ISD::SELECT, MVT::i64, CC, FPDataPtr, DataPtr);
513 SDOperand NewOffset = DAG.getNode(ISD::ADD, MVT::i64, Offset,
514 DAG.getConstant(8, MVT::i64));
515 SDOperand Update = DAG.getTruncStore(Offset.getValue(1), NewOffset,
516 Tmp, NULL, 0, MVT::i32);
519 if (Op.getValueType() == MVT::i32)
520 Result = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Update, DataPtr,
523 Result = DAG.getLoad(Op.getValueType(), Update, DataPtr, NULL, 0);
527 SDOperand Chain = Op.getOperand(0);
528 SDOperand DestP = Op.getOperand(1);
529 SDOperand SrcP = Op.getOperand(2);
530 SrcValueSDNode *DestS = cast<SrcValueSDNode>(Op.getOperand(3));
531 SrcValueSDNode *SrcS = cast<SrcValueSDNode>(Op.getOperand(4));
533 SDOperand Val = DAG.getLoad(getPointerTy(), Chain, SrcP,
534 SrcS->getValue(), SrcS->getOffset());
535 SDOperand Result = DAG.getStore(Val.getValue(1), Val, DestP, DestS->getValue(),
537 SDOperand NP = DAG.getNode(ISD::ADD, MVT::i64, SrcP,
538 DAG.getConstant(8, MVT::i64));
539 Val = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Result, NP, NULL,0, MVT::i32);
540 SDOperand NPD = DAG.getNode(ISD::ADD, MVT::i64, DestP,
541 DAG.getConstant(8, MVT::i64));
542 return DAG.getTruncStore(Val.getValue(1), Val, NPD, NULL, 0, MVT::i32);
545 SDOperand Chain = Op.getOperand(0);
546 SDOperand VAListP = Op.getOperand(1);
547 SrcValueSDNode *VAListS = cast<SrcValueSDNode>(Op.getOperand(2));
549 // vastart stores the address of the VarArgsBase and VarArgsOffset
550 SDOperand FR = DAG.getFrameIndex(VarArgsBase, MVT::i64);
551 SDOperand S1 = DAG.getStore(Chain, FR, VAListP, VAListS->getValue(),
552 VAListS->getOffset());
553 SDOperand SA2 = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
554 DAG.getConstant(8, MVT::i64));
555 return DAG.getTruncStore(S1, DAG.getConstant(VarArgsOffset, MVT::i64),
556 SA2, NULL, 0, MVT::i32);
558 case ISD::RETURNADDR:
559 return DAG.getNode(AlphaISD::GlobalRetAddr, MVT::i64);
561 case ISD::FRAMEADDR: break;
567 SDOperand AlphaTargetLowering::CustomPromoteOperation(SDOperand Op,
569 assert(Op.getValueType() == MVT::i32 &&
570 Op.getOpcode() == ISD::VAARG &&
571 "Unknown node to custom promote!");
573 // The code in LowerOperation already handles i32 vaarg
574 return LowerOperation(Op, DAG);
580 /// getConstraintType - Given a constraint letter, return the type of
581 /// constraint it is for this target.
582 AlphaTargetLowering::ConstraintType
583 AlphaTargetLowering::getConstraintType(const std::string &Constraint) const {
584 if (Constraint.size() == 1) {
585 switch (Constraint[0]) {
589 return C_RegisterClass;
592 return TargetLowering::getConstraintType(Constraint);
595 std::vector<unsigned> AlphaTargetLowering::
596 getRegClassForInlineAsmConstraint(const std::string &Constraint,
597 MVT::ValueType VT) const {
598 if (Constraint.size() == 1) {
599 switch (Constraint[0]) {
600 default: break; // Unknown constriant letter
602 return make_vector<unsigned>(Alpha::F0 , Alpha::F1 , Alpha::F2 ,
603 Alpha::F3 , Alpha::F4 , Alpha::F5 ,
604 Alpha::F6 , Alpha::F7 , Alpha::F8 ,
605 Alpha::F9 , Alpha::F10, Alpha::F11,
606 Alpha::F12, Alpha::F13, Alpha::F14,
607 Alpha::F15, Alpha::F16, Alpha::F17,
608 Alpha::F18, Alpha::F19, Alpha::F20,
609 Alpha::F21, Alpha::F22, Alpha::F23,
610 Alpha::F24, Alpha::F25, Alpha::F26,
611 Alpha::F27, Alpha::F28, Alpha::F29,
612 Alpha::F30, Alpha::F31, 0);
614 return make_vector<unsigned>(Alpha::R0 , Alpha::R1 , Alpha::R2 ,
615 Alpha::R3 , Alpha::R4 , Alpha::R5 ,
616 Alpha::R6 , Alpha::R7 , Alpha::R8 ,
617 Alpha::R9 , Alpha::R10, Alpha::R11,
618 Alpha::R12, Alpha::R13, Alpha::R14,
619 Alpha::R15, Alpha::R16, Alpha::R17,
620 Alpha::R18, Alpha::R19, Alpha::R20,
621 Alpha::R21, Alpha::R22, Alpha::R23,
622 Alpha::R24, Alpha::R25, Alpha::R26,
623 Alpha::R27, Alpha::R28, Alpha::R29,
624 Alpha::R30, Alpha::R31, 0);
628 return std::vector<unsigned>();