1 //===-- AlphaISelLowering.cpp - Alpha DAG Lowering Implementation ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Andrew Lenharth and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AlphaISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "AlphaISelLowering.h"
15 #include "AlphaTargetMachine.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/CodeGen/SSARegMap.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/Module.h"
24 #include "llvm/Support/CommandLine.h"
28 //Shamelessly adapted from PPC32
29 // Structure used to return the necessary information to codegen an SDIV as
32 int64_t m; // magic number
33 int64_t s; // shift amount
37 uint64_t m; // magic number
38 int64_t a; // add indicator
39 int64_t s; // shift amount
42 /// magic - calculate the magic numbers required to codegen an integer sdiv as
43 /// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
45 static struct ms magic(int64_t d) {
47 uint64_t ad, anc, delta, q1, r1, q2, r2, t;
48 const uint64_t two63 = 9223372036854775808ULL; // 2^63
52 t = two63 + ((uint64_t)d >> 63);
53 anc = t - 1 - t%ad; // absolute value of nc
54 p = 63; // initialize p
55 q1 = two63/anc; // initialize q1 = 2p/abs(nc)
56 r1 = two63 - q1*anc; // initialize r1 = rem(2p,abs(nc))
57 q2 = two63/ad; // initialize q2 = 2p/abs(d)
58 r2 = two63 - q2*ad; // initialize r2 = rem(2p,abs(d))
61 q1 = 2*q1; // update q1 = 2p/abs(nc)
62 r1 = 2*r1; // update r1 = rem(2p/abs(nc))
63 if (r1 >= anc) { // must be unsigned comparison
67 q2 = 2*q2; // update q2 = 2p/abs(d)
68 r2 = 2*r2; // update r2 = rem(2p/abs(d))
69 if (r2 >= ad) { // must be unsigned comparison
74 } while (q1 < delta || (q1 == delta && r1 == 0));
77 if (d < 0) mag.m = -mag.m; // resulting magic number
78 mag.s = p - 64; // resulting shift
82 /// magicu - calculate the magic numbers required to codegen an integer udiv as
83 /// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
84 static struct mu magicu(uint64_t d)
87 uint64_t nc, delta, q1, r1, q2, r2;
89 magu.a = 0; // initialize "add" indicator
91 p = 63; // initialize p
92 q1 = 0x8000000000000000ull/nc; // initialize q1 = 2p/nc
93 r1 = 0x8000000000000000ull - q1*nc; // initialize r1 = rem(2p,nc)
94 q2 = 0x7FFFFFFFFFFFFFFFull/d; // initialize q2 = (2p-1)/d
95 r2 = 0x7FFFFFFFFFFFFFFFull - q2*d; // initialize r2 = rem((2p-1),d)
99 q1 = 2*q1 + 1; // update q1
100 r1 = 2*r1 - nc; // update r1
103 q1 = 2*q1; // update q1
104 r1 = 2*r1; // update r1
106 if (r2 + 1 >= d - r2) {
107 if (q2 >= 0x7FFFFFFFFFFFFFFFull) magu.a = 1;
108 q2 = 2*q2 + 1; // update q2
109 r2 = 2*r2 + 1 - d; // update r2
112 if (q2 >= 0x8000000000000000ull) magu.a = 1;
113 q2 = 2*q2; // update q2
114 r2 = 2*r2 + 1; // update r2
117 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0)));
118 magu.m = q2 + 1; // resulting magic number
119 magu.s = p - 64; // resulting shift
123 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
124 /// return a DAG expression to select that will generate the same value by
125 /// multiplying by a magic number. See:
126 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
127 static SDOperand BuildSDIVSequence(SDOperand N, SelectionDAG* ISelDAG) {
128 int64_t d = (int64_t)cast<ConstantSDNode>(N.getOperand(1))->getSignExtended();
129 ms magics = magic(d);
130 // Multiply the numerator (operand 0) by the magic value
131 SDOperand Q = ISelDAG->getNode(ISD::MULHS, MVT::i64, N.getOperand(0),
132 ISelDAG->getConstant(magics.m, MVT::i64));
133 // If d > 0 and m < 0, add the numerator
134 if (d > 0 && magics.m < 0)
135 Q = ISelDAG->getNode(ISD::ADD, MVT::i64, Q, N.getOperand(0));
136 // If d < 0 and m > 0, subtract the numerator.
137 if (d < 0 && magics.m > 0)
138 Q = ISelDAG->getNode(ISD::SUB, MVT::i64, Q, N.getOperand(0));
139 // Shift right algebraic if shift value is nonzero
141 Q = ISelDAG->getNode(ISD::SRA, MVT::i64, Q,
142 ISelDAG->getConstant(magics.s, MVT::i64));
143 // Extract the sign bit and add it to the quotient
145 ISelDAG->getNode(ISD::SRL, MVT::i64, Q, ISelDAG->getConstant(63, MVT::i64));
146 return ISelDAG->getNode(ISD::ADD, MVT::i64, Q, T);
149 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
150 /// return a DAG expression to select that will generate the same value by
151 /// multiplying by a magic number. See:
152 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
153 static SDOperand BuildUDIVSequence(SDOperand N, SelectionDAG* ISelDAG) {
155 (unsigned)cast<ConstantSDNode>(N.getOperand(1))->getSignExtended();
156 mu magics = magicu(d);
157 // Multiply the numerator (operand 0) by the magic value
158 SDOperand Q = ISelDAG->getNode(ISD::MULHU, MVT::i64, N.getOperand(0),
159 ISelDAG->getConstant(magics.m, MVT::i64));
161 Q = ISelDAG->getNode(ISD::SRL, MVT::i64, Q,
162 ISelDAG->getConstant(magics.s, MVT::i64));
164 SDOperand NPQ = ISelDAG->getNode(ISD::SUB, MVT::i64, N.getOperand(0), Q);
165 NPQ = ISelDAG->getNode(ISD::SRL, MVT::i64, NPQ,
166 ISelDAG->getConstant(1, MVT::i64));
167 NPQ = ISelDAG->getNode(ISD::ADD, MVT::i64, NPQ, Q);
168 Q = ISelDAG->getNode(ISD::SRL, MVT::i64, NPQ,
169 ISelDAG->getConstant(magics.s-1, MVT::i64));
174 /// AddLiveIn - This helper function adds the specified physical register to the
175 /// MachineFunction as a live in value. It also creates a corresponding virtual
177 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
178 TargetRegisterClass *RC) {
179 assert(RC->contains(PReg) && "Not the correct regclass!");
180 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
181 MF.addLiveIn(PReg, VReg);
185 AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM) {
186 // Set up the TargetLowering object.
187 //I am having problems with shr n ubyte 1
188 setShiftAmountType(MVT::i64);
189 setSetCCResultType(MVT::i64);
190 setSetCCResultContents(ZeroOrOneSetCCResult);
192 addRegisterClass(MVT::i64, Alpha::GPRCRegisterClass);
193 addRegisterClass(MVT::f64, Alpha::F8RCRegisterClass);
194 addRegisterClass(MVT::f32, Alpha::F4RCRegisterClass);
196 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
197 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
199 setOperationAction(ISD::EXTLOAD, MVT::i1, Promote);
200 setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
202 setOperationAction(ISD::ZEXTLOAD, MVT::i1, Promote);
203 setOperationAction(ISD::ZEXTLOAD, MVT::i32, Expand);
205 setOperationAction(ISD::SEXTLOAD, MVT::i1, Promote);
206 setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
207 setOperationAction(ISD::SEXTLOAD, MVT::i16, Expand);
209 setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote);
211 setOperationAction(ISD::FREM, MVT::f32, Expand);
212 setOperationAction(ISD::FREM, MVT::f64, Expand);
214 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
215 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
216 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
217 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
219 if (!TM.getSubtarget<AlphaSubtarget>().hasCT()) {
220 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
221 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
222 setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
224 setOperationAction(ISD::BSWAP , MVT::i64, Expand);
225 setOperationAction(ISD::ROTL , MVT::i64, Expand);
226 setOperationAction(ISD::ROTR , MVT::i64, Expand);
228 setOperationAction(ISD::SREM , MVT::i64, Custom);
229 setOperationAction(ISD::UREM , MVT::i64, Custom);
230 setOperationAction(ISD::SDIV , MVT::i64, Custom);
231 setOperationAction(ISD::UDIV , MVT::i64, Custom);
233 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
234 setOperationAction(ISD::MEMSET , MVT::Other, Expand);
235 setOperationAction(ISD::MEMCPY , MVT::Other, Expand);
237 // We don't support sin/cos/sqrt
238 setOperationAction(ISD::FSIN , MVT::f64, Expand);
239 setOperationAction(ISD::FCOS , MVT::f64, Expand);
240 setOperationAction(ISD::FSIN , MVT::f32, Expand);
241 setOperationAction(ISD::FCOS , MVT::f32, Expand);
243 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
244 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
246 // FIXME: Alpha supports fcopysign natively!?
247 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
248 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
250 setOperationAction(ISD::SETCC, MVT::f32, Promote);
252 // We don't have line number support yet.
253 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
254 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
255 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
257 // Not implemented yet.
258 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
259 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
260 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
262 // We want to legalize GlobalAddress and ConstantPool and
263 // ExternalSymbols nodes into the appropriate instructions to
264 // materialize the address.
265 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
266 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
267 setOperationAction(ISD::ExternalSymbol, MVT::i64, Custom);
269 setOperationAction(ISD::VASTART, MVT::Other, Custom);
270 setOperationAction(ISD::VAEND, MVT::Other, Expand);
271 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
272 setOperationAction(ISD::VAARG, MVT::Other, Custom);
273 setOperationAction(ISD::VAARG, MVT::i32, Custom);
275 setStackPointerRegisterToSaveRestore(Alpha::R30);
277 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
278 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
279 addLegalFPImmediate(+0.0); //F31
280 addLegalFPImmediate(-0.0); //-F31
282 computeRegisterProperties();
284 useITOF = TM.getSubtarget<AlphaSubtarget>().hasF2I();
287 const char *AlphaTargetLowering::getTargetNodeName(unsigned Opcode) const {
290 case AlphaISD::ITOFT_: return "Alpha::ITOFT_";
291 case AlphaISD::FTOIT_: return "Alpha::FTOIT_";
292 case AlphaISD::CVTQT_: return "Alpha::CVTQT_";
293 case AlphaISD::CVTQS_: return "Alpha::CVTQS_";
294 case AlphaISD::CVTTQ_: return "Alpha::CVTTQ_";
295 case AlphaISD::GPRelHi: return "Alpha::GPRelHi";
296 case AlphaISD::GPRelLo: return "Alpha::GPRelLo";
297 case AlphaISD::RelLit: return "Alpha::RelLit";
298 case AlphaISD::GlobalBaseReg: return "Alpha::GlobalBaseReg";
299 case AlphaISD::CALL: return "Alpha::CALL";
300 case AlphaISD::DivCall: return "Alpha::DivCall";
304 //http://www.cs.arizona.edu/computer.help/policy/DIGITAL_unix/AA-PY8AC-TET1_html/callCH3.html#BLOCK21
306 //For now, just use variable size stack frame format
308 //In a standard call, the first six items are passed in registers $16
309 //- $21 and/or registers $f16 - $f21. (See Section 4.1.2 for details
310 //of argument-to-register correspondence.) The remaining items are
311 //collected in a memory argument list that is a naturally aligned
312 //array of quadwords. In a standard call, this list, if present, must
313 //be passed at 0(SP).
314 //7 ... n 0(SP) ... (n-7)*8(SP)
322 std::vector<SDOperand>
323 AlphaTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG)
325 MachineFunction &MF = DAG.getMachineFunction();
326 MachineFrameInfo *MFI = MF.getFrameInfo();
327 MachineBasicBlock& BB = MF.front();
328 std::vector<SDOperand> ArgValues;
330 unsigned args_int[] = {
331 Alpha::R16, Alpha::R17, Alpha::R18, Alpha::R19, Alpha::R20, Alpha::R21};
332 unsigned args_float[] = {
333 Alpha::F16, Alpha::F17, Alpha::F18, Alpha::F19, Alpha::F20, Alpha::F21};
337 GP = AddLiveIn(MF, Alpha::R29, getRegClassFor(MVT::i64));
338 RA = AddLiveIn(MF, Alpha::R26, getRegClassFor(MVT::i64));
340 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I)
345 MVT::ValueType VT = getValueType(I->getType());
348 std::cerr << "Unknown Type " << VT << "\n";
352 args_float[count] = AddLiveIn(MF, args_float[count], getRegClassFor(VT));
353 argt = DAG.getCopyFromReg(DAG.getRoot(), args_float[count], VT);
354 DAG.setRoot(argt.getValue(1));
361 args_int[count] = AddLiveIn(MF, args_int[count], getRegClassFor(MVT::i64));
362 argt = DAG.getCopyFromReg(DAG.getRoot(), args_int[count], MVT::i64);
363 DAG.setRoot(argt.getValue(1));
364 if (VT != MVT::i64) {
366 I->getType()->isSigned() ? ISD::AssertSext : ISD::AssertZext;
367 argt = DAG.getNode(AssertOp, MVT::i64, argt,
368 DAG.getValueType(VT));
369 argt = DAG.getNode(ISD::TRUNCATE, VT, argt);
374 // Create the frame index object for this incoming parameter...
375 int FI = MFI->CreateFixedObject(8, 8 * (count - 6));
377 // Create the SelectionDAG nodes corresponding to a load
378 //from this parameter
379 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
380 argt = DAG.getLoad(getValueType(I->getType()),
381 DAG.getEntryNode(), FIN, DAG.getSrcValue(NULL));
384 ArgValues.push_back(argt);
387 // If the functions takes variable number of arguments, copy all regs to stack
389 VarArgsOffset = count * 8;
390 std::vector<SDOperand> LS;
391 for (int i = 0; i < 6; ++i) {
392 if (MRegisterInfo::isPhysicalRegister(args_int[i]))
393 args_int[i] = AddLiveIn(MF, args_int[i], getRegClassFor(MVT::i64));
394 SDOperand argt = DAG.getCopyFromReg(DAG.getRoot(), args_int[i], MVT::i64);
395 int FI = MFI->CreateFixedObject(8, -8 * (6 - i));
396 if (i == 0) VarArgsBase = FI;
397 SDOperand SDFI = DAG.getFrameIndex(FI, MVT::i64);
398 LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), argt,
399 SDFI, DAG.getSrcValue(NULL)));
401 if (MRegisterInfo::isPhysicalRegister(args_float[i]))
402 args_float[i] = AddLiveIn(MF, args_float[i], getRegClassFor(MVT::f64));
403 argt = DAG.getCopyFromReg(DAG.getRoot(), args_float[i], MVT::f64);
404 FI = MFI->CreateFixedObject(8, - 8 * (12 - i));
405 SDFI = DAG.getFrameIndex(FI, MVT::i64);
406 LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), argt,
407 SDFI, DAG.getSrcValue(NULL)));
410 //Set up a token factor with all the stack traffic
411 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, LS));
414 // Finally, inform the code generator which regs we return values in.
415 switch (getValueType(F.getReturnType())) {
416 default: assert(0 && "Unknown type!");
417 case MVT::isVoid: break;
423 MF.addLiveOut(Alpha::R0);
427 MF.addLiveOut(Alpha::F0);
431 //return the arguments+
435 std::pair<SDOperand, SDOperand>
436 AlphaTargetLowering::LowerCallTo(SDOperand Chain,
437 const Type *RetTy, bool isVarArg,
438 unsigned CallingConv, bool isTailCall,
439 SDOperand Callee, ArgListTy &Args,
443 NumBytes = (Args.size() - 6) * 8;
445 Chain = DAG.getCALLSEQ_START(Chain,
446 DAG.getConstant(NumBytes, getPointerTy()));
447 std::vector<SDOperand> args_to_use;
448 for (unsigned i = 0, e = Args.size(); i != e; ++i)
450 switch (getValueType(Args[i].second)) {
451 default: assert(0 && "Unexpected ValueType for argument!");
456 // Promote the integer to 64 bits. If the input type is signed use a
457 // sign extend, otherwise use a zero extend.
458 if (Args[i].second->isSigned())
459 Args[i].first = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64, Args[i].first);
461 Args[i].first = DAG.getNode(ISD::ZERO_EXTEND, MVT::i64, Args[i].first);
468 args_to_use.push_back(Args[i].first);
471 std::vector<MVT::ValueType> RetVals;
472 MVT::ValueType RetTyVT = getValueType(RetTy);
473 MVT::ValueType ActualRetTyVT = RetTyVT;
474 if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i32)
475 ActualRetTyVT = MVT::i64;
477 if (RetTyVT != MVT::isVoid)
478 RetVals.push_back(ActualRetTyVT);
479 RetVals.push_back(MVT::Other);
481 std::vector<SDOperand> Ops;
482 Ops.push_back(Chain);
483 Ops.push_back(Callee);
484 Ops.insert(Ops.end(), args_to_use.begin(), args_to_use.end());
485 SDOperand TheCall = DAG.getNode(AlphaISD::CALL, RetVals, Ops);
486 Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
487 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
488 DAG.getConstant(NumBytes, getPointerTy()));
489 SDOperand RetVal = TheCall;
491 if (RetTyVT != ActualRetTyVT) {
492 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext : ISD::AssertZext,
493 MVT::i64, RetVal, DAG.getValueType(RetTyVT));
494 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
497 return std::make_pair(RetVal, Chain);
500 void AlphaTargetLowering::restoreGP(MachineBasicBlock* BB)
502 BuildMI(BB, Alpha::BIS, 2, Alpha::R29).addReg(GP).addReg(GP);
504 void AlphaTargetLowering::restoreRA(MachineBasicBlock* BB)
506 BuildMI(BB, Alpha::BIS, 2, Alpha::R26).addReg(RA).addReg(RA);
515 /// LowerOperation - Provide custom lowering hooks for some operations.
517 SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
518 switch (Op.getOpcode()) {
519 default: assert(0 && "Wasn't expecting to be able to lower this!");
520 case ISD::SINT_TO_FP: {
521 assert(MVT::i64 == Op.getOperand(0).getValueType() &&
522 "Unhandled SINT_TO_FP type in custom expander!");
524 bool isDouble = MVT::f64 == Op.getValueType();
526 LD = DAG.getNode(AlphaISD::ITOFT_, MVT::f64, Op.getOperand(0));
529 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
530 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i64);
531 SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
532 Op.getOperand(0), FI, DAG.getSrcValue(0));
533 LD = DAG.getLoad(MVT::f64, ST, FI, DAG.getSrcValue(0));
535 SDOperand FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_,
536 isDouble?MVT::f64:MVT::f32, LD);
539 case ISD::FP_TO_SINT: {
540 bool isDouble = MVT::f64 == Op.getOperand(0).getValueType();
541 SDOperand src = Op.getOperand(0);
543 if (!isDouble) //Promote
544 src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, src);
546 src = DAG.getNode(AlphaISD::CVTTQ_, MVT::f64, src);
549 return DAG.getNode(AlphaISD::FTOIT_, MVT::i64, src);
552 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
553 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i64);
554 SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
555 src, FI, DAG.getSrcValue(0));
556 return DAG.getLoad(MVT::i64, ST, FI, DAG.getSrcValue(0));
559 case ISD::ConstantPool: {
560 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
561 Constant *C = CP->get();
562 SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i64, CP->getAlignment());
564 SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, CPI,
565 DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
566 SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, CPI, Hi);
569 case ISD::GlobalAddress: {
570 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
571 GlobalValue *GV = GSDN->getGlobal();
572 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i64, GSDN->getOffset());
574 if (!GV->hasWeakLinkage() && !GV->isExternal()) {
575 SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, GA,
576 DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
577 SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, GA, Hi);
580 return DAG.getNode(AlphaISD::RelLit, MVT::i64, GA, DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
582 case ISD::ExternalSymbol: {
583 return DAG.getNode(AlphaISD::RelLit, MVT::i64,
584 DAG.getTargetExternalSymbol(cast<ExternalSymbolSDNode>(Op)->getSymbol(), MVT::i64),
585 DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
590 //Expand only on constant case
591 if (Op.getOperand(1).getOpcode() == ISD::Constant) {
592 MVT::ValueType VT = Op.Val->getValueType(0);
593 unsigned Opc = Op.Val->getOpcode() == ISD::UREM ? ISD::UDIV : ISD::SDIV;
594 SDOperand Tmp1 = Op.Val->getOpcode() == ISD::UREM ?
595 BuildUDIVSequence(Op, &DAG) :
596 BuildSDIVSequence(Op, &DAG);
597 Tmp1 = DAG.getNode(ISD::MUL, VT, Tmp1, Op.getOperand(1));
598 Tmp1 = DAG.getNode(ISD::SUB, VT, Op.getOperand(0), Tmp1);
604 if (MVT::isInteger(Op.getValueType())) {
605 const char* opstr = 0;
606 switch(Op.getOpcode()) {
607 case ISD::UREM: opstr = "__remqu"; break;
608 case ISD::SREM: opstr = "__remq"; break;
609 case ISD::UDIV: opstr = "__divqu"; break;
610 case ISD::SDIV: opstr = "__divq"; break;
612 SDOperand Tmp1 = Op.getOperand(0),
613 Tmp2 = Op.getOperand(1),
614 Addr = DAG.getExternalSymbol(opstr, MVT::i64);
615 return DAG.getNode(AlphaISD::DivCall, MVT::i64, Addr, Tmp1, Tmp2);
620 SDOperand Chain = Op.getOperand(0);
621 SDOperand VAListP = Op.getOperand(1);
622 SDOperand VAListS = Op.getOperand(2);
624 SDOperand Base = DAG.getLoad(MVT::i64, Chain, VAListP, VAListS);
625 SDOperand Tmp = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
626 DAG.getConstant(8, MVT::i64));
627 SDOperand Offset = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Base.getValue(1),
628 Tmp, DAG.getSrcValue(0), MVT::i32);
629 SDOperand DataPtr = DAG.getNode(ISD::ADD, MVT::i64, Base, Offset);
630 if (MVT::isFloatingPoint(Op.getValueType()))
632 //if fp && Offset < 6*8, then subtract 6*8 from DataPtr
633 SDOperand FPDataPtr = DAG.getNode(ISD::SUB, MVT::i64, DataPtr,
634 DAG.getConstant(8*6, MVT::i64));
635 SDOperand CC = DAG.getSetCC(MVT::i64, Offset,
636 DAG.getConstant(8*6, MVT::i64), ISD::SETLT);
637 DataPtr = DAG.getNode(ISD::SELECT, MVT::i64, CC, FPDataPtr, DataPtr);
640 SDOperand NewOffset = DAG.getNode(ISD::ADD, MVT::i64, Offset,
641 DAG.getConstant(8, MVT::i64));
642 SDOperand Update = DAG.getNode(ISD::TRUNCSTORE, MVT::Other,
643 Offset.getValue(1), NewOffset,
644 Tmp, DAG.getSrcValue(0),
645 DAG.getValueType(MVT::i32));
648 if (Op.getValueType() == MVT::i32)
649 Result = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Update, DataPtr,
650 DAG.getSrcValue(0), MVT::i32);
652 Result = DAG.getLoad(Op.getValueType(), Update, DataPtr,
657 SDOperand Chain = Op.getOperand(0);
658 SDOperand DestP = Op.getOperand(1);
659 SDOperand SrcP = Op.getOperand(2);
660 SDOperand DestS = Op.getOperand(3);
661 SDOperand SrcS = Op.getOperand(4);
663 SDOperand Val = DAG.getLoad(getPointerTy(), Chain, SrcP, SrcS);
664 SDOperand Result = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1), Val,
666 SDOperand NP = DAG.getNode(ISD::ADD, MVT::i64, SrcP,
667 DAG.getConstant(8, MVT::i64));
668 Val = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Result, NP,
669 DAG.getSrcValue(0), MVT::i32);
670 SDOperand NPD = DAG.getNode(ISD::ADD, MVT::i64, DestP,
671 DAG.getConstant(8, MVT::i64));
672 return DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Val.getValue(1),
673 Val, NPD, DAG.getSrcValue(0),DAG.getValueType(MVT::i32));
676 SDOperand Chain = Op.getOperand(0);
677 SDOperand VAListP = Op.getOperand(1);
678 SDOperand VAListS = Op.getOperand(2);
680 // vastart stores the address of the VarArgsBase and VarArgsOffset
681 SDOperand FR = DAG.getFrameIndex(VarArgsBase, MVT::i64);
682 SDOperand S1 = DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP,
684 SDOperand SA2 = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
685 DAG.getConstant(8, MVT::i64));
686 return DAG.getNode(ISD::TRUNCSTORE, MVT::Other, S1,
687 DAG.getConstant(VarArgsOffset, MVT::i64), SA2,
688 DAG.getSrcValue(0), DAG.getValueType(MVT::i32));
695 SDOperand AlphaTargetLowering::CustomPromoteOperation(SDOperand Op,
697 assert(Op.getValueType() == MVT::i32 &&
698 Op.getOpcode() == ISD::VAARG &&
699 "Unknown node to custom promote!");
701 // The code in LowerOperation already handles i32 vaarg
702 return LowerOperation(Op, DAG);