1 //===-- AlphaISelLowering.cpp - Alpha DAG Lowering Implementation ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Andrew Lenharth and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AlphaISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "AlphaISelLowering.h"
15 #include "AlphaTargetMachine.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/CodeGen/SSARegMap.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/Module.h"
24 #include "llvm/Support/CommandLine.h"
27 /// AddLiveIn - This helper function adds the specified physical register to the
28 /// MachineFunction as a live in value. It also creates a corresponding virtual
30 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
31 TargetRegisterClass *RC) {
32 assert(RC->contains(PReg) && "Not the correct regclass!");
33 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
34 MF.addLiveIn(PReg, VReg);
38 AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM) {
39 // Set up the TargetLowering object.
40 //I am having problems with shr n ubyte 1
41 setShiftAmountType(MVT::i64);
42 setSetCCResultType(MVT::i64);
43 setSetCCResultContents(ZeroOrOneSetCCResult);
45 setUsesGlobalOffsetTable(true);
47 addRegisterClass(MVT::i64, Alpha::GPRCRegisterClass);
48 addRegisterClass(MVT::f64, Alpha::F8RCRegisterClass);
49 addRegisterClass(MVT::f32, Alpha::F4RCRegisterClass);
51 setLoadXAction(ISD::EXTLOAD, MVT::i1, Promote);
52 setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand);
54 setLoadXAction(ISD::ZEXTLOAD, MVT::i1, Promote);
55 setLoadXAction(ISD::ZEXTLOAD, MVT::i32, Expand);
57 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
58 setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand);
59 setLoadXAction(ISD::SEXTLOAD, MVT::i16, Expand);
61 setStoreXAction(MVT::i1, Promote);
63 // setOperationAction(ISD::BRIND, MVT::Other, Expand);
64 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
65 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
66 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
68 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
70 setOperationAction(ISD::FREM, MVT::f32, Expand);
71 setOperationAction(ISD::FREM, MVT::f64, Expand);
73 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
74 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
75 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
76 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
78 if (!TM.getSubtarget<AlphaSubtarget>().hasCT()) {
79 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
80 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
81 setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
83 setOperationAction(ISD::BSWAP , MVT::i64, Expand);
84 setOperationAction(ISD::ROTL , MVT::i64, Expand);
85 setOperationAction(ISD::ROTR , MVT::i64, Expand);
87 setOperationAction(ISD::SREM , MVT::i64, Custom);
88 setOperationAction(ISD::UREM , MVT::i64, Custom);
89 setOperationAction(ISD::SDIV , MVT::i64, Custom);
90 setOperationAction(ISD::UDIV , MVT::i64, Custom);
92 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
93 setOperationAction(ISD::MEMSET , MVT::Other, Expand);
94 setOperationAction(ISD::MEMCPY , MVT::Other, Expand);
96 // We don't support sin/cos/sqrt/pow
97 setOperationAction(ISD::FSIN , MVT::f64, Expand);
98 setOperationAction(ISD::FCOS , MVT::f64, Expand);
99 setOperationAction(ISD::FSIN , MVT::f32, Expand);
100 setOperationAction(ISD::FCOS , MVT::f32, Expand);
102 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
103 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
105 setOperationAction(ISD::FPOW , MVT::f32, Expand);
106 setOperationAction(ISD::FPOW , MVT::f64, Expand);
108 setOperationAction(ISD::SETCC, MVT::f32, Promote);
110 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Promote);
112 // We don't have line number support yet.
113 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
114 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
115 setOperationAction(ISD::LABEL, MVT::Other, Expand);
117 // Not implemented yet.
118 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
119 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
120 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
122 // We want to legalize GlobalAddress and ConstantPool and
123 // ExternalSymbols nodes into the appropriate instructions to
124 // materialize the address.
125 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
126 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
127 setOperationAction(ISD::ExternalSymbol, MVT::i64, Custom);
128 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
130 setOperationAction(ISD::VASTART, MVT::Other, Custom);
131 setOperationAction(ISD::VAEND, MVT::Other, Expand);
132 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
133 setOperationAction(ISD::VAARG, MVT::Other, Custom);
134 setOperationAction(ISD::VAARG, MVT::i32, Custom);
136 setOperationAction(ISD::RET, MVT::Other, Custom);
138 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
139 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
141 setStackPointerRegisterToSaveRestore(Alpha::R30);
143 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
144 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
145 addLegalFPImmediate(APFloat(+0.0)); //F31
146 addLegalFPImmediate(APFloat(+0.0f)); //F31
147 addLegalFPImmediate(APFloat(-0.0)); //-F31
148 addLegalFPImmediate(APFloat(-0.0f)); //-F31
151 setJumpBufAlignment(16);
153 computeRegisterProperties();
156 const char *AlphaTargetLowering::getTargetNodeName(unsigned Opcode) const {
159 case AlphaISD::CVTQT_: return "Alpha::CVTQT_";
160 case AlphaISD::CVTQS_: return "Alpha::CVTQS_";
161 case AlphaISD::CVTTQ_: return "Alpha::CVTTQ_";
162 case AlphaISD::GPRelHi: return "Alpha::GPRelHi";
163 case AlphaISD::GPRelLo: return "Alpha::GPRelLo";
164 case AlphaISD::RelLit: return "Alpha::RelLit";
165 case AlphaISD::GlobalRetAddr: return "Alpha::GlobalRetAddr";
166 case AlphaISD::CALL: return "Alpha::CALL";
167 case AlphaISD::DivCall: return "Alpha::DivCall";
168 case AlphaISD::RET_FLAG: return "Alpha::RET_FLAG";
169 case AlphaISD::COND_BRANCH_I: return "Alpha::COND_BRANCH_I";
170 case AlphaISD::COND_BRANCH_F: return "Alpha::COND_BRANCH_F";
174 static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
175 MVT::ValueType PtrVT = Op.getValueType();
176 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
177 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
178 SDOperand Zero = DAG.getConstant(0, PtrVT);
180 SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, JTI,
181 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
182 SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, JTI, Hi);
186 //http://www.cs.arizona.edu/computer.help/policy/DIGITAL_unix/
187 //AA-PY8AC-TET1_html/callCH3.html#BLOCK21
189 //For now, just use variable size stack frame format
191 //In a standard call, the first six items are passed in registers $16
192 //- $21 and/or registers $f16 - $f21. (See Section 4.1.2 for details
193 //of argument-to-register correspondence.) The remaining items are
194 //collected in a memory argument list that is a naturally aligned
195 //array of quadwords. In a standard call, this list, if present, must
196 //be passed at 0(SP).
197 //7 ... n 0(SP) ... (n-7)*8(SP)
205 static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
207 int &VarArgsOffset) {
208 MachineFunction &MF = DAG.getMachineFunction();
209 MachineFrameInfo *MFI = MF.getFrameInfo();
210 std::vector<SDOperand> ArgValues;
211 SDOperand Root = Op.getOperand(0);
213 AddLiveIn(MF, Alpha::R29, &Alpha::GPRCRegClass); //GP
214 AddLiveIn(MF, Alpha::R26, &Alpha::GPRCRegClass); //RA
216 unsigned args_int[] = {
217 Alpha::R16, Alpha::R17, Alpha::R18, Alpha::R19, Alpha::R20, Alpha::R21};
218 unsigned args_float[] = {
219 Alpha::F16, Alpha::F17, Alpha::F18, Alpha::F19, Alpha::F20, Alpha::F21};
221 for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
223 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
229 cerr << "Unknown Type " << ObjectVT << "\n";
232 args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
233 &Alpha::F8RCRegClass);
234 ArgVal = DAG.getCopyFromReg(Root, args_float[ArgNo], ObjectVT);
237 args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
238 &Alpha::F4RCRegClass);
239 ArgVal = DAG.getCopyFromReg(Root, args_float[ArgNo], ObjectVT);
242 args_int[ArgNo] = AddLiveIn(MF, args_int[ArgNo],
243 &Alpha::GPRCRegClass);
244 ArgVal = DAG.getCopyFromReg(Root, args_int[ArgNo], MVT::i64);
248 // Create the frame index object for this incoming parameter...
249 int FI = MFI->CreateFixedObject(8, 8 * (ArgNo - 6));
251 // Create the SelectionDAG nodes corresponding to a load
252 //from this parameter
253 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
254 ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
256 ArgValues.push_back(ArgVal);
259 // If the functions takes variable number of arguments, copy all regs to stack
260 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
262 VarArgsOffset = (Op.Val->getNumValues()-1) * 8;
263 std::vector<SDOperand> LS;
264 for (int i = 0; i < 6; ++i) {
265 if (MRegisterInfo::isPhysicalRegister(args_int[i]))
266 args_int[i] = AddLiveIn(MF, args_int[i], &Alpha::GPRCRegClass);
267 SDOperand argt = DAG.getCopyFromReg(Root, args_int[i], MVT::i64);
268 int FI = MFI->CreateFixedObject(8, -8 * (6 - i));
269 if (i == 0) VarArgsBase = FI;
270 SDOperand SDFI = DAG.getFrameIndex(FI, MVT::i64);
271 LS.push_back(DAG.getStore(Root, argt, SDFI, NULL, 0));
273 if (MRegisterInfo::isPhysicalRegister(args_float[i]))
274 args_float[i] = AddLiveIn(MF, args_float[i], &Alpha::F8RCRegClass);
275 argt = DAG.getCopyFromReg(Root, args_float[i], MVT::f64);
276 FI = MFI->CreateFixedObject(8, - 8 * (12 - i));
277 SDFI = DAG.getFrameIndex(FI, MVT::i64);
278 LS.push_back(DAG.getStore(Root, argt, SDFI, NULL, 0));
281 //Set up a token factor with all the stack traffic
282 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, &LS[0], LS.size());
285 ArgValues.push_back(Root);
287 // Return the new list of results.
288 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
289 Op.Val->value_end());
290 return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size());
293 static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
294 SDOperand Copy = DAG.getCopyToReg(Op.getOperand(0), Alpha::R26,
295 DAG.getNode(AlphaISD::GlobalRetAddr,
298 switch (Op.getNumOperands()) {
300 assert(0 && "Do not know how to return this many arguments!");
304 //return SDOperand(); // ret void is legal
306 MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
308 if (MVT::isInteger(ArgVT))
311 assert(MVT::isFloatingPoint(ArgVT));
314 Copy = DAG.getCopyToReg(Copy, ArgReg, Op.getOperand(1), Copy.getValue(1));
315 if (DAG.getMachineFunction().liveout_empty())
316 DAG.getMachineFunction().addLiveOut(ArgReg);
320 return DAG.getNode(AlphaISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
323 std::pair<SDOperand, SDOperand>
324 AlphaTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
325 bool RetTyIsSigned, bool isVarArg,
326 unsigned CallingConv, bool isTailCall,
327 SDOperand Callee, ArgListTy &Args,
331 NumBytes = (Args.size() - 6) * 8;
333 Chain = DAG.getCALLSEQ_START(Chain,
334 DAG.getConstant(NumBytes, getPointerTy()));
335 std::vector<SDOperand> args_to_use;
336 for (unsigned i = 0, e = Args.size(); i != e; ++i)
338 switch (getValueType(Args[i].Ty)) {
339 default: assert(0 && "Unexpected ValueType for argument!");
344 // Promote the integer to 64 bits. If the input type is signed use a
345 // sign extend, otherwise use a zero extend.
347 Args[i].Node = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64, Args[i].Node);
348 else if (Args[i].isZExt)
349 Args[i].Node = DAG.getNode(ISD::ZERO_EXTEND, MVT::i64, Args[i].Node);
351 Args[i].Node = DAG.getNode(ISD::ANY_EXTEND, MVT::i64, Args[i].Node);
358 args_to_use.push_back(Args[i].Node);
361 std::vector<MVT::ValueType> RetVals;
362 MVT::ValueType RetTyVT = getValueType(RetTy);
363 MVT::ValueType ActualRetTyVT = RetTyVT;
364 if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i32)
365 ActualRetTyVT = MVT::i64;
367 if (RetTyVT != MVT::isVoid)
368 RetVals.push_back(ActualRetTyVT);
369 RetVals.push_back(MVT::Other);
371 std::vector<SDOperand> Ops;
372 Ops.push_back(Chain);
373 Ops.push_back(Callee);
374 Ops.insert(Ops.end(), args_to_use.begin(), args_to_use.end());
375 SDOperand TheCall = DAG.getNode(AlphaISD::CALL, RetVals, &Ops[0], Ops.size());
376 Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
377 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
378 DAG.getConstant(NumBytes, getPointerTy()));
379 SDOperand RetVal = TheCall;
381 if (RetTyVT != ActualRetTyVT) {
382 RetVal = DAG.getNode(RetTyIsSigned ? ISD::AssertSext : ISD::AssertZext,
383 MVT::i64, RetVal, DAG.getValueType(RetTyVT));
384 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
387 return std::make_pair(RetVal, Chain);
390 /// LowerOperation - Provide custom lowering hooks for some operations.
392 SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
393 switch (Op.getOpcode()) {
394 default: assert(0 && "Wasn't expecting to be able to lower this!");
395 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG,
399 case ISD::RET: return LowerRET(Op,DAG);
400 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
402 case ISD::SINT_TO_FP: {
403 assert(MVT::i64 == Op.getOperand(0).getValueType() &&
404 "Unhandled SINT_TO_FP type in custom expander!");
406 bool isDouble = MVT::f64 == Op.getValueType();
407 LD = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0));
408 SDOperand FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_,
409 isDouble?MVT::f64:MVT::f32, LD);
412 case ISD::FP_TO_SINT: {
413 bool isDouble = MVT::f64 == Op.getOperand(0).getValueType();
414 SDOperand src = Op.getOperand(0);
416 if (!isDouble) //Promote
417 src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, src);
419 src = DAG.getNode(AlphaISD::CVTTQ_, MVT::f64, src);
421 return DAG.getNode(ISD::BIT_CONVERT, MVT::i64, src);
423 case ISD::ConstantPool: {
424 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
425 Constant *C = CP->getConstVal();
426 SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i64, CP->getAlignment());
428 SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, CPI,
429 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
430 SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, CPI, Hi);
433 case ISD::GlobalTLSAddress:
434 assert(0 && "TLS not implemented for Alpha.");
435 case ISD::GlobalAddress: {
436 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
437 GlobalValue *GV = GSDN->getGlobal();
438 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i64, GSDN->getOffset());
440 // if (!GV->hasWeakLinkage() && !GV->isDeclaration() && !GV->hasLinkOnceLinkage()) {
441 if (GV->hasInternalLinkage()) {
442 SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, GA,
443 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
444 SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, GA, Hi);
447 return DAG.getNode(AlphaISD::RelLit, MVT::i64, GA,
448 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
450 case ISD::ExternalSymbol: {
451 return DAG.getNode(AlphaISD::RelLit, MVT::i64,
452 DAG.getTargetExternalSymbol(cast<ExternalSymbolSDNode>(Op)
453 ->getSymbol(), MVT::i64),
454 DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
459 //Expand only on constant case
460 if (Op.getOperand(1).getOpcode() == ISD::Constant) {
461 MVT::ValueType VT = Op.Val->getValueType(0);
462 SDOperand Tmp1 = Op.Val->getOpcode() == ISD::UREM ?
463 BuildUDIV(Op.Val, DAG, NULL) :
464 BuildSDIV(Op.Val, DAG, NULL);
465 Tmp1 = DAG.getNode(ISD::MUL, VT, Tmp1, Op.getOperand(1));
466 Tmp1 = DAG.getNode(ISD::SUB, VT, Op.getOperand(0), Tmp1);
472 if (MVT::isInteger(Op.getValueType())) {
473 if (Op.getOperand(1).getOpcode() == ISD::Constant)
474 return Op.getOpcode() == ISD::SDIV ? BuildSDIV(Op.Val, DAG, NULL)
475 : BuildUDIV(Op.Val, DAG, NULL);
476 const char* opstr = 0;
477 switch (Op.getOpcode()) {
478 case ISD::UREM: opstr = "__remqu"; break;
479 case ISD::SREM: opstr = "__remq"; break;
480 case ISD::UDIV: opstr = "__divqu"; break;
481 case ISD::SDIV: opstr = "__divq"; break;
483 SDOperand Tmp1 = Op.getOperand(0),
484 Tmp2 = Op.getOperand(1),
485 Addr = DAG.getExternalSymbol(opstr, MVT::i64);
486 return DAG.getNode(AlphaISD::DivCall, MVT::i64, Addr, Tmp1, Tmp2);
491 SDOperand Chain = Op.getOperand(0);
492 SDOperand VAListP = Op.getOperand(1);
493 SrcValueSDNode *VAListS = cast<SrcValueSDNode>(Op.getOperand(2));
495 SDOperand Base = DAG.getLoad(MVT::i64, Chain, VAListP, VAListS->getValue(),
496 VAListS->getOffset());
497 SDOperand Tmp = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
498 DAG.getConstant(8, MVT::i64));
499 SDOperand Offset = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Base.getValue(1),
500 Tmp, NULL, 0, MVT::i32);
501 SDOperand DataPtr = DAG.getNode(ISD::ADD, MVT::i64, Base, Offset);
502 if (MVT::isFloatingPoint(Op.getValueType()))
504 //if fp && Offset < 6*8, then subtract 6*8 from DataPtr
505 SDOperand FPDataPtr = DAG.getNode(ISD::SUB, MVT::i64, DataPtr,
506 DAG.getConstant(8*6, MVT::i64));
507 SDOperand CC = DAG.getSetCC(MVT::i64, Offset,
508 DAG.getConstant(8*6, MVT::i64), ISD::SETLT);
509 DataPtr = DAG.getNode(ISD::SELECT, MVT::i64, CC, FPDataPtr, DataPtr);
512 SDOperand NewOffset = DAG.getNode(ISD::ADD, MVT::i64, Offset,
513 DAG.getConstant(8, MVT::i64));
514 SDOperand Update = DAG.getTruncStore(Offset.getValue(1), NewOffset,
515 Tmp, NULL, 0, MVT::i32);
518 if (Op.getValueType() == MVT::i32)
519 Result = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Update, DataPtr,
522 Result = DAG.getLoad(Op.getValueType(), Update, DataPtr, NULL, 0);
526 SDOperand Chain = Op.getOperand(0);
527 SDOperand DestP = Op.getOperand(1);
528 SDOperand SrcP = Op.getOperand(2);
529 SrcValueSDNode *DestS = cast<SrcValueSDNode>(Op.getOperand(3));
530 SrcValueSDNode *SrcS = cast<SrcValueSDNode>(Op.getOperand(4));
532 SDOperand Val = DAG.getLoad(getPointerTy(), Chain, SrcP,
533 SrcS->getValue(), SrcS->getOffset());
534 SDOperand Result = DAG.getStore(Val.getValue(1), Val, DestP, DestS->getValue(),
536 SDOperand NP = DAG.getNode(ISD::ADD, MVT::i64, SrcP,
537 DAG.getConstant(8, MVT::i64));
538 Val = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Result, NP, NULL,0, MVT::i32);
539 SDOperand NPD = DAG.getNode(ISD::ADD, MVT::i64, DestP,
540 DAG.getConstant(8, MVT::i64));
541 return DAG.getTruncStore(Val.getValue(1), Val, NPD, NULL, 0, MVT::i32);
544 SDOperand Chain = Op.getOperand(0);
545 SDOperand VAListP = Op.getOperand(1);
546 SrcValueSDNode *VAListS = cast<SrcValueSDNode>(Op.getOperand(2));
548 // vastart stores the address of the VarArgsBase and VarArgsOffset
549 SDOperand FR = DAG.getFrameIndex(VarArgsBase, MVT::i64);
550 SDOperand S1 = DAG.getStore(Chain, FR, VAListP, VAListS->getValue(),
551 VAListS->getOffset());
552 SDOperand SA2 = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
553 DAG.getConstant(8, MVT::i64));
554 return DAG.getTruncStore(S1, DAG.getConstant(VarArgsOffset, MVT::i64),
555 SA2, NULL, 0, MVT::i32);
557 case ISD::RETURNADDR:
558 return DAG.getNode(AlphaISD::GlobalRetAddr, MVT::i64);
560 case ISD::FRAMEADDR: break;
566 SDOperand AlphaTargetLowering::CustomPromoteOperation(SDOperand Op,
568 assert(Op.getValueType() == MVT::i32 &&
569 Op.getOpcode() == ISD::VAARG &&
570 "Unknown node to custom promote!");
572 // The code in LowerOperation already handles i32 vaarg
573 return LowerOperation(Op, DAG);
579 /// getConstraintType - Given a constraint letter, return the type of
580 /// constraint it is for this target.
581 AlphaTargetLowering::ConstraintType
582 AlphaTargetLowering::getConstraintType(const std::string &Constraint) const {
583 if (Constraint.size() == 1) {
584 switch (Constraint[0]) {
588 return C_RegisterClass;
591 return TargetLowering::getConstraintType(Constraint);
594 std::vector<unsigned> AlphaTargetLowering::
595 getRegClassForInlineAsmConstraint(const std::string &Constraint,
596 MVT::ValueType VT) const {
597 if (Constraint.size() == 1) {
598 switch (Constraint[0]) {
599 default: break; // Unknown constriant letter
601 return make_vector<unsigned>(Alpha::F0 , Alpha::F1 , Alpha::F2 ,
602 Alpha::F3 , Alpha::F4 , Alpha::F5 ,
603 Alpha::F6 , Alpha::F7 , Alpha::F8 ,
604 Alpha::F9 , Alpha::F10, Alpha::F11,
605 Alpha::F12, Alpha::F13, Alpha::F14,
606 Alpha::F15, Alpha::F16, Alpha::F17,
607 Alpha::F18, Alpha::F19, Alpha::F20,
608 Alpha::F21, Alpha::F22, Alpha::F23,
609 Alpha::F24, Alpha::F25, Alpha::F26,
610 Alpha::F27, Alpha::F28, Alpha::F29,
611 Alpha::F30, Alpha::F31, 0);
613 return make_vector<unsigned>(Alpha::R0 , Alpha::R1 , Alpha::R2 ,
614 Alpha::R3 , Alpha::R4 , Alpha::R5 ,
615 Alpha::R6 , Alpha::R7 , Alpha::R8 ,
616 Alpha::R9 , Alpha::R10, Alpha::R11,
617 Alpha::R12, Alpha::R13, Alpha::R14,
618 Alpha::R15, Alpha::R16, Alpha::R17,
619 Alpha::R18, Alpha::R19, Alpha::R20,
620 Alpha::R21, Alpha::R22, Alpha::R23,
621 Alpha::R24, Alpha::R25, Alpha::R26,
622 Alpha::R27, Alpha::R28, Alpha::R29,
623 Alpha::R30, Alpha::R31, 0);
627 return std::vector<unsigned>();