1 //===-- AlphaISelLowering.cpp - Alpha DAG Lowering Implementation ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Andrew Lenharth and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AlphaISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "AlphaISelLowering.h"
15 #include "AlphaTargetMachine.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/CodeGen/SSARegMap.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/Support/CommandLine.h"
29 extern cl::opt<bool> EnableAlphaIDIV;
30 extern cl::opt<bool> EnableAlphaCount;
31 extern cl::opt<bool> EnableAlphaLSMark;
34 /// AddLiveIn - This helper function adds the specified physical register to the
35 /// MachineFunction as a live in value. It also creates a corresponding virtual
37 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
38 TargetRegisterClass *RC) {
39 assert(RC->contains(PReg) && "Not the correct regclass!");
40 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
41 MF.addLiveIn(PReg, VReg);
45 AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM) {
46 // Set up the TargetLowering object.
47 //I am having problems with shr n ubyte 1
48 setShiftAmountType(MVT::i64);
49 setSetCCResultType(MVT::i64);
50 setSetCCResultContents(ZeroOrOneSetCCResult);
52 addRegisterClass(MVT::i64, Alpha::GPRCRegisterClass);
53 addRegisterClass(MVT::f64, Alpha::F8RCRegisterClass);
54 addRegisterClass(MVT::f32, Alpha::F4RCRegisterClass);
56 setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
57 setOperationAction(ISD::BRTWOWAY_CC, MVT::Other, Expand);
59 setOperationAction(ISD::EXTLOAD, MVT::i1, Promote);
60 setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
62 setOperationAction(ISD::ZEXTLOAD, MVT::i1, Promote);
63 setOperationAction(ISD::ZEXTLOAD, MVT::i32, Expand);
65 setOperationAction(ISD::SEXTLOAD, MVT::i1, Promote);
66 setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
67 setOperationAction(ISD::SEXTLOAD, MVT::i16, Expand);
69 setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote);
71 setOperationAction(ISD::FREM, MVT::f32, Expand);
72 setOperationAction(ISD::FREM, MVT::f64, Expand);
74 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
75 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
76 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
77 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
79 if (!TM.getSubtarget<AlphaSubtarget>().hasCT()) {
80 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
81 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
82 setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
85 //If this didn't legalize into a div....
86 // setOperationAction(ISD::SREM , MVT::i64, Expand);
87 // setOperationAction(ISD::UREM , MVT::i64, Expand);
89 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
90 setOperationAction(ISD::MEMSET , MVT::Other, Expand);
91 setOperationAction(ISD::MEMCPY , MVT::Other, Expand);
93 // We don't support sin/cos/sqrt
94 setOperationAction(ISD::FSIN , MVT::f64, Expand);
95 setOperationAction(ISD::FCOS , MVT::f64, Expand);
96 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
97 setOperationAction(ISD::FSIN , MVT::f32, Expand);
98 setOperationAction(ISD::FCOS , MVT::f32, Expand);
99 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
101 setOperationAction(ISD::SETCC, MVT::f32, Promote);
103 // We don't have line number support yet.
104 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
105 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
107 addLegalFPImmediate(+0.0); //F31
108 addLegalFPImmediate(-0.0); //-F31
110 computeRegisterProperties();
112 useITOF = TM.getSubtarget<AlphaSubtarget>().hasF2I();
116 //http://www.cs.arizona.edu/computer.help/policy/DIGITAL_unix/AA-PY8AC-TET1_html/callCH3.html#BLOCK21
118 //For now, just use variable size stack frame format
120 //In a standard call, the first six items are passed in registers $16
121 //- $21 and/or registers $f16 - $f21. (See Section 4.1.2 for details
122 //of argument-to-register correspondence.) The remaining items are
123 //collected in a memory argument list that is a naturally aligned
124 //array of quadwords. In a standard call, this list, if present, must
125 //be passed at 0(SP).
126 //7 ... n 0(SP) ... (n-7)*8(SP)
134 std::vector<SDOperand>
135 AlphaTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG)
137 MachineFunction &MF = DAG.getMachineFunction();
138 MachineFrameInfo *MFI = MF.getFrameInfo();
139 MachineBasicBlock& BB = MF.front();
140 std::vector<SDOperand> ArgValues;
142 unsigned args_int[] = {
143 Alpha::R16, Alpha::R17, Alpha::R18, Alpha::R19, Alpha::R20, Alpha::R21};
144 unsigned args_float[] = {
145 Alpha::F16, Alpha::F17, Alpha::F18, Alpha::F19, Alpha::F20, Alpha::F21};
149 GP = AddLiveIn(MF, Alpha::R29, getRegClassFor(MVT::i64));
150 RA = AddLiveIn(MF, Alpha::R26, getRegClassFor(MVT::i64));
152 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I)
157 MVT::ValueType VT = getValueType(I->getType());
160 std::cerr << "Unknown Type " << VT << "\n";
164 args_float[count] = AddLiveIn(MF, args_float[count], getRegClassFor(VT));
165 argt = DAG.getCopyFromReg(DAG.getRoot(), args_float[count], VT);
166 DAG.setRoot(argt.getValue(1));
173 args_int[count] = AddLiveIn(MF, args_int[count], getRegClassFor(MVT::i64));
174 argt = DAG.getCopyFromReg(DAG.getRoot(), args_int[count], MVT::i64);
175 DAG.setRoot(argt.getValue(1));
176 if (VT != MVT::i64) {
178 I->getType()->isSigned() ? ISD::AssertSext : ISD::AssertZext;
179 argt = DAG.getNode(AssertOp, MVT::i64, argt,
180 DAG.getValueType(VT));
181 argt = DAG.getNode(ISD::TRUNCATE, VT, argt);
186 // Create the frame index object for this incoming parameter...
187 int FI = MFI->CreateFixedObject(8, 8 * (count - 6));
189 // Create the SelectionDAG nodes corresponding to a load
190 //from this parameter
191 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
192 argt = DAG.getLoad(getValueType(I->getType()),
193 DAG.getEntryNode(), FIN, DAG.getSrcValue(NULL));
196 ArgValues.push_back(argt);
199 // If the functions takes variable number of arguments, copy all regs to stack
201 VarArgsOffset = count * 8;
202 std::vector<SDOperand> LS;
203 for (int i = 0; i < 6; ++i) {
204 if (MRegisterInfo::isPhysicalRegister(args_int[i]))
205 args_int[i] = AddLiveIn(MF, args_int[i], getRegClassFor(MVT::i64));
206 SDOperand argt = DAG.getCopyFromReg(DAG.getRoot(), args_int[i], MVT::i64);
207 int FI = MFI->CreateFixedObject(8, -8 * (6 - i));
208 if (i == 0) VarArgsBase = FI;
209 SDOperand SDFI = DAG.getFrameIndex(FI, MVT::i64);
210 LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), argt,
211 SDFI, DAG.getSrcValue(NULL)));
213 if (MRegisterInfo::isPhysicalRegister(args_float[i]))
214 args_float[i] = AddLiveIn(MF, args_float[i], getRegClassFor(MVT::f64));
215 argt = DAG.getCopyFromReg(DAG.getRoot(), args_float[i], MVT::f64);
216 FI = MFI->CreateFixedObject(8, - 8 * (12 - i));
217 SDFI = DAG.getFrameIndex(FI, MVT::i64);
218 LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), argt,
219 SDFI, DAG.getSrcValue(NULL)));
222 //Set up a token factor with all the stack traffic
223 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, LS));
226 // Finally, inform the code generator which regs we return values in.
227 switch (getValueType(F.getReturnType())) {
228 default: assert(0 && "Unknown type!");
229 case MVT::isVoid: break;
235 MF.addLiveOut(Alpha::R0);
239 MF.addLiveOut(Alpha::F0);
243 //return the arguments
247 std::pair<SDOperand, SDOperand>
248 AlphaTargetLowering::LowerCallTo(SDOperand Chain,
249 const Type *RetTy, bool isVarArg,
250 unsigned CallingConv, bool isTailCall,
251 SDOperand Callee, ArgListTy &Args,
255 NumBytes = (Args.size() - 6) * 8;
257 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
258 DAG.getConstant(NumBytes, getPointerTy()));
259 std::vector<SDOperand> args_to_use;
260 for (unsigned i = 0, e = Args.size(); i != e; ++i)
262 switch (getValueType(Args[i].second)) {
263 default: assert(0 && "Unexpected ValueType for argument!");
268 // Promote the integer to 64 bits. If the input type is signed use a
269 // sign extend, otherwise use a zero extend.
270 if (Args[i].second->isSigned())
271 Args[i].first = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64, Args[i].first);
273 Args[i].first = DAG.getNode(ISD::ZERO_EXTEND, MVT::i64, Args[i].first);
280 args_to_use.push_back(Args[i].first);
283 std::vector<MVT::ValueType> RetVals;
284 MVT::ValueType RetTyVT = getValueType(RetTy);
285 MVT::ValueType ActualRetTyVT = RetTyVT;
286 if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i32)
287 ActualRetTyVT = MVT::i64;
289 if (RetTyVT != MVT::isVoid)
290 RetVals.push_back(ActualRetTyVT);
291 RetVals.push_back(MVT::Other);
293 SDOperand TheCall = SDOperand(DAG.getCall(RetVals,
294 Chain, Callee, args_to_use), 0);
295 Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
296 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
297 DAG.getConstant(NumBytes, getPointerTy()));
298 SDOperand RetVal = TheCall;
300 if (RetTyVT != ActualRetTyVT) {
301 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext : ISD::AssertZext,
302 MVT::i64, RetVal, DAG.getValueType(RetTyVT));
303 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
306 return std::make_pair(RetVal, Chain);
309 SDOperand AlphaTargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
310 Value *VAListV, SelectionDAG &DAG) {
311 // vastart stores the address of the VarArgsBase and VarArgsOffset
312 SDOperand FR = DAG.getFrameIndex(VarArgsBase, MVT::i64);
313 SDOperand S1 = DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP,
314 DAG.getSrcValue(VAListV));
315 SDOperand SA2 = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
316 DAG.getConstant(8, MVT::i64));
317 return DAG.getNode(ISD::TRUNCSTORE, MVT::Other, S1,
318 DAG.getConstant(VarArgsOffset, MVT::i64), SA2,
319 DAG.getSrcValue(VAListV, 8), DAG.getValueType(MVT::i32));
322 std::pair<SDOperand,SDOperand> AlphaTargetLowering::
323 LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
324 const Type *ArgTy, SelectionDAG &DAG) {
325 SDOperand Base = DAG.getLoad(MVT::i64, Chain, VAListP,
326 DAG.getSrcValue(VAListV));
327 SDOperand Tmp = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
328 DAG.getConstant(8, MVT::i64));
329 SDOperand Offset = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Base.getValue(1),
330 Tmp, DAG.getSrcValue(VAListV, 8), MVT::i32);
331 SDOperand DataPtr = DAG.getNode(ISD::ADD, MVT::i64, Base, Offset);
332 if (ArgTy->isFloatingPoint())
334 //if fp && Offset < 6*8, then subtract 6*8 from DataPtr
335 SDOperand FPDataPtr = DAG.getNode(ISD::SUB, MVT::i64, DataPtr,
336 DAG.getConstant(8*6, MVT::i64));
337 SDOperand CC = DAG.getSetCC(MVT::i64, Offset,
338 DAG.getConstant(8*6, MVT::i64), ISD::SETLT);
339 DataPtr = DAG.getNode(ISD::SELECT, MVT::i64, CC, FPDataPtr, DataPtr);
343 if (ArgTy == Type::IntTy)
344 Result = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Offset.getValue(1),
345 DataPtr, DAG.getSrcValue(NULL), MVT::i32);
346 else if (ArgTy == Type::UIntTy)
347 Result = DAG.getExtLoad(ISD::ZEXTLOAD, MVT::i64, Offset.getValue(1),
348 DataPtr, DAG.getSrcValue(NULL), MVT::i32);
350 Result = DAG.getLoad(getValueType(ArgTy), Offset.getValue(1), DataPtr,
351 DAG.getSrcValue(NULL));
353 SDOperand NewOffset = DAG.getNode(ISD::ADD, MVT::i64, Offset,
354 DAG.getConstant(8, MVT::i64));
355 SDOperand Update = DAG.getNode(ISD::TRUNCSTORE, MVT::Other,
356 Result.getValue(1), NewOffset,
357 Tmp, DAG.getSrcValue(VAListV, 8),
358 DAG.getValueType(MVT::i32));
359 Result = DAG.getNode(ISD::TRUNCATE, getValueType(ArgTy), Result);
361 return std::make_pair(Result, Update);
365 SDOperand AlphaTargetLowering::
366 LowerVACopy(SDOperand Chain, SDOperand SrcP, Value *SrcV, SDOperand DestP,
367 Value *DestV, SelectionDAG &DAG) {
368 SDOperand Val = DAG.getLoad(getPointerTy(), Chain, SrcP,
369 DAG.getSrcValue(SrcV));
370 SDOperand Result = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
371 Val, DestP, DAG.getSrcValue(DestV));
372 SDOperand NP = DAG.getNode(ISD::ADD, MVT::i64, SrcP,
373 DAG.getConstant(8, MVT::i64));
374 Val = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Result, NP,
375 DAG.getSrcValue(SrcV, 8), MVT::i32);
376 SDOperand NPD = DAG.getNode(ISD::ADD, MVT::i64, DestP,
377 DAG.getConstant(8, MVT::i64));
378 return DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Val.getValue(1),
379 Val, NPD, DAG.getSrcValue(DestV, 8),
380 DAG.getValueType(MVT::i32));
383 void AlphaTargetLowering::restoreGP(MachineBasicBlock* BB)
385 BuildMI(BB, Alpha::BIS, 2, Alpha::R29).addReg(GP).addReg(GP);
387 void AlphaTargetLowering::restoreRA(MachineBasicBlock* BB)
389 BuildMI(BB, Alpha::BIS, 2, Alpha::R26).addReg(RA).addReg(RA);
393 /// LowerOperation - Provide custom lowering hooks for some operations.
395 SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
396 switch (Op.getOpcode()) {
397 default: assert(0 && "Wasn't expecting to be able to lower this!");
398 case ISD::SINT_TO_FP: {
399 assert(MVT::i64 == Op.getOperand(0).getValueType() &&
400 "Unhandled SINT_TO_FP type in custom expander!");
402 bool isDouble = MVT::f64 == Op.getValueType();
404 LD = DAG.getNode(AlphaISD::ITOFT_, MVT::f64, Op.getOperand(0));
407 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
408 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i64);
409 SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
410 Op.getOperand(0), FI, DAG.getSrcValue(0));
411 LD = DAG.getLoad(MVT::f64, ST, FI, DAG.getSrcValue(0));
413 SDOperand FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_,
414 isDouble?MVT::f64:MVT::f32, LD);
417 case ISD::FP_TO_SINT: {
418 bool isDouble = MVT::f64 == Op.getOperand(0).getValueType();
419 SDOperand src = Op.getOperand(0);
421 if (!isDouble) //Promote
422 src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, src);
424 src = DAG.getNode(AlphaISD::CVTTQ_, MVT::f64, src);
427 return DAG.getNode(AlphaISD::FTOIT_, MVT::i64, src);
430 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
431 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i64);
432 SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
433 src, FI, DAG.getSrcValue(0));
434 return DAG.getLoad(MVT::i64, ST, FI, DAG.getSrcValue(0));