1 //===-- AlphaISelDAGToDAG.cpp - Alpha pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for Alpha,
11 // converting from a legalized dag to a Alpha dag.
13 //===----------------------------------------------------------------------===//
16 #include "AlphaTargetMachine.h"
17 #include "AlphaISelLowering.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SelectionDAGISel.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/Constants.h"
26 #include "llvm/DerivedTypes.h"
27 #include "llvm/GlobalValue.h"
28 #include "llvm/Intrinsics.h"
29 #include "llvm/Support/Compiler.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/MathExtras.h"
33 #include "llvm/Support/raw_ostream.h"
39 //===--------------------------------------------------------------------===//
40 /// AlphaDAGToDAGISel - Alpha specific code to select Alpha machine
41 /// instructions for SelectionDAG operations.
42 class AlphaDAGToDAGISel : public SelectionDAGISel {
43 static const int64_t IMM_LOW = -32768;
44 static const int64_t IMM_HIGH = 32767;
45 static const int64_t IMM_MULT = 65536;
46 static const int64_t IMM_FULLHIGH = IMM_HIGH + IMM_HIGH * IMM_MULT;
47 static const int64_t IMM_FULLLOW = IMM_LOW + IMM_LOW * IMM_MULT;
49 static int64_t get_ldah16(int64_t x) {
50 int64_t y = x / IMM_MULT;
51 if (x % IMM_MULT > IMM_HIGH)
56 static int64_t get_lda16(int64_t x) {
57 return x - get_ldah16(x) * IMM_MULT;
60 /// get_zapImm - Return a zap mask if X is a valid immediate for a zapnot
61 /// instruction (if not, return 0). Note that this code accepts partial
62 /// zap masks. For example (and LHS, 1) is a valid zap, as long we know
63 /// that the bits 1-7 of LHS are already zero. If LHS is non-null, we are
64 /// in checking mode. If LHS is null, we assume that the mask has already
65 /// been validated before.
66 uint64_t get_zapImm(SDValue LHS, uint64_t Constant) {
67 uint64_t BitsToCheck = 0;
69 for (unsigned i = 0; i != 8; ++i) {
70 if (((Constant >> 8*i) & 0xFF) == 0) {
74 if (((Constant >> 8*i) & 0xFF) == 0xFF) {
75 // If the entire byte is set, zapnot the byte.
76 } else if (LHS.getNode() == 0) {
77 // Otherwise, if the mask was previously validated, we know its okay
78 // to zapnot this entire byte even though all the bits aren't set.
80 // Otherwise we don't know that the it's okay to zapnot this entire
81 // byte. Only do this iff we can prove that the missing bits are
82 // already null, so the bytezap doesn't need to really null them.
83 BitsToCheck |= ~Constant & (0xFF << 8*i);
88 // If there are missing bits in a byte (for example, X & 0xEF00), check to
89 // see if the missing bits (0x1000) are already known zero if not, the zap
90 // isn't okay to do, as it won't clear all the required bits.
92 !CurDAG->MaskedValueIsZero(LHS,
93 APInt(LHS.getValueSizeInBits(),
100 static uint64_t get_zapImm(uint64_t x) {
102 for(int i = 0; i != 8; ++i) {
103 if ((x & 0x00FF) == 0x00FF)
105 else if ((x & 0x00FF) != 0)
113 static uint64_t getNearPower2(uint64_t x) {
115 unsigned at = CountLeadingZeros_64(x);
116 uint64_t complow = 1 << (63 - at);
117 uint64_t comphigh = 1 << (64 - at);
118 //cerr << x << ":" << complow << ":" << comphigh << "\n";
119 if (abs(complow - x) <= abs(comphigh - x))
125 static bool chkRemNearPower2(uint64_t x, uint64_t r, bool swap) {
126 uint64_t y = getNearPower2(x);
133 static bool isFPZ(SDValue N) {
134 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
135 return (CN && (CN->getValueAPF().isZero()));
137 static bool isFPZn(SDValue N) {
138 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
139 return (CN && CN->getValueAPF().isNegZero());
141 static bool isFPZp(SDValue N) {
142 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
143 return (CN && CN->getValueAPF().isPosZero());
147 explicit AlphaDAGToDAGISel(AlphaTargetMachine &TM)
148 : SelectionDAGISel(TM)
151 /// getI64Imm - Return a target constant with the specified value, of type
153 inline SDValue getI64Imm(int64_t Imm) {
154 return CurDAG->getTargetConstant(Imm, MVT::i64);
157 // Select - Convert the specified operand from a target-independent to a
158 // target-specific node if it hasn't already been changed.
159 SDNode *Select(SDValue Op);
161 /// InstructionSelect - This callback is invoked by
162 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
163 virtual void InstructionSelect();
165 virtual const char *getPassName() const {
166 return "Alpha DAG->DAG Pattern Instruction Selection";
169 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
170 /// inline asm expressions.
171 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
173 std::vector<SDValue> &OutOps) {
175 switch (ConstraintCode) {
176 default: return true;
182 OutOps.push_back(Op0);
186 // Include the pieces autogenerated from the target description.
187 #include "AlphaGenDAGISel.inc"
190 /// getTargetMachine - Return a reference to the TargetMachine, casted
191 /// to the target-specific type.
192 const AlphaTargetMachine &getTargetMachine() {
193 return static_cast<const AlphaTargetMachine &>(TM);
196 /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
197 /// to the target-specific type.
198 const AlphaInstrInfo *getInstrInfo() {
199 return getTargetMachine().getInstrInfo();
202 SDNode *getGlobalBaseReg();
203 SDNode *getGlobalRetAddr();
204 void SelectCALL(SDValue Op);
209 /// getGlobalBaseReg - Output the instructions required to put the
210 /// GOT address into a register.
212 SDNode *AlphaDAGToDAGISel::getGlobalBaseReg() {
213 MachineFunction *MF = BB->getParent();
214 unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
215 return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
218 /// getGlobalRetAddr - Grab the return address.
220 SDNode *AlphaDAGToDAGISel::getGlobalRetAddr() {
221 MachineFunction *MF = BB->getParent();
222 unsigned GlobalRetAddr = getInstrInfo()->getGlobalRetAddr(MF);
223 return CurDAG->getRegister(GlobalRetAddr, TLI.getPointerTy()).getNode();
226 /// InstructionSelect - This callback is invoked by
227 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
228 void AlphaDAGToDAGISel::InstructionSelect() {
231 // Select target instructions for the DAG.
233 CurDAG->RemoveDeadNodes();
236 // Select - Convert the specified operand from a target-independent to a
237 // target-specific node if it hasn't already been changed.
238 SDNode *AlphaDAGToDAGISel::Select(SDValue Op) {
239 SDNode *N = Op.getNode();
240 if (N->isMachineOpcode()) {
241 return NULL; // Already selected.
243 DebugLoc dl = N->getDebugLoc();
245 switch (N->getOpcode()) {
251 case ISD::FrameIndex: {
252 int FI = cast<FrameIndexSDNode>(N)->getIndex();
253 return CurDAG->SelectNodeTo(N, Alpha::LDA, MVT::i64,
254 CurDAG->getTargetFrameIndex(FI, MVT::i32),
257 case ISD::GLOBAL_OFFSET_TABLE:
258 return getGlobalBaseReg();
259 case AlphaISD::GlobalRetAddr:
260 return getGlobalRetAddr();
262 case AlphaISD::DivCall: {
263 SDValue Chain = CurDAG->getEntryNode();
264 SDValue N0 = Op.getOperand(0);
265 SDValue N1 = Op.getOperand(1);
266 SDValue N2 = Op.getOperand(2);
267 Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R24, N1,
269 Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R25, N2,
271 Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R27, N0,
274 CurDAG->getTargetNode(Alpha::JSRs, dl, MVT::Other, MVT::Flag,
275 Chain, Chain.getValue(1));
276 Chain = CurDAG->getCopyFromReg(Chain, dl, Alpha::R27, MVT::i64,
278 return CurDAG->SelectNodeTo(N, Alpha::BISr, MVT::i64, Chain, Chain);
281 case ISD::READCYCLECOUNTER: {
282 SDValue Chain = N->getOperand(0);
283 return CurDAG->getTargetNode(Alpha::RPCC, dl, MVT::i64, MVT::Other,
287 case ISD::Constant: {
288 uint64_t uval = cast<ConstantSDNode>(N)->getZExtValue();
291 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
292 Alpha::R31, MVT::i64);
293 ReplaceUses(Op, Result);
297 int64_t val = (int64_t)uval;
298 int32_t val32 = (int32_t)val;
299 if (val <= IMM_HIGH + IMM_HIGH * IMM_MULT &&
300 val >= IMM_LOW + IMM_LOW * IMM_MULT)
301 break; //(LDAH (LDA))
302 if ((uval >> 32) == 0 && //empty upper bits
303 val32 <= IMM_HIGH + IMM_HIGH * IMM_MULT)
304 // val32 >= IMM_LOW + IMM_LOW * IMM_MULT) //always true
305 break; //(zext (LDAH (LDA)))
306 //Else use the constant pool
307 ConstantInt *C = ConstantInt::get(Type::Int64Ty, uval);
308 SDValue CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
309 SDNode *Tmp = CurDAG->getTargetNode(Alpha::LDAHr, dl, MVT::i64, CPI,
310 SDValue(getGlobalBaseReg(), 0));
311 return CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, MVT::Other,
312 CPI, SDValue(Tmp, 0), CurDAG->getEntryNode());
314 case ISD::TargetConstantFP:
315 case ISD::ConstantFP: {
316 ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);
317 bool isDouble = N->getValueType(0) == MVT::f64;
318 MVT T = isDouble ? MVT::f64 : MVT::f32;
319 if (CN->getValueAPF().isPosZero()) {
320 return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYST : Alpha::CPYSS,
321 T, CurDAG->getRegister(Alpha::F31, T),
322 CurDAG->getRegister(Alpha::F31, T));
323 } else if (CN->getValueAPF().isNegZero()) {
324 return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYSNT : Alpha::CPYSNS,
325 T, CurDAG->getRegister(Alpha::F31, T),
326 CurDAG->getRegister(Alpha::F31, T));
328 llvm_report_error("Unhandled FP constant type");
334 if (N->getOperand(0).getNode()->getValueType(0).isFloatingPoint()) {
335 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
337 unsigned Opc = Alpha::WTF;
341 default: DEBUG(N->dump(CurDAG)); assert(0 && "Unknown FP comparison!");
342 case ISD::SETEQ: case ISD::SETOEQ: case ISD::SETUEQ:
343 Opc = Alpha::CMPTEQ; break;
344 case ISD::SETLT: case ISD::SETOLT: case ISD::SETULT:
345 Opc = Alpha::CMPTLT; break;
346 case ISD::SETLE: case ISD::SETOLE: case ISD::SETULE:
347 Opc = Alpha::CMPTLE; break;
348 case ISD::SETGT: case ISD::SETOGT: case ISD::SETUGT:
349 Opc = Alpha::CMPTLT; rev = true; break;
350 case ISD::SETGE: case ISD::SETOGE: case ISD::SETUGE:
351 Opc = Alpha::CMPTLE; rev = true; break;
352 case ISD::SETNE: case ISD::SETONE: case ISD::SETUNE:
353 Opc = Alpha::CMPTEQ; inv = true; break;
355 Opc = Alpha::CMPTUN; inv = true; break;
357 Opc = Alpha::CMPTUN; break;
359 SDValue tmp1 = N->getOperand(rev?1:0);
360 SDValue tmp2 = N->getOperand(rev?0:1);
361 SDNode *cmp = CurDAG->getTargetNode(Opc, dl, MVT::f64, tmp1, tmp2);
363 cmp = CurDAG->getTargetNode(Alpha::CMPTEQ, dl,
364 MVT::f64, SDValue(cmp, 0),
365 CurDAG->getRegister(Alpha::F31, MVT::f64));
367 case ISD::SETUEQ: case ISD::SETULT: case ISD::SETULE:
368 case ISD::SETUNE: case ISD::SETUGT: case ISD::SETUGE:
370 SDNode* cmp2 = CurDAG->getTargetNode(Alpha::CMPTUN, dl, MVT::f64,
372 cmp = CurDAG->getTargetNode(Alpha::ADDT, dl, MVT::f64,
373 SDValue(cmp2, 0), SDValue(cmp, 0));
379 SDNode* LD = CurDAG->getTargetNode(Alpha::FTOIT, dl,
380 MVT::i64, SDValue(cmp, 0));
381 return CurDAG->getTargetNode(Alpha::CMPULT, dl, MVT::i64,
382 CurDAG->getRegister(Alpha::R31, MVT::i64),
388 if (N->getValueType(0).isFloatingPoint() &&
389 (N->getOperand(0).getOpcode() != ISD::SETCC ||
390 !N->getOperand(0).getOperand(1).getValueType().isFloatingPoint())) {
391 //This should be the condition not covered by the Patterns
392 //FIXME: Don't have SelectCode die, but rather return something testable
393 // so that things like this can be caught in fall though code
395 bool isDouble = N->getValueType(0) == MVT::f64;
396 SDValue cond = N->getOperand(0);
397 SDValue TV = N->getOperand(1);
398 SDValue FV = N->getOperand(2);
400 SDNode* LD = CurDAG->getTargetNode(Alpha::ITOFT, dl, MVT::f64, cond);
401 return CurDAG->getTargetNode(isDouble?Alpha::FCMOVNET:Alpha::FCMOVNES,
402 dl, MVT::f64, FV, TV, SDValue(LD,0));
407 ConstantSDNode* SC = NULL;
408 ConstantSDNode* MC = NULL;
409 if (N->getOperand(0).getOpcode() == ISD::SRL &&
410 (MC = dyn_cast<ConstantSDNode>(N->getOperand(1))) &&
411 (SC = dyn_cast<ConstantSDNode>(N->getOperand(0).getOperand(1)))) {
412 uint64_t sval = SC->getZExtValue();
413 uint64_t mval = MC->getZExtValue();
414 // If the result is a zap, let the autogened stuff handle it.
415 if (get_zapImm(N->getOperand(0), mval))
417 // given mask X, and shift S, we want to see if there is any zap in the
418 // mask if we play around with the botton S bits
419 uint64_t dontcare = (~0ULL) >> (64 - sval);
420 uint64_t mask = mval << sval;
422 if (get_zapImm(mask | dontcare))
423 mask = mask | dontcare;
425 if (get_zapImm(mask)) {
427 SDValue(CurDAG->getTargetNode(Alpha::ZAPNOTi, dl, MVT::i64,
428 N->getOperand(0).getOperand(0),
429 getI64Imm(get_zapImm(mask))), 0);
430 return CurDAG->getTargetNode(Alpha::SRLr, dl, MVT::i64, Z,
439 return SelectCode(Op);
442 void AlphaDAGToDAGISel::SelectCALL(SDValue Op) {
443 //TODO: add flag stuff to prevent nondeturministic breakage!
445 SDNode *N = Op.getNode();
446 SDValue Chain = N->getOperand(0);
447 SDValue Addr = N->getOperand(1);
448 SDValue InFlag(0,0); // Null incoming flag value.
449 DebugLoc dl = N->getDebugLoc();
451 std::vector<SDValue> CallOperands;
452 std::vector<MVT> TypeOperands;
455 for(int i = 2, e = N->getNumOperands(); i < e; ++i) {
456 TypeOperands.push_back(N->getOperand(i).getValueType());
457 CallOperands.push_back(N->getOperand(i));
459 int count = N->getNumOperands() - 2;
461 static const unsigned args_int[] = {Alpha::R16, Alpha::R17, Alpha::R18,
462 Alpha::R19, Alpha::R20, Alpha::R21};
463 static const unsigned args_float[] = {Alpha::F16, Alpha::F17, Alpha::F18,
464 Alpha::F19, Alpha::F20, Alpha::F21};
466 for (int i = 6; i < count; ++i) {
467 unsigned Opc = Alpha::WTF;
468 if (TypeOperands[i].isInteger()) {
470 } else if (TypeOperands[i] == MVT::f32) {
472 } else if (TypeOperands[i] == MVT::f64) {
475 assert(0 && "Unknown operand");
477 SDValue Ops[] = { CallOperands[i], getI64Imm((i - 6) * 8),
478 CurDAG->getCopyFromReg(Chain, dl, Alpha::R30, MVT::i64),
480 Chain = SDValue(CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 4), 0);
482 for (int i = 0; i < std::min(6, count); ++i) {
483 if (TypeOperands[i].isInteger()) {
484 Chain = CurDAG->getCopyToReg(Chain, dl, args_int[i],
485 CallOperands[i], InFlag);
486 InFlag = Chain.getValue(1);
487 } else if (TypeOperands[i] == MVT::f32 || TypeOperands[i] == MVT::f64) {
488 Chain = CurDAG->getCopyToReg(Chain, dl, args_float[i],
489 CallOperands[i], InFlag);
490 InFlag = Chain.getValue(1);
492 assert(0 && "Unknown operand");
495 // Finally, once everything is in registers to pass to the call, emit the
497 if (Addr.getOpcode() == AlphaISD::GPRelLo) {
498 SDValue GOT = SDValue(getGlobalBaseReg(), 0);
499 Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R29, GOT, InFlag);
500 InFlag = Chain.getValue(1);
501 Chain = SDValue(CurDAG->getTargetNode(Alpha::BSR, dl, MVT::Other,
502 MVT::Flag, Addr.getOperand(0),
505 Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R27, Addr, InFlag);
506 InFlag = Chain.getValue(1);
507 Chain = SDValue(CurDAG->getTargetNode(Alpha::JSR, dl, MVT::Other,
508 MVT::Flag, Chain, InFlag), 0);
510 InFlag = Chain.getValue(1);
512 std::vector<SDValue> CallResults;
514 switch (N->getValueType(0).getSimpleVT()) {
515 default: assert(0 && "Unexpected ret value!");
516 case MVT::Other: break;
518 Chain = CurDAG->getCopyFromReg(Chain, dl,
519 Alpha::R0, MVT::i64, InFlag).getValue(1);
520 CallResults.push_back(Chain.getValue(0));
523 Chain = CurDAG->getCopyFromReg(Chain, dl,
524 Alpha::F0, MVT::f32, InFlag).getValue(1);
525 CallResults.push_back(Chain.getValue(0));
528 Chain = CurDAG->getCopyFromReg(Chain, dl,
529 Alpha::F0, MVT::f64, InFlag).getValue(1);
530 CallResults.push_back(Chain.getValue(0));
534 CallResults.push_back(Chain);
535 for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
536 ReplaceUses(Op.getValue(i), CallResults[i]);
540 /// createAlphaISelDag - This pass converts a legalized DAG into a
541 /// Alpha-specific DAG, ready for instruction scheduling.
543 FunctionPass *llvm::createAlphaISelDag(AlphaTargetMachine &TM) {
544 return new AlphaDAGToDAGISel(TM);