1 //===-- AlphaISelDAGToDAG.cpp - Alpha pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Andrew Lenharth and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for Alpha,
11 // converting from a legalized dag to a Alpha dag.
13 //===----------------------------------------------------------------------===//
16 #include "AlphaTargetMachine.h"
17 #include "AlphaISelLowering.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/SSARegMap.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SelectionDAGISel.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/Constants.h"
27 #include "llvm/GlobalValue.h"
28 #include "llvm/Intrinsics.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/Support/MathExtras.h"
39 //===--------------------------------------------------------------------===//
40 /// AlphaDAGToDAGISel - Alpha specific code to select Alpha machine
41 /// instructions for SelectionDAG operations.
42 class AlphaDAGToDAGISel : public SelectionDAGISel {
43 AlphaTargetLowering AlphaLowering;
45 static const int64_t IMM_LOW = -32768;
46 static const int64_t IMM_HIGH = 32767;
47 static const int64_t IMM_MULT = 65536;
48 static const int64_t IMM_FULLHIGH = IMM_HIGH + IMM_HIGH * IMM_MULT;
49 static const int64_t IMM_FULLLOW = IMM_LOW + IMM_LOW * IMM_MULT;
51 static int64_t get_ldah16(int64_t x) {
52 int64_t y = x / IMM_MULT;
53 if (x % IMM_MULT > IMM_HIGH)
58 static int64_t get_lda16(int64_t x) {
59 return x - get_ldah16(x) * IMM_MULT;
62 static uint64_t get_zapImm(uint64_t x) {
63 unsigned int build = 0;
64 for(int i = 0; i < 8; ++i)
66 if ((x & 0x00FF) == 0x00FF)
68 else if ((x & 0x00FF) != 0)
75 static uint64_t getNearPower2(uint64_t x) {
77 unsigned at = CountLeadingZeros_64(x);
78 uint64_t complow = 1 << (63 - at);
79 uint64_t comphigh = 1 << (64 - at);
80 //std::cerr << x << ":" << complow << ":" << comphigh << "\n";
81 if (abs(complow - x) <= abs(comphigh - x))
87 static bool isFPZ(SDOperand N) {
88 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
89 return (CN && (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)));
91 static bool isFPZn(SDOperand N) {
92 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
93 return (CN && CN->isExactlyValue(-0.0));
95 static bool isFPZp(SDOperand N) {
96 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
97 return (CN && CN->isExactlyValue(+0.0));
101 AlphaDAGToDAGISel(TargetMachine &TM)
102 : SelectionDAGISel(AlphaLowering), AlphaLowering(TM)
105 /// getI64Imm - Return a target constant with the specified value, of type
107 inline SDOperand getI64Imm(int64_t Imm) {
108 return CurDAG->getTargetConstant(Imm, MVT::i64);
111 // Select - Convert the specified operand from a target-independent to a
112 // target-specific node if it hasn't already been changed.
113 SDNode *Select(SDOperand &Result, SDOperand Op);
115 /// InstructionSelectBasicBlock - This callback is invoked by
116 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
117 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
119 virtual const char *getPassName() const {
120 return "Alpha DAG->DAG Pattern Instruction Selection";
123 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
124 /// inline asm expressions.
125 virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
127 std::vector<SDOperand> &OutOps,
130 switch (ConstraintCode) {
131 default: return true;
137 OutOps.push_back(Op0);
141 // Include the pieces autogenerated from the target description.
142 #include "AlphaGenDAGISel.inc"
145 SDOperand getGlobalBaseReg();
146 SDOperand getGlobalRetAddr();
147 SDOperand SelectCALL(SDOperand Op);
152 /// getGlobalBaseReg - Output the instructions required to put the
153 /// GOT address into a register.
155 SDOperand AlphaDAGToDAGISel::getGlobalBaseReg() {
156 return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
157 AlphaLowering.getVRegGP(),
161 /// getRASaveReg - Grab the return address
163 SDOperand AlphaDAGToDAGISel::getGlobalRetAddr() {
164 return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
165 AlphaLowering.getVRegRA(),
169 /// InstructionSelectBasicBlock - This callback is invoked by
170 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
171 void AlphaDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
174 // Select target instructions for the DAG.
175 DAG.setRoot(SelectRoot(DAG.getRoot()));
176 DAG.RemoveDeadNodes();
178 // Emit machine code to BB.
179 ScheduleAndEmitDAG(DAG);
182 // Select - Convert the specified operand from a target-independent to a
183 // target-specific node if it hasn't already been changed.
184 SDNode *AlphaDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
186 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
187 N->getOpcode() < AlphaISD::FIRST_NUMBER) {
189 return NULL; // Already selected.
192 switch (N->getOpcode()) {
195 Result = SelectCALL(Op);
198 case ISD::FrameIndex: {
199 int FI = cast<FrameIndexSDNode>(N)->getIndex();
200 return CurDAG->SelectNodeTo(N, Alpha::LDA, MVT::i64,
201 CurDAG->getTargetFrameIndex(FI, MVT::i32),
204 case AlphaISD::GlobalBaseReg:
205 Result = getGlobalBaseReg();
206 ReplaceUses(Op, Result);
208 case AlphaISD::GlobalRetAddr:
209 Result = getGlobalRetAddr();
210 ReplaceUses(Op, Result);
213 case AlphaISD::DivCall: {
214 SDOperand Chain = CurDAG->getEntryNode();
215 SDOperand N0, N1, N2;
216 AddToQueue(N0, Op.getOperand(0));
217 AddToQueue(N1, Op.getOperand(1));
218 AddToQueue(N2, Op.getOperand(2));
219 Chain = CurDAG->getCopyToReg(Chain, Alpha::R24, N1,
221 Chain = CurDAG->getCopyToReg(Chain, Alpha::R25, N2,
223 Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, N0,
226 CurDAG->getTargetNode(Alpha::JSRs, MVT::Other, MVT::Flag,
227 Chain, Chain.getValue(1));
228 Chain = CurDAG->getCopyFromReg(Chain, Alpha::R27, MVT::i64,
229 SDOperand(CNode, 1));
230 return CurDAG->SelectNodeTo(N, Alpha::BIS, MVT::i64, Chain, Chain).Val;
233 case ISD::READCYCLECOUNTER: {
235 AddToQueue(Chain, N->getOperand(0)); //Select chain
236 Result = SDOperand(CurDAG->getTargetNode(Alpha::RPCC, MVT::i64, MVT::Other,
241 case ISD::Constant: {
242 uint64_t uval = cast<ConstantSDNode>(N)->getValue();
245 Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), Alpha::R31,
247 ReplaceUses(Op, Result);
251 int64_t val = (int64_t)uval;
252 int32_t val32 = (int32_t)val;
253 if (val <= IMM_HIGH + IMM_HIGH * IMM_MULT &&
254 val >= IMM_LOW + IMM_LOW * IMM_MULT)
255 break; //(LDAH (LDA))
256 if ((uval >> 32) == 0 && //empty upper bits
257 val32 <= IMM_HIGH + IMM_HIGH * IMM_MULT)
258 // val32 >= IMM_LOW + IMM_LOW * IMM_MULT) //always true
259 break; //(zext (LDAH (LDA)))
260 //Else use the constant pool
261 MachineConstantPool *CP = BB->getParent()->getConstantPool();
263 ConstantUInt::get(Type::getPrimitiveType(Type::ULongTyID) , uval);
264 SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
265 SDNode *Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI,
267 return CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, MVT::Other,
268 CPI, SDOperand(Tmp, 0), CurDAG->getEntryNode()).Val;
270 case ISD::TargetConstantFP: {
271 ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);
272 bool isDouble = N->getValueType(0) == MVT::f64;
273 MVT::ValueType T = isDouble ? MVT::f64 : MVT::f32;
274 if (CN->isExactlyValue(+0.0)) {
275 return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYST : Alpha::CPYSS,
276 T, CurDAG->getRegister(Alpha::F31, T),
277 CurDAG->getRegister(Alpha::F31, T)).Val;
278 } else if ( CN->isExactlyValue(-0.0)) {
279 return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYSNT : Alpha::CPYSNS,
280 T, CurDAG->getRegister(Alpha::F31, T),
281 CurDAG->getRegister(Alpha::F31, T)).Val;
289 if (MVT::isFloatingPoint(N->getOperand(0).Val->getValueType(0))) {
290 unsigned Opc = Alpha::WTF;
291 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
295 default: DEBUG(N->dump()); assert(0 && "Unknown FP comparison!");
296 case ISD::SETEQ: case ISD::SETOEQ: case ISD::SETUEQ: Opc = Alpha::CMPTEQ; break;
297 case ISD::SETLT: case ISD::SETOLT: case ISD::SETULT: Opc = Alpha::CMPTLT; break;
298 case ISD::SETLE: case ISD::SETOLE: case ISD::SETULE: Opc = Alpha::CMPTLE; break;
299 case ISD::SETGT: case ISD::SETOGT: case ISD::SETUGT: Opc = Alpha::CMPTLT; rev = true; break;
300 case ISD::SETGE: case ISD::SETOGE: case ISD::SETUGE: Opc = Alpha::CMPTLE; rev = true; break;
301 case ISD::SETNE: case ISD::SETONE: case ISD::SETUNE: Opc = Alpha::CMPTEQ; isNE = true; break;
303 SDOperand tmp1, tmp2;
304 AddToQueue(tmp1, N->getOperand(0));
305 AddToQueue(tmp2, N->getOperand(1));
306 SDNode *cmp = CurDAG->getTargetNode(Opc, MVT::f64,
310 cmp = CurDAG->getTargetNode(Alpha::CMPTEQ, MVT::f64, SDOperand(cmp, 0),
311 CurDAG->getRegister(Alpha::F31, MVT::f64));
314 if (AlphaLowering.hasITOF()) {
315 LD = CurDAG->getNode(AlphaISD::FTOIT_, MVT::i64, SDOperand(cmp, 0));
318 CurDAG->getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
319 SDOperand FI = CurDAG->getFrameIndex(FrameIdx, MVT::i64);
321 SDOperand(CurDAG->getTargetNode(Alpha::STT, MVT::Other,
322 SDOperand(cmp, 0), FI,
323 CurDAG->getRegister(Alpha::R31, MVT::i64)), 0);
324 LD = SDOperand(CurDAG->getTargetNode(Alpha::LDQ, MVT::i64, FI,
325 CurDAG->getRegister(Alpha::R31, MVT::i64),
328 Result = SDOperand(CurDAG->getTargetNode(Alpha::CMPULT, MVT::i64,
329 CurDAG->getRegister(Alpha::R31, MVT::i64),
336 if (MVT::isFloatingPoint(N->getValueType(0)) &&
337 (N->getOperand(0).getOpcode() != ISD::SETCC ||
338 !MVT::isFloatingPoint(N->getOperand(0).getOperand(1).getValueType()))) {
339 //This should be the condition not covered by the Patterns
340 //FIXME: Don't have SelectCode die, but rather return something testable
341 // so that things like this can be caught in fall though code
343 bool isDouble = N->getValueType(0) == MVT::f64;
344 SDOperand LD, cond, TV, FV;
345 AddToQueue(cond, N->getOperand(0));
346 AddToQueue(TV, N->getOperand(1));
347 AddToQueue(FV, N->getOperand(2));
349 if (AlphaLowering.hasITOF()) {
350 LD = CurDAG->getNode(AlphaISD::ITOFT_, MVT::f64, cond);
353 CurDAG->getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
354 SDOperand FI = CurDAG->getFrameIndex(FrameIdx, MVT::i64);
356 SDOperand(CurDAG->getTargetNode(Alpha::STQ, MVT::Other,
357 cond, FI, CurDAG->getRegister(Alpha::R31, MVT::i64)), 0);
358 LD = SDOperand(CurDAG->getTargetNode(Alpha::LDT, MVT::f64, FI,
359 CurDAG->getRegister(Alpha::R31, MVT::i64),
362 Result = SDOperand(CurDAG->getTargetNode(isDouble?Alpha::FCMOVNET:Alpha::FCMOVNES,
363 MVT::f64, FV, TV, LD), 0);
369 ConstantSDNode* SC = NULL;
370 ConstantSDNode* MC = NULL;
371 if (N->getOperand(0).getOpcode() == ISD::SRL &&
372 (MC = dyn_cast<ConstantSDNode>(N->getOperand(1))) &&
373 (SC = dyn_cast<ConstantSDNode>(N->getOperand(0).getOperand(1))))
375 uint64_t sval = SC->getValue();
376 uint64_t mval = MC->getValue();
377 if (get_zapImm(mval)) //the result is a zap, let the autogened stuff deal
379 // given mask X, and shift S, we want to see if there is any zap in the mask
380 // if we play around with the botton S bits
381 uint64_t dontcare = (~0ULL) >> (64 - sval);
382 uint64_t mask = mval << sval;
384 if (get_zapImm(mask | dontcare))
385 mask = mask | dontcare;
387 if (get_zapImm(mask)) {
389 AddToQueue(Src, N->getOperand(0).getOperand(0));
391 SDOperand(CurDAG->getTargetNode(Alpha::ZAPNOTi, MVT::i64, Src,
392 getI64Imm(get_zapImm(mask))), 0);
393 Result = SDOperand(CurDAG->getTargetNode(Alpha::SRL, MVT::i64, Z,
394 getI64Imm(sval)), 0);
403 return SelectCode(Result, Op);
406 SDOperand AlphaDAGToDAGISel::SelectCALL(SDOperand Op) {
407 //TODO: add flag stuff to prevent nondeturministic breakage!
411 SDOperand Addr = N->getOperand(1);
412 SDOperand InFlag(0,0); // Null incoming flag value.
413 AddToQueue(Chain, N->getOperand(0));
415 std::vector<SDOperand> CallOperands;
416 std::vector<MVT::ValueType> TypeOperands;
419 for(int i = 2, e = N->getNumOperands(); i < e; ++i) {
421 TypeOperands.push_back(N->getOperand(i).getValueType());
422 AddToQueue(Tmp, N->getOperand(i));
423 CallOperands.push_back(Tmp);
425 int count = N->getNumOperands() - 2;
427 static const unsigned args_int[] = {Alpha::R16, Alpha::R17, Alpha::R18,
428 Alpha::R19, Alpha::R20, Alpha::R21};
429 static const unsigned args_float[] = {Alpha::F16, Alpha::F17, Alpha::F18,
430 Alpha::F19, Alpha::F20, Alpha::F21};
432 for (int i = 6; i < count; ++i) {
433 unsigned Opc = Alpha::WTF;
434 if (MVT::isInteger(TypeOperands[i])) {
436 } else if (TypeOperands[i] == MVT::f32) {
438 } else if (TypeOperands[i] == MVT::f64) {
441 assert(0 && "Unknown operand");
442 Chain = SDOperand(CurDAG->getTargetNode(Opc, MVT::Other, CallOperands[i],
443 getI64Imm((i - 6) * 8),
444 CurDAG->getCopyFromReg(Chain, Alpha::R30, MVT::i64),
447 for (int i = 0; i < std::min(6, count); ++i) {
448 if (MVT::isInteger(TypeOperands[i])) {
449 Chain = CurDAG->getCopyToReg(Chain, args_int[i], CallOperands[i], InFlag);
450 InFlag = Chain.getValue(1);
451 } else if (TypeOperands[i] == MVT::f32 || TypeOperands[i] == MVT::f64) {
452 Chain = CurDAG->getCopyToReg(Chain, args_float[i], CallOperands[i], InFlag);
453 InFlag = Chain.getValue(1);
455 assert(0 && "Unknown operand");
458 // Finally, once everything is in registers to pass to the call, emit the
460 if (Addr.getOpcode() == AlphaISD::GPRelLo) {
461 SDOperand GOT = getGlobalBaseReg();
462 Chain = CurDAG->getCopyToReg(Chain, Alpha::R29, GOT, InFlag);
463 InFlag = Chain.getValue(1);
464 Chain = SDOperand(CurDAG->getTargetNode(Alpha::BSR, MVT::Other, MVT::Flag,
465 Addr.getOperand(0), Chain, InFlag), 0);
467 AddToQueue(Addr, Addr);
468 Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, Addr, InFlag);
469 InFlag = Chain.getValue(1);
470 Chain = SDOperand(CurDAG->getTargetNode(Alpha::JSR, MVT::Other, MVT::Flag,
473 InFlag = Chain.getValue(1);
475 std::vector<SDOperand> CallResults;
477 switch (N->getValueType(0)) {
478 default: assert(0 && "Unexpected ret value!");
479 case MVT::Other: break;
481 Chain = CurDAG->getCopyFromReg(Chain, Alpha::R0, MVT::i64, InFlag).getValue(1);
482 CallResults.push_back(Chain.getValue(0));
485 Chain = CurDAG->getCopyFromReg(Chain, Alpha::F0, MVT::f32, InFlag).getValue(1);
486 CallResults.push_back(Chain.getValue(0));
489 Chain = CurDAG->getCopyFromReg(Chain, Alpha::F0, MVT::f64, InFlag).getValue(1);
490 CallResults.push_back(Chain.getValue(0));
494 CallResults.push_back(Chain);
495 for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
496 ReplaceUses(Op.getValue(i), CallResults[i]);
497 return CallResults[Op.ResNo];
501 /// createAlphaISelDag - This pass converts a legalized DAG into a
502 /// Alpha-specific DAG, ready for instruction scheduling.
504 FunctionPass *llvm::createAlphaISelDag(TargetMachine &TM) {
505 return new AlphaDAGToDAGISel(TM);