1 //===-- ARM64InstPrinter.cpp - Convert ARM64 MCInst to assembly syntax ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class prints an ARM64 MCInst to a .s file.
12 //===----------------------------------------------------------------------===//
14 #include "ARM64InstPrinter.h"
15 #include "MCTargetDesc/ARM64AddressingModes.h"
16 #include "Utils/ARM64BaseInfo.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/ADT/StringExtras.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCRegisterInfo.h"
22 #include "llvm/Support/Format.h"
23 #include "llvm/Support/raw_ostream.h"
26 #define DEBUG_TYPE "asm-printer"
28 #define GET_INSTRUCTION_NAME
29 #define PRINT_ALIAS_INSTR
30 #include "ARM64GenAsmWriter.inc"
31 #define GET_INSTRUCTION_NAME
32 #define PRINT_ALIAS_INSTR
33 #include "ARM64GenAsmWriter1.inc"
35 ARM64InstPrinter::ARM64InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
36 const MCRegisterInfo &MRI,
37 const MCSubtargetInfo &STI)
38 : MCInstPrinter(MAI, MII, MRI) {
39 // Initialize the set of available features.
40 setAvailableFeatures(STI.getFeatureBits());
43 ARM64AppleInstPrinter::ARM64AppleInstPrinter(const MCAsmInfo &MAI,
44 const MCInstrInfo &MII,
45 const MCRegisterInfo &MRI,
46 const MCSubtargetInfo &STI)
47 : ARM64InstPrinter(MAI, MII, MRI, STI) {}
49 void ARM64InstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
50 // This is for .cfi directives.
51 OS << getRegisterName(RegNo);
54 void ARM64InstPrinter::printInst(const MCInst *MI, raw_ostream &O,
56 // Check for special encodings and print the canonical alias instead.
58 unsigned Opcode = MI->getOpcode();
60 if (Opcode == ARM64::SYSxt)
61 if (printSysAlias(MI, O)) {
62 printAnnotation(O, Annot);
66 // TBZ/TBNZ should print the register operand as a Wreg if the bit
68 if ((Opcode == ARM64::TBNZ || Opcode == ARM64::TBZ) &&
69 MI->getOperand(1).getImm() < 32) {
71 unsigned Reg = MI->getOperand(0).getReg();
72 newMI.getOperand(0).setReg(getWRegFromXReg(Reg));
73 printInstruction(&newMI, O);
74 printAnnotation(O, Annot);
78 // SBFM/UBFM should print to a nicer aliased form if possible.
79 if (Opcode == ARM64::SBFMXri || Opcode == ARM64::SBFMWri ||
80 Opcode == ARM64::UBFMXri || Opcode == ARM64::UBFMWri) {
81 const MCOperand &Op0 = MI->getOperand(0);
82 const MCOperand &Op1 = MI->getOperand(1);
83 const MCOperand &Op2 = MI->getOperand(2);
84 const MCOperand &Op3 = MI->getOperand(3);
86 bool IsSigned = (Opcode == ARM64::SBFMXri || Opcode == ARM64::SBFMWri);
87 bool Is64Bit = (Opcode == ARM64::SBFMXri || Opcode == ARM64::UBFMXri);
88 if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) {
89 const char *AsmMnemonic = nullptr;
91 switch (Op3.getImm()) {
102 AsmMnemonic = "sxth";
104 AsmMnemonic = "uxth";
107 // *xtw is only valid for signed 64-bit operations.
108 if (Is64Bit && IsSigned)
109 AsmMnemonic = "sxtw";
114 O << '\t' << AsmMnemonic << '\t' << getRegisterName(Op0.getReg())
115 << ", " << getRegisterName(getWRegFromXReg(Op1.getReg()));
116 printAnnotation(O, Annot);
121 // All immediate shifts are aliases, implemented using the Bitfield
122 // instruction. In all cases the immediate shift amount shift must be in
123 // the range 0 to (reg.size -1).
124 if (Op2.isImm() && Op3.isImm()) {
125 const char *AsmMnemonic = nullptr;
127 int64_t immr = Op2.getImm();
128 int64_t imms = Op3.getImm();
129 if (Opcode == ARM64::UBFMWri && imms != 0x1F && ((imms + 1) == immr)) {
132 } else if (Opcode == ARM64::UBFMXri && imms != 0x3f &&
133 ((imms + 1 == immr))) {
136 } else if (Opcode == ARM64::UBFMWri && imms == 0x1f) {
139 } else if (Opcode == ARM64::UBFMXri && imms == 0x3f) {
142 } else if (Opcode == ARM64::SBFMWri && imms == 0x1f) {
145 } else if (Opcode == ARM64::SBFMXri && imms == 0x3f) {
150 O << '\t' << AsmMnemonic << '\t' << getRegisterName(Op0.getReg())
151 << ", " << getRegisterName(Op1.getReg()) << ", #" << shift;
152 printAnnotation(O, Annot);
157 // SBFIZ/UBFIZ aliases
158 if (Op2.getImm() > Op3.getImm()) {
159 O << '\t' << (IsSigned ? "sbfiz" : "ubfiz") << '\t'
160 << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op1.getReg())
161 << ", #" << (Is64Bit ? 64 : 32) - Op2.getImm() << ", #" << Op3.getImm() + 1;
162 printAnnotation(O, Annot);
166 // Otherwise SBFX/UBFX is the preferred form
167 O << '\t' << (IsSigned ? "sbfx" : "ubfx") << '\t'
168 << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op1.getReg())
169 << ", #" << Op2.getImm() << ", #" << Op3.getImm() - Op2.getImm() + 1;
170 printAnnotation(O, Annot);
174 if (Opcode == ARM64::BFMXri || Opcode == ARM64::BFMWri) {
175 const MCOperand &Op0 = MI->getOperand(0); // Op1 == Op0
176 const MCOperand &Op2 = MI->getOperand(2);
177 int ImmR = MI->getOperand(3).getImm();
178 int ImmS = MI->getOperand(4).getImm();
182 int BitWidth = Opcode == ARM64::BFMXri ? 64 : 32;
183 int LSB = (BitWidth - ImmR) % BitWidth;
184 int Width = ImmS + 1;
185 O << "\tbfi\t" << getRegisterName(Op0.getReg()) << ", "
186 << getRegisterName(Op2.getReg()) << ", #" << LSB << ", #" << Width;
187 printAnnotation(O, Annot);
192 int Width = ImmS - ImmR + 1;
193 // Otherwise BFXIL the preferred form
195 << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op2.getReg())
196 << ", #" << LSB << ", #" << Width;
197 printAnnotation(O, Annot);
201 // Symbolic operands for MOVZ, MOVN and MOVK already imply a shift
202 // (e.g. :gottprel_g1: is always going to be "lsl #16") so it should not be
204 if ((Opcode == ARM64::MOVZXi || Opcode == ARM64::MOVZWi ||
205 Opcode == ARM64::MOVNXi || Opcode == ARM64::MOVNWi) &&
206 MI->getOperand(1).isExpr()) {
207 if (Opcode == ARM64::MOVZXi || Opcode == ARM64::MOVZWi)
212 O << getRegisterName(MI->getOperand(0).getReg()) << ", #"
213 << *MI->getOperand(1).getExpr();
217 if ((Opcode == ARM64::MOVKXi || Opcode == ARM64::MOVKWi) &&
218 MI->getOperand(2).isExpr()) {
219 O << "\tmovk\t" << getRegisterName(MI->getOperand(0).getReg()) << ", #"
220 << *MI->getOperand(2).getExpr();
224 // FIXME: TableGen should be able to do all of these now.
226 // ANDS WZR, Wn, Wm{, lshift #imm} ==> TST Wn{, lshift #imm}
227 // ANDS XZR, Xn, Xm{, lshift #imm} ==> TST Xn{, lshift #imm}
228 if ((Opcode == ARM64::ANDSWrs && MI->getOperand(0).getReg() == ARM64::WZR) ||
229 (Opcode == ARM64::ANDSXrs && MI->getOperand(0).getReg() == ARM64::XZR)) {
230 O << "\ttst\t" << getRegisterName(MI->getOperand(1).getReg()) << ", ";
231 printShiftedRegister(MI, 2, O);
235 // ORN Wn, WZR, Wm{, lshift #imm} ==> MVN Wn, Wm{, lshift #imm}
236 // ORN Xn, XZR, Xm{, lshift #imm} ==> MVN Xn, Xm{, lshift #imm}
237 if ((Opcode == ARM64::ORNWrs && MI->getOperand(1).getReg() == ARM64::WZR) ||
238 (Opcode == ARM64::ORNXrs && MI->getOperand(1).getReg() == ARM64::XZR)) {
239 O << "\tmvn\t" << getRegisterName(MI->getOperand(0).getReg()) << ", ";
240 printShiftedRegister(MI, 2, O);
243 // SUBS WZR, Wn, Wm{, lshift #imm} ==> CMP Wn, Wm{, lshift #imm}
244 // SUBS XZR, Xn, Xm{, lshift #imm} ==> CMP Xn, Xm{, lshift #imm}
245 if ((Opcode == ARM64::SUBSWrs && MI->getOperand(0).getReg() == ARM64::WZR) ||
246 (Opcode == ARM64::SUBSXrs && MI->getOperand(0).getReg() == ARM64::XZR)) {
247 O << "\tcmp\t" << getRegisterName(MI->getOperand(1).getReg()) << ", ";
248 printShiftedRegister(MI, 2, O);
251 // SUBS XZR, Xn, Wm, uxtb #imm ==> CMP Xn, uxtb #imm
252 // SUBS WZR, Wn, Xm, uxtb #imm ==> CMP Wn, uxtb #imm
253 if ((Opcode == ARM64::SUBSXrx && MI->getOperand(0).getReg() == ARM64::XZR) ||
254 (Opcode == ARM64::SUBSWrx && MI->getOperand(0).getReg() == ARM64::WZR)) {
255 O << "\tcmp\t" << getRegisterName(MI->getOperand(1).getReg()) << ", ";
256 printExtendedRegister(MI, 2, O);
259 // SUBS XZR, Xn, Xm, uxtx #imm ==> CMP Xn, uxtb #imm
260 if (Opcode == ARM64::SUBSXrx64 && MI->getOperand(0).getReg() == ARM64::XZR) {
261 O << "\tcmp\t" << getRegisterName(MI->getOperand(1).getReg()) << ", "
262 << getRegisterName(MI->getOperand(2).getReg());
263 printExtend(MI, 3, O);
267 // ADDS WZR, Wn, Wm{, lshift #imm} ==> CMN Wn, Wm{, lshift #imm}
268 // ADDS XZR, Xn, Xm{, lshift #imm} ==> CMN Xn, Xm{, lshift #imm}
269 if ((Opcode == ARM64::ADDSWrs && MI->getOperand(0).getReg() == ARM64::WZR) ||
270 (Opcode == ARM64::ADDSXrs && MI->getOperand(0).getReg() == ARM64::XZR)) {
271 O << "\tcmn\t" << getRegisterName(MI->getOperand(1).getReg()) << ", ";
272 printShiftedRegister(MI, 2, O);
275 // ADDS XZR, Xn, Wm, uxtb #imm ==> CMN Xn, uxtb #imm
276 if (Opcode == ARM64::ADDSXrx && MI->getOperand(0).getReg() == ARM64::XZR) {
277 O << "\tcmn\t" << getRegisterName(MI->getOperand(1).getReg()) << ", ";
278 printExtendedRegister(MI, 2, O);
281 // ADDS XZR, Xn, Xm, uxtx #imm ==> CMN Xn, uxtb #imm
282 if (Opcode == ARM64::ADDSXrx64 && MI->getOperand(0).getReg() == ARM64::XZR) {
283 O << "\tcmn\t" << getRegisterName(MI->getOperand(1).getReg()) << ", "
284 << getRegisterName(MI->getOperand(2).getReg());
285 printExtend(MI, 3, O);
289 if (!printAliasInstr(MI, O))
290 printInstruction(MI, O);
292 printAnnotation(O, Annot);
295 static bool isTblTbxInstruction(unsigned Opcode, StringRef &Layout,
298 case ARM64::TBXv8i8One:
299 case ARM64::TBXv8i8Two:
300 case ARM64::TBXv8i8Three:
301 case ARM64::TBXv8i8Four:
305 case ARM64::TBLv8i8One:
306 case ARM64::TBLv8i8Two:
307 case ARM64::TBLv8i8Three:
308 case ARM64::TBLv8i8Four:
312 case ARM64::TBXv16i8One:
313 case ARM64::TBXv16i8Two:
314 case ARM64::TBXv16i8Three:
315 case ARM64::TBXv16i8Four:
319 case ARM64::TBLv16i8One:
320 case ARM64::TBLv16i8Two:
321 case ARM64::TBLv16i8Three:
322 case ARM64::TBLv16i8Four:
331 struct LdStNInstrDesc {
333 const char *Mnemonic;
340 static LdStNInstrDesc LdStNInstInfo[] = {
341 { ARM64::LD1i8, "ld1", ".b", 1, true, 0 },
342 { ARM64::LD1i16, "ld1", ".h", 1, true, 0 },
343 { ARM64::LD1i32, "ld1", ".s", 1, true, 0 },
344 { ARM64::LD1i64, "ld1", ".d", 1, true, 0 },
345 { ARM64::LD1i8_POST, "ld1", ".b", 2, true, 1 },
346 { ARM64::LD1i16_POST, "ld1", ".h", 2, true, 2 },
347 { ARM64::LD1i32_POST, "ld1", ".s", 2, true, 4 },
348 { ARM64::LD1i64_POST, "ld1", ".d", 2, true, 8 },
349 { ARM64::LD1Rv16b, "ld1r", ".16b", 0, false, 0 },
350 { ARM64::LD1Rv8h, "ld1r", ".8h", 0, false, 0 },
351 { ARM64::LD1Rv4s, "ld1r", ".4s", 0, false, 0 },
352 { ARM64::LD1Rv2d, "ld1r", ".2d", 0, false, 0 },
353 { ARM64::LD1Rv8b, "ld1r", ".8b", 0, false, 0 },
354 { ARM64::LD1Rv4h, "ld1r", ".4h", 0, false, 0 },
355 { ARM64::LD1Rv2s, "ld1r", ".2s", 0, false, 0 },
356 { ARM64::LD1Rv1d, "ld1r", ".1d", 0, false, 0 },
357 { ARM64::LD1Rv16b_POST, "ld1r", ".16b", 1, false, 1 },
358 { ARM64::LD1Rv8h_POST, "ld1r", ".8h", 1, false, 2 },
359 { ARM64::LD1Rv4s_POST, "ld1r", ".4s", 1, false, 4 },
360 { ARM64::LD1Rv2d_POST, "ld1r", ".2d", 1, false, 8 },
361 { ARM64::LD1Rv8b_POST, "ld1r", ".8b", 1, false, 1 },
362 { ARM64::LD1Rv4h_POST, "ld1r", ".4h", 1, false, 2 },
363 { ARM64::LD1Rv2s_POST, "ld1r", ".2s", 1, false, 4 },
364 { ARM64::LD1Rv1d_POST, "ld1r", ".1d", 1, false, 8 },
365 { ARM64::LD1Onev16b, "ld1", ".16b", 0, false, 0 },
366 { ARM64::LD1Onev8h, "ld1", ".8h", 0, false, 0 },
367 { ARM64::LD1Onev4s, "ld1", ".4s", 0, false, 0 },
368 { ARM64::LD1Onev2d, "ld1", ".2d", 0, false, 0 },
369 { ARM64::LD1Onev8b, "ld1", ".8b", 0, false, 0 },
370 { ARM64::LD1Onev4h, "ld1", ".4h", 0, false, 0 },
371 { ARM64::LD1Onev2s, "ld1", ".2s", 0, false, 0 },
372 { ARM64::LD1Onev1d, "ld1", ".1d", 0, false, 0 },
373 { ARM64::LD1Onev16b_POST, "ld1", ".16b", 1, false, 16 },
374 { ARM64::LD1Onev8h_POST, "ld1", ".8h", 1, false, 16 },
375 { ARM64::LD1Onev4s_POST, "ld1", ".4s", 1, false, 16 },
376 { ARM64::LD1Onev2d_POST, "ld1", ".2d", 1, false, 16 },
377 { ARM64::LD1Onev8b_POST, "ld1", ".8b", 1, false, 8 },
378 { ARM64::LD1Onev4h_POST, "ld1", ".4h", 1, false, 8 },
379 { ARM64::LD1Onev2s_POST, "ld1", ".2s", 1, false, 8 },
380 { ARM64::LD1Onev1d_POST, "ld1", ".1d", 1, false, 8 },
381 { ARM64::LD1Twov16b, "ld1", ".16b", 0, false, 0 },
382 { ARM64::LD1Twov8h, "ld1", ".8h", 0, false, 0 },
383 { ARM64::LD1Twov4s, "ld1", ".4s", 0, false, 0 },
384 { ARM64::LD1Twov2d, "ld1", ".2d", 0, false, 0 },
385 { ARM64::LD1Twov8b, "ld1", ".8b", 0, false, 0 },
386 { ARM64::LD1Twov4h, "ld1", ".4h", 0, false, 0 },
387 { ARM64::LD1Twov2s, "ld1", ".2s", 0, false, 0 },
388 { ARM64::LD1Twov1d, "ld1", ".1d", 0, false, 0 },
389 { ARM64::LD1Twov16b_POST, "ld1", ".16b", 1, false, 32 },
390 { ARM64::LD1Twov8h_POST, "ld1", ".8h", 1, false, 32 },
391 { ARM64::LD1Twov4s_POST, "ld1", ".4s", 1, false, 32 },
392 { ARM64::LD1Twov2d_POST, "ld1", ".2d", 1, false, 32 },
393 { ARM64::LD1Twov8b_POST, "ld1", ".8b", 1, false, 16 },
394 { ARM64::LD1Twov4h_POST, "ld1", ".4h", 1, false, 16 },
395 { ARM64::LD1Twov2s_POST, "ld1", ".2s", 1, false, 16 },
396 { ARM64::LD1Twov1d_POST, "ld1", ".1d", 1, false, 16 },
397 { ARM64::LD1Threev16b, "ld1", ".16b", 0, false, 0 },
398 { ARM64::LD1Threev8h, "ld1", ".8h", 0, false, 0 },
399 { ARM64::LD1Threev4s, "ld1", ".4s", 0, false, 0 },
400 { ARM64::LD1Threev2d, "ld1", ".2d", 0, false, 0 },
401 { ARM64::LD1Threev8b, "ld1", ".8b", 0, false, 0 },
402 { ARM64::LD1Threev4h, "ld1", ".4h", 0, false, 0 },
403 { ARM64::LD1Threev2s, "ld1", ".2s", 0, false, 0 },
404 { ARM64::LD1Threev1d, "ld1", ".1d", 0, false, 0 },
405 { ARM64::LD1Threev16b_POST, "ld1", ".16b", 1, false, 48 },
406 { ARM64::LD1Threev8h_POST, "ld1", ".8h", 1, false, 48 },
407 { ARM64::LD1Threev4s_POST, "ld1", ".4s", 1, false, 48 },
408 { ARM64::LD1Threev2d_POST, "ld1", ".2d", 1, false, 48 },
409 { ARM64::LD1Threev8b_POST, "ld1", ".8b", 1, false, 24 },
410 { ARM64::LD1Threev4h_POST, "ld1", ".4h", 1, false, 24 },
411 { ARM64::LD1Threev2s_POST, "ld1", ".2s", 1, false, 24 },
412 { ARM64::LD1Threev1d_POST, "ld1", ".1d", 1, false, 24 },
413 { ARM64::LD1Fourv16b, "ld1", ".16b", 0, false, 0 },
414 { ARM64::LD1Fourv8h, "ld1", ".8h", 0, false, 0 },
415 { ARM64::LD1Fourv4s, "ld1", ".4s", 0, false, 0 },
416 { ARM64::LD1Fourv2d, "ld1", ".2d", 0, false, 0 },
417 { ARM64::LD1Fourv8b, "ld1", ".8b", 0, false, 0 },
418 { ARM64::LD1Fourv4h, "ld1", ".4h", 0, false, 0 },
419 { ARM64::LD1Fourv2s, "ld1", ".2s", 0, false, 0 },
420 { ARM64::LD1Fourv1d, "ld1", ".1d", 0, false, 0 },
421 { ARM64::LD1Fourv16b_POST, "ld1", ".16b", 1, false, 64 },
422 { ARM64::LD1Fourv8h_POST, "ld1", ".8h", 1, false, 64 },
423 { ARM64::LD1Fourv4s_POST, "ld1", ".4s", 1, false, 64 },
424 { ARM64::LD1Fourv2d_POST, "ld1", ".2d", 1, false, 64 },
425 { ARM64::LD1Fourv8b_POST, "ld1", ".8b", 1, false, 32 },
426 { ARM64::LD1Fourv4h_POST, "ld1", ".4h", 1, false, 32 },
427 { ARM64::LD1Fourv2s_POST, "ld1", ".2s", 1, false, 32 },
428 { ARM64::LD1Fourv1d_POST, "ld1", ".1d", 1, false, 32 },
429 { ARM64::LD2i8, "ld2", ".b", 1, true, 0 },
430 { ARM64::LD2i16, "ld2", ".h", 1, true, 0 },
431 { ARM64::LD2i32, "ld2", ".s", 1, true, 0 },
432 { ARM64::LD2i64, "ld2", ".d", 1, true, 0 },
433 { ARM64::LD2i8_POST, "ld2", ".b", 2, true, 2 },
434 { ARM64::LD2i16_POST, "ld2", ".h", 2, true, 4 },
435 { ARM64::LD2i32_POST, "ld2", ".s", 2, true, 8 },
436 { ARM64::LD2i64_POST, "ld2", ".d", 2, true, 16 },
437 { ARM64::LD2Rv16b, "ld2r", ".16b", 0, false, 0 },
438 { ARM64::LD2Rv8h, "ld2r", ".8h", 0, false, 0 },
439 { ARM64::LD2Rv4s, "ld2r", ".4s", 0, false, 0 },
440 { ARM64::LD2Rv2d, "ld2r", ".2d", 0, false, 0 },
441 { ARM64::LD2Rv8b, "ld2r", ".8b", 0, false, 0 },
442 { ARM64::LD2Rv4h, "ld2r", ".4h", 0, false, 0 },
443 { ARM64::LD2Rv2s, "ld2r", ".2s", 0, false, 0 },
444 { ARM64::LD2Rv1d, "ld2r", ".1d", 0, false, 0 },
445 { ARM64::LD2Rv16b_POST, "ld2r", ".16b", 1, false, 2 },
446 { ARM64::LD2Rv8h_POST, "ld2r", ".8h", 1, false, 4 },
447 { ARM64::LD2Rv4s_POST, "ld2r", ".4s", 1, false, 8 },
448 { ARM64::LD2Rv2d_POST, "ld2r", ".2d", 1, false, 16 },
449 { ARM64::LD2Rv8b_POST, "ld2r", ".8b", 1, false, 2 },
450 { ARM64::LD2Rv4h_POST, "ld2r", ".4h", 1, false, 4 },
451 { ARM64::LD2Rv2s_POST, "ld2r", ".2s", 1, false, 8 },
452 { ARM64::LD2Rv1d_POST, "ld2r", ".1d", 1, false, 16 },
453 { ARM64::LD2Twov16b, "ld2", ".16b", 0, false, 0 },
454 { ARM64::LD2Twov8h, "ld2", ".8h", 0, false, 0 },
455 { ARM64::LD2Twov4s, "ld2", ".4s", 0, false, 0 },
456 { ARM64::LD2Twov2d, "ld2", ".2d", 0, false, 0 },
457 { ARM64::LD2Twov8b, "ld2", ".8b", 0, false, 0 },
458 { ARM64::LD2Twov4h, "ld2", ".4h", 0, false, 0 },
459 { ARM64::LD2Twov2s, "ld2", ".2s", 0, false, 0 },
460 { ARM64::LD2Twov16b_POST, "ld2", ".16b", 1, false, 32 },
461 { ARM64::LD2Twov8h_POST, "ld2", ".8h", 1, false, 32 },
462 { ARM64::LD2Twov4s_POST, "ld2", ".4s", 1, false, 32 },
463 { ARM64::LD2Twov2d_POST, "ld2", ".2d", 1, false, 32 },
464 { ARM64::LD2Twov8b_POST, "ld2", ".8b", 1, false, 16 },
465 { ARM64::LD2Twov4h_POST, "ld2", ".4h", 1, false, 16 },
466 { ARM64::LD2Twov2s_POST, "ld2", ".2s", 1, false, 16 },
467 { ARM64::LD3i8, "ld3", ".b", 1, true, 0 },
468 { ARM64::LD3i16, "ld3", ".h", 1, true, 0 },
469 { ARM64::LD3i32, "ld3", ".s", 1, true, 0 },
470 { ARM64::LD3i64, "ld3", ".d", 1, true, 0 },
471 { ARM64::LD3i8_POST, "ld3", ".b", 2, true, 3 },
472 { ARM64::LD3i16_POST, "ld3", ".h", 2, true, 6 },
473 { ARM64::LD3i32_POST, "ld3", ".s", 2, true, 12 },
474 { ARM64::LD3i64_POST, "ld3", ".d", 2, true, 24 },
475 { ARM64::LD3Rv16b, "ld3r", ".16b", 0, false, 0 },
476 { ARM64::LD3Rv8h, "ld3r", ".8h", 0, false, 0 },
477 { ARM64::LD3Rv4s, "ld3r", ".4s", 0, false, 0 },
478 { ARM64::LD3Rv2d, "ld3r", ".2d", 0, false, 0 },
479 { ARM64::LD3Rv8b, "ld3r", ".8b", 0, false, 0 },
480 { ARM64::LD3Rv4h, "ld3r", ".4h", 0, false, 0 },
481 { ARM64::LD3Rv2s, "ld3r", ".2s", 0, false, 0 },
482 { ARM64::LD3Rv1d, "ld3r", ".1d", 0, false, 0 },
483 { ARM64::LD3Rv16b_POST, "ld3r", ".16b", 1, false, 3 },
484 { ARM64::LD3Rv8h_POST, "ld3r", ".8h", 1, false, 6 },
485 { ARM64::LD3Rv4s_POST, "ld3r", ".4s", 1, false, 12 },
486 { ARM64::LD3Rv2d_POST, "ld3r", ".2d", 1, false, 24 },
487 { ARM64::LD3Rv8b_POST, "ld3r", ".8b", 1, false, 3 },
488 { ARM64::LD3Rv4h_POST, "ld3r", ".4h", 1, false, 6 },
489 { ARM64::LD3Rv2s_POST, "ld3r", ".2s", 1, false, 12 },
490 { ARM64::LD3Rv1d_POST, "ld3r", ".1d", 1, false, 24 },
491 { ARM64::LD3Threev16b, "ld3", ".16b", 0, false, 0 },
492 { ARM64::LD3Threev8h, "ld3", ".8h", 0, false, 0 },
493 { ARM64::LD3Threev4s, "ld3", ".4s", 0, false, 0 },
494 { ARM64::LD3Threev2d, "ld3", ".2d", 0, false, 0 },
495 { ARM64::LD3Threev8b, "ld3", ".8b", 0, false, 0 },
496 { ARM64::LD3Threev4h, "ld3", ".4h", 0, false, 0 },
497 { ARM64::LD3Threev2s, "ld3", ".2s", 0, false, 0 },
498 { ARM64::LD3Threev16b_POST, "ld3", ".16b", 1, false, 48 },
499 { ARM64::LD3Threev8h_POST, "ld3", ".8h", 1, false, 48 },
500 { ARM64::LD3Threev4s_POST, "ld3", ".4s", 1, false, 48 },
501 { ARM64::LD3Threev2d_POST, "ld3", ".2d", 1, false, 48 },
502 { ARM64::LD3Threev8b_POST, "ld3", ".8b", 1, false, 24 },
503 { ARM64::LD3Threev4h_POST, "ld3", ".4h", 1, false, 24 },
504 { ARM64::LD3Threev2s_POST, "ld3", ".2s", 1, false, 24 },
505 { ARM64::LD4i8, "ld4", ".b", 1, true, 0 },
506 { ARM64::LD4i16, "ld4", ".h", 1, true, 0 },
507 { ARM64::LD4i32, "ld4", ".s", 1, true, 0 },
508 { ARM64::LD4i64, "ld4", ".d", 1, true, 0 },
509 { ARM64::LD4i8_POST, "ld4", ".b", 2, true, 4 },
510 { ARM64::LD4i16_POST, "ld4", ".h", 2, true, 8 },
511 { ARM64::LD4i32_POST, "ld4", ".s", 2, true, 16 },
512 { ARM64::LD4i64_POST, "ld4", ".d", 2, true, 32 },
513 { ARM64::LD4Rv16b, "ld4r", ".16b", 0, false, 0 },
514 { ARM64::LD4Rv8h, "ld4r", ".8h", 0, false, 0 },
515 { ARM64::LD4Rv4s, "ld4r", ".4s", 0, false, 0 },
516 { ARM64::LD4Rv2d, "ld4r", ".2d", 0, false, 0 },
517 { ARM64::LD4Rv8b, "ld4r", ".8b", 0, false, 0 },
518 { ARM64::LD4Rv4h, "ld4r", ".4h", 0, false, 0 },
519 { ARM64::LD4Rv2s, "ld4r", ".2s", 0, false, 0 },
520 { ARM64::LD4Rv1d, "ld4r", ".1d", 0, false, 0 },
521 { ARM64::LD4Rv16b_POST, "ld4r", ".16b", 1, false, 4 },
522 { ARM64::LD4Rv8h_POST, "ld4r", ".8h", 1, false, 8 },
523 { ARM64::LD4Rv4s_POST, "ld4r", ".4s", 1, false, 16 },
524 { ARM64::LD4Rv2d_POST, "ld4r", ".2d", 1, false, 32 },
525 { ARM64::LD4Rv8b_POST, "ld4r", ".8b", 1, false, 4 },
526 { ARM64::LD4Rv4h_POST, "ld4r", ".4h", 1, false, 8 },
527 { ARM64::LD4Rv2s_POST, "ld4r", ".2s", 1, false, 16 },
528 { ARM64::LD4Rv1d_POST, "ld4r", ".1d", 1, false, 32 },
529 { ARM64::LD4Fourv16b, "ld4", ".16b", 0, false, 0 },
530 { ARM64::LD4Fourv8h, "ld4", ".8h", 0, false, 0 },
531 { ARM64::LD4Fourv4s, "ld4", ".4s", 0, false, 0 },
532 { ARM64::LD4Fourv2d, "ld4", ".2d", 0, false, 0 },
533 { ARM64::LD4Fourv8b, "ld4", ".8b", 0, false, 0 },
534 { ARM64::LD4Fourv4h, "ld4", ".4h", 0, false, 0 },
535 { ARM64::LD4Fourv2s, "ld4", ".2s", 0, false, 0 },
536 { ARM64::LD4Fourv16b_POST, "ld4", ".16b", 1, false, 64 },
537 { ARM64::LD4Fourv8h_POST, "ld4", ".8h", 1, false, 64 },
538 { ARM64::LD4Fourv4s_POST, "ld4", ".4s", 1, false, 64 },
539 { ARM64::LD4Fourv2d_POST, "ld4", ".2d", 1, false, 64 },
540 { ARM64::LD4Fourv8b_POST, "ld4", ".8b", 1, false, 32 },
541 { ARM64::LD4Fourv4h_POST, "ld4", ".4h", 1, false, 32 },
542 { ARM64::LD4Fourv2s_POST, "ld4", ".2s", 1, false, 32 },
543 { ARM64::ST1i8, "st1", ".b", 0, true, 0 },
544 { ARM64::ST1i16, "st1", ".h", 0, true, 0 },
545 { ARM64::ST1i32, "st1", ".s", 0, true, 0 },
546 { ARM64::ST1i64, "st1", ".d", 0, true, 0 },
547 { ARM64::ST1i8_POST, "st1", ".b", 1, true, 1 },
548 { ARM64::ST1i16_POST, "st1", ".h", 1, true, 2 },
549 { ARM64::ST1i32_POST, "st1", ".s", 1, true, 4 },
550 { ARM64::ST1i64_POST, "st1", ".d", 1, true, 8 },
551 { ARM64::ST1Onev16b, "st1", ".16b", 0, false, 0 },
552 { ARM64::ST1Onev8h, "st1", ".8h", 0, false, 0 },
553 { ARM64::ST1Onev4s, "st1", ".4s", 0, false, 0 },
554 { ARM64::ST1Onev2d, "st1", ".2d", 0, false, 0 },
555 { ARM64::ST1Onev8b, "st1", ".8b", 0, false, 0 },
556 { ARM64::ST1Onev4h, "st1", ".4h", 0, false, 0 },
557 { ARM64::ST1Onev2s, "st1", ".2s", 0, false, 0 },
558 { ARM64::ST1Onev1d, "st1", ".1d", 0, false, 0 },
559 { ARM64::ST1Onev16b_POST, "st1", ".16b", 1, false, 16 },
560 { ARM64::ST1Onev8h_POST, "st1", ".8h", 1, false, 16 },
561 { ARM64::ST1Onev4s_POST, "st1", ".4s", 1, false, 16 },
562 { ARM64::ST1Onev2d_POST, "st1", ".2d", 1, false, 16 },
563 { ARM64::ST1Onev8b_POST, "st1", ".8b", 1, false, 8 },
564 { ARM64::ST1Onev4h_POST, "st1", ".4h", 1, false, 8 },
565 { ARM64::ST1Onev2s_POST, "st1", ".2s", 1, false, 8 },
566 { ARM64::ST1Onev1d_POST, "st1", ".1d", 1, false, 8 },
567 { ARM64::ST1Twov16b, "st1", ".16b", 0, false, 0 },
568 { ARM64::ST1Twov8h, "st1", ".8h", 0, false, 0 },
569 { ARM64::ST1Twov4s, "st1", ".4s", 0, false, 0 },
570 { ARM64::ST1Twov2d, "st1", ".2d", 0, false, 0 },
571 { ARM64::ST1Twov8b, "st1", ".8b", 0, false, 0 },
572 { ARM64::ST1Twov4h, "st1", ".4h", 0, false, 0 },
573 { ARM64::ST1Twov2s, "st1", ".2s", 0, false, 0 },
574 { ARM64::ST1Twov1d, "st1", ".1d", 0, false, 0 },
575 { ARM64::ST1Twov16b_POST, "st1", ".16b", 1, false, 32 },
576 { ARM64::ST1Twov8h_POST, "st1", ".8h", 1, false, 32 },
577 { ARM64::ST1Twov4s_POST, "st1", ".4s", 1, false, 32 },
578 { ARM64::ST1Twov2d_POST, "st1", ".2d", 1, false, 32 },
579 { ARM64::ST1Twov8b_POST, "st1", ".8b", 1, false, 16 },
580 { ARM64::ST1Twov4h_POST, "st1", ".4h", 1, false, 16 },
581 { ARM64::ST1Twov2s_POST, "st1", ".2s", 1, false, 16 },
582 { ARM64::ST1Twov1d_POST, "st1", ".1d", 1, false, 16 },
583 { ARM64::ST1Threev16b, "st1", ".16b", 0, false, 0 },
584 { ARM64::ST1Threev8h, "st1", ".8h", 0, false, 0 },
585 { ARM64::ST1Threev4s, "st1", ".4s", 0, false, 0 },
586 { ARM64::ST1Threev2d, "st1", ".2d", 0, false, 0 },
587 { ARM64::ST1Threev8b, "st1", ".8b", 0, false, 0 },
588 { ARM64::ST1Threev4h, "st1", ".4h", 0, false, 0 },
589 { ARM64::ST1Threev2s, "st1", ".2s", 0, false, 0 },
590 { ARM64::ST1Threev1d, "st1", ".1d", 0, false, 0 },
591 { ARM64::ST1Threev16b_POST, "st1", ".16b", 1, false, 48 },
592 { ARM64::ST1Threev8h_POST, "st1", ".8h", 1, false, 48 },
593 { ARM64::ST1Threev4s_POST, "st1", ".4s", 1, false, 48 },
594 { ARM64::ST1Threev2d_POST, "st1", ".2d", 1, false, 48 },
595 { ARM64::ST1Threev8b_POST, "st1", ".8b", 1, false, 24 },
596 { ARM64::ST1Threev4h_POST, "st1", ".4h", 1, false, 24 },
597 { ARM64::ST1Threev2s_POST, "st1", ".2s", 1, false, 24 },
598 { ARM64::ST1Threev1d_POST, "st1", ".1d", 1, false, 24 },
599 { ARM64::ST1Fourv16b, "st1", ".16b", 0, false, 0 },
600 { ARM64::ST1Fourv8h, "st1", ".8h", 0, false, 0 },
601 { ARM64::ST1Fourv4s, "st1", ".4s", 0, false, 0 },
602 { ARM64::ST1Fourv2d, "st1", ".2d", 0, false, 0 },
603 { ARM64::ST1Fourv8b, "st1", ".8b", 0, false, 0 },
604 { ARM64::ST1Fourv4h, "st1", ".4h", 0, false, 0 },
605 { ARM64::ST1Fourv2s, "st1", ".2s", 0, false, 0 },
606 { ARM64::ST1Fourv1d, "st1", ".1d", 0, false, 0 },
607 { ARM64::ST1Fourv16b_POST, "st1", ".16b", 1, false, 64 },
608 { ARM64::ST1Fourv8h_POST, "st1", ".8h", 1, false, 64 },
609 { ARM64::ST1Fourv4s_POST, "st1", ".4s", 1, false, 64 },
610 { ARM64::ST1Fourv2d_POST, "st1", ".2d", 1, false, 64 },
611 { ARM64::ST1Fourv8b_POST, "st1", ".8b", 1, false, 32 },
612 { ARM64::ST1Fourv4h_POST, "st1", ".4h", 1, false, 32 },
613 { ARM64::ST1Fourv2s_POST, "st1", ".2s", 1, false, 32 },
614 { ARM64::ST1Fourv1d_POST, "st1", ".1d", 1, false, 32 },
615 { ARM64::ST2i8, "st2", ".b", 0, true, 0 },
616 { ARM64::ST2i16, "st2", ".h", 0, true, 0 },
617 { ARM64::ST2i32, "st2", ".s", 0, true, 0 },
618 { ARM64::ST2i64, "st2", ".d", 0, true, 0 },
619 { ARM64::ST2i8_POST, "st2", ".b", 1, true, 2 },
620 { ARM64::ST2i16_POST, "st2", ".h", 1, true, 4 },
621 { ARM64::ST2i32_POST, "st2", ".s", 1, true, 8 },
622 { ARM64::ST2i64_POST, "st2", ".d", 1, true, 16 },
623 { ARM64::ST2Twov16b, "st2", ".16b", 0, false, 0 },
624 { ARM64::ST2Twov8h, "st2", ".8h", 0, false, 0 },
625 { ARM64::ST2Twov4s, "st2", ".4s", 0, false, 0 },
626 { ARM64::ST2Twov2d, "st2", ".2d", 0, false, 0 },
627 { ARM64::ST2Twov8b, "st2", ".8b", 0, false, 0 },
628 { ARM64::ST2Twov4h, "st2", ".4h", 0, false, 0 },
629 { ARM64::ST2Twov2s, "st2", ".2s", 0, false, 0 },
630 { ARM64::ST2Twov16b_POST, "st2", ".16b", 1, false, 32 },
631 { ARM64::ST2Twov8h_POST, "st2", ".8h", 1, false, 32 },
632 { ARM64::ST2Twov4s_POST, "st2", ".4s", 1, false, 32 },
633 { ARM64::ST2Twov2d_POST, "st2", ".2d", 1, false, 32 },
634 { ARM64::ST2Twov8b_POST, "st2", ".8b", 1, false, 16 },
635 { ARM64::ST2Twov4h_POST, "st2", ".4h", 1, false, 16 },
636 { ARM64::ST2Twov2s_POST, "st2", ".2s", 1, false, 16 },
637 { ARM64::ST3i8, "st3", ".b", 0, true, 0 },
638 { ARM64::ST3i16, "st3", ".h", 0, true, 0 },
639 { ARM64::ST3i32, "st3", ".s", 0, true, 0 },
640 { ARM64::ST3i64, "st3", ".d", 0, true, 0 },
641 { ARM64::ST3i8_POST, "st3", ".b", 1, true, 3 },
642 { ARM64::ST3i16_POST, "st3", ".h", 1, true, 6 },
643 { ARM64::ST3i32_POST, "st3", ".s", 1, true, 12 },
644 { ARM64::ST3i64_POST, "st3", ".d", 1, true, 24 },
645 { ARM64::ST3Threev16b, "st3", ".16b", 0, false, 0 },
646 { ARM64::ST3Threev8h, "st3", ".8h", 0, false, 0 },
647 { ARM64::ST3Threev4s, "st3", ".4s", 0, false, 0 },
648 { ARM64::ST3Threev2d, "st3", ".2d", 0, false, 0 },
649 { ARM64::ST3Threev8b, "st3", ".8b", 0, false, 0 },
650 { ARM64::ST3Threev4h, "st3", ".4h", 0, false, 0 },
651 { ARM64::ST3Threev2s, "st3", ".2s", 0, false, 0 },
652 { ARM64::ST3Threev16b_POST, "st3", ".16b", 1, false, 48 },
653 { ARM64::ST3Threev8h_POST, "st3", ".8h", 1, false, 48 },
654 { ARM64::ST3Threev4s_POST, "st3", ".4s", 1, false, 48 },
655 { ARM64::ST3Threev2d_POST, "st3", ".2d", 1, false, 48 },
656 { ARM64::ST3Threev8b_POST, "st3", ".8b", 1, false, 24 },
657 { ARM64::ST3Threev4h_POST, "st3", ".4h", 1, false, 24 },
658 { ARM64::ST3Threev2s_POST, "st3", ".2s", 1, false, 24 },
659 { ARM64::ST4i8, "st4", ".b", 0, true, 0 },
660 { ARM64::ST4i16, "st4", ".h", 0, true, 0 },
661 { ARM64::ST4i32, "st4", ".s", 0, true, 0 },
662 { ARM64::ST4i64, "st4", ".d", 0, true, 0 },
663 { ARM64::ST4i8_POST, "st4", ".b", 1, true, 4 },
664 { ARM64::ST4i16_POST, "st4", ".h", 1, true, 8 },
665 { ARM64::ST4i32_POST, "st4", ".s", 1, true, 16 },
666 { ARM64::ST4i64_POST, "st4", ".d", 1, true, 32 },
667 { ARM64::ST4Fourv16b, "st4", ".16b", 0, false, 0 },
668 { ARM64::ST4Fourv8h, "st4", ".8h", 0, false, 0 },
669 { ARM64::ST4Fourv4s, "st4", ".4s", 0, false, 0 },
670 { ARM64::ST4Fourv2d, "st4", ".2d", 0, false, 0 },
671 { ARM64::ST4Fourv8b, "st4", ".8b", 0, false, 0 },
672 { ARM64::ST4Fourv4h, "st4", ".4h", 0, false, 0 },
673 { ARM64::ST4Fourv2s, "st4", ".2s", 0, false, 0 },
674 { ARM64::ST4Fourv16b_POST, "st4", ".16b", 1, false, 64 },
675 { ARM64::ST4Fourv8h_POST, "st4", ".8h", 1, false, 64 },
676 { ARM64::ST4Fourv4s_POST, "st4", ".4s", 1, false, 64 },
677 { ARM64::ST4Fourv2d_POST, "st4", ".2d", 1, false, 64 },
678 { ARM64::ST4Fourv8b_POST, "st4", ".8b", 1, false, 32 },
679 { ARM64::ST4Fourv4h_POST, "st4", ".4h", 1, false, 32 },
680 { ARM64::ST4Fourv2s_POST, "st4", ".2s", 1, false, 32 },
683 static LdStNInstrDesc *getLdStNInstrDesc(unsigned Opcode) {
685 for (Idx = 0; Idx != array_lengthof(LdStNInstInfo); ++Idx)
686 if (LdStNInstInfo[Idx].Opcode == Opcode)
687 return &LdStNInstInfo[Idx];
692 void ARM64AppleInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
694 unsigned Opcode = MI->getOpcode();
695 StringRef Layout, Mnemonic;
698 if (isTblTbxInstruction(MI->getOpcode(), Layout, IsTbx)) {
699 O << "\t" << (IsTbx ? "tbx" : "tbl") << Layout << '\t'
700 << getRegisterName(MI->getOperand(0).getReg(), ARM64::vreg) << ", ";
702 unsigned ListOpNum = IsTbx ? 2 : 1;
703 printVectorList(MI, ListOpNum, O, "");
706 << getRegisterName(MI->getOperand(ListOpNum + 1).getReg(), ARM64::vreg);
707 printAnnotation(O, Annot);
711 if (LdStNInstrDesc *LdStDesc = getLdStNInstrDesc(Opcode)) {
712 O << "\t" << LdStDesc->Mnemonic << LdStDesc->Layout << '\t';
714 // Now onto the operands: first a vector list with possible lane
715 // specifier. E.g. { v0 }[2]
716 int OpNum = LdStDesc->ListOperand;
717 printVectorList(MI, OpNum++, O, "");
719 if (LdStDesc->HasLane)
720 O << '[' << MI->getOperand(OpNum++).getImm() << ']';
722 // Next the address: [xN]
723 unsigned AddrReg = MI->getOperand(OpNum++).getReg();
724 O << ", [" << getRegisterName(AddrReg) << ']';
726 // Finally, there might be a post-indexed offset.
727 if (LdStDesc->NaturalOffset != 0) {
728 unsigned Reg = MI->getOperand(OpNum++).getReg();
729 if (Reg != ARM64::XZR)
730 O << ", " << getRegisterName(Reg);
732 assert(LdStDesc->NaturalOffset && "no offset on post-inc instruction?");
733 O << ", #" << LdStDesc->NaturalOffset;
737 printAnnotation(O, Annot);
741 ARM64InstPrinter::printInst(MI, O, Annot);
744 bool ARM64InstPrinter::printSysAlias(const MCInst *MI, raw_ostream &O) {
746 unsigned Opcode = MI->getOpcode();
747 assert(Opcode == ARM64::SYSxt && "Invalid opcode for SYS alias!");
750 const char *Asm = nullptr;
751 const MCOperand &Op1 = MI->getOperand(0);
752 const MCOperand &Cn = MI->getOperand(1);
753 const MCOperand &Cm = MI->getOperand(2);
754 const MCOperand &Op2 = MI->getOperand(3);
756 unsigned Op1Val = Op1.getImm();
757 unsigned CnVal = Cn.getImm();
758 unsigned CmVal = Cm.getImm();
759 unsigned Op2Val = Op2.getImm();
768 if (Op1Val == 0 && Op2Val == 0)
772 if (Op1Val == 0 && Op2Val == 0)
774 else if (Op1Val == 3 && Op2Val == 1)
780 if (Op1Val == 3 && Op2Val == 1)
784 if (Op1Val == 0 && Op2Val == 1)
786 if (Op1Val == 0 && Op2Val == 2)
790 if (Op1Val == 3 && Op2Val == 1)
792 else if (Op1Val == 0 && Op2Val == 2)
796 if (Op1Val == 3 && Op2Val == 1)
800 if (Op1Val == 3 && Op2Val == 1)
802 else if (Op1Val == 0 && Op2Val == 2)
815 case 0: Asm = "at\ts1e1r"; break;
816 case 1: Asm = "at\ts1e1w"; break;
817 case 2: Asm = "at\ts1e0r"; break;
818 case 3: Asm = "at\ts1e0w"; break;
825 case 0: Asm = "at\ts1e2r"; break;
826 case 1: Asm = "at\ts1e2w"; break;
827 case 4: Asm = "at\ts12e1r"; break;
828 case 5: Asm = "at\ts12e1w"; break;
829 case 6: Asm = "at\ts12e0r"; break;
830 case 7: Asm = "at\ts12e0w"; break;
837 case 0: Asm = "at\ts1e3r"; break;
838 case 1: Asm = "at\ts1e3w"; break;
844 } else if (CnVal == 8) {
857 case 0: Asm = "tlbi\tvmalle1is"; break;
858 case 1: Asm = "tlbi\tvae1is"; break;
859 case 2: Asm = "tlbi\taside1is"; break;
860 case 3: Asm = "tlbi\tvaae1is"; break;
861 case 5: Asm = "tlbi\tvale1is"; break;
862 case 7: Asm = "tlbi\tvaale1is"; break;
869 case 0: Asm = "tlbi\talle2is"; break;
870 case 1: Asm = "tlbi\tvae2is"; break;
871 case 4: Asm = "tlbi\talle1is"; break;
872 case 5: Asm = "tlbi\tvale2is"; break;
873 case 6: Asm = "tlbi\tvmalls12e1is"; break;
880 case 0: Asm = "tlbi\talle3is"; break;
881 case 1: Asm = "tlbi\tvae3is"; break;
882 case 5: Asm = "tlbi\tvale3is"; break;
895 case 1: Asm = "tlbi\tipas2e1is"; break;
896 case 5: Asm = "tlbi\tipas2le1is"; break;
909 case 1: Asm = "tlbi\tipas2e1"; break;
910 case 5: Asm = "tlbi\tipas2le1"; break;
923 case 0: Asm = "tlbi\tvmalle1"; break;
924 case 1: Asm = "tlbi\tvae1"; break;
925 case 2: Asm = "tlbi\taside1"; break;
926 case 3: Asm = "tlbi\tvaae1"; break;
927 case 5: Asm = "tlbi\tvale1"; break;
928 case 7: Asm = "tlbi\tvaale1"; break;
935 case 0: Asm = "tlbi\talle2"; break;
936 case 1: Asm = "tlbi\tvae2"; break;
937 case 4: Asm = "tlbi\talle1"; break;
938 case 5: Asm = "tlbi\tvale2"; break;
939 case 6: Asm = "tlbi\tvmalls12e1"; break;
946 case 0: Asm = "tlbi\talle3"; break;
947 case 1: Asm = "tlbi\tvae3"; break;
948 case 5: Asm = "tlbi\tvale3"; break;
957 unsigned Reg = MI->getOperand(4).getReg();
960 if (StringRef(Asm).lower().find("all") == StringRef::npos)
961 O << ", " << getRegisterName(Reg);
964 return Asm != nullptr;
967 void ARM64InstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
969 const MCOperand &Op = MI->getOperand(OpNo);
971 unsigned Reg = Op.getReg();
972 O << getRegisterName(Reg);
973 } else if (Op.isImm()) {
974 O << '#' << Op.getImm();
976 assert(Op.isExpr() && "unknown operand kind in printOperand");
981 void ARM64InstPrinter::printHexImm(const MCInst *MI, unsigned OpNo,
983 const MCOperand &Op = MI->getOperand(OpNo);
984 O << format("#%#llx", Op.getImm());
987 void ARM64InstPrinter::printPostIncOperand(const MCInst *MI, unsigned OpNo,
988 unsigned Imm, raw_ostream &O) {
989 const MCOperand &Op = MI->getOperand(OpNo);
991 unsigned Reg = Op.getReg();
992 if (Reg == ARM64::XZR)
995 O << getRegisterName(Reg);
997 assert(0 && "unknown operand kind in printPostIncOperand64");
1000 void ARM64InstPrinter::printVRegOperand(const MCInst *MI, unsigned OpNo,
1002 const MCOperand &Op = MI->getOperand(OpNo);
1003 assert(Op.isReg() && "Non-register vreg operand!");
1004 unsigned Reg = Op.getReg();
1005 O << getRegisterName(Reg, ARM64::vreg);
1008 void ARM64InstPrinter::printSysCROperand(const MCInst *MI, unsigned OpNo,
1010 const MCOperand &Op = MI->getOperand(OpNo);
1011 assert(Op.isImm() && "System instruction C[nm] operands must be immediates!");
1012 O << "c" << Op.getImm();
1015 void ARM64InstPrinter::printAddSubImm(const MCInst *MI, unsigned OpNum,
1017 const MCOperand &MO = MI->getOperand(OpNum);
1019 unsigned Val = (MO.getImm() & 0xfff);
1020 assert(Val == MO.getImm() && "Add/sub immediate out of range!");
1022 ARM64_AM::getShiftValue(MI->getOperand(OpNum + 1).getImm());
1025 printShifter(MI, OpNum + 1, O);
1028 *CommentStream << "=#" << (Val << Shift) << '\n';
1030 assert(MO.isExpr() && "Unexpected operand type!");
1032 printShifter(MI, OpNum + 1, O);
1036 void ARM64InstPrinter::printLogicalImm32(const MCInst *MI, unsigned OpNum,
1038 uint64_t Val = MI->getOperand(OpNum).getImm();
1040 O.write_hex(ARM64_AM::decodeLogicalImmediate(Val, 32));
1043 void ARM64InstPrinter::printLogicalImm64(const MCInst *MI, unsigned OpNum,
1045 uint64_t Val = MI->getOperand(OpNum).getImm();
1047 O.write_hex(ARM64_AM::decodeLogicalImmediate(Val, 64));
1050 void ARM64InstPrinter::printShifter(const MCInst *MI, unsigned OpNum,
1052 unsigned Val = MI->getOperand(OpNum).getImm();
1053 // LSL #0 should not be printed.
1054 if (ARM64_AM::getShiftType(Val) == ARM64_AM::LSL &&
1055 ARM64_AM::getShiftValue(Val) == 0)
1057 O << ", " << ARM64_AM::getShiftExtendName(ARM64_AM::getShiftType(Val)) << " #"
1058 << ARM64_AM::getShiftValue(Val);
1061 void ARM64InstPrinter::printShiftedRegister(const MCInst *MI, unsigned OpNum,
1063 O << getRegisterName(MI->getOperand(OpNum).getReg());
1064 printShifter(MI, OpNum + 1, O);
1067 void ARM64InstPrinter::printExtendedRegister(const MCInst *MI, unsigned OpNum,
1069 O << getRegisterName(MI->getOperand(OpNum).getReg());
1070 printExtend(MI, OpNum + 1, O);
1073 void ARM64InstPrinter::printExtend(const MCInst *MI, unsigned OpNum,
1075 unsigned Val = MI->getOperand(OpNum).getImm();
1076 ARM64_AM::ShiftExtendType ExtType = ARM64_AM::getArithExtendType(Val);
1077 unsigned ShiftVal = ARM64_AM::getArithShiftValue(Val);
1079 // If the destination or first source register operand is [W]SP, print
1080 // UXTW/UXTX as LSL, and if the shift amount is also zero, print nothing at
1082 if (ExtType == ARM64_AM::UXTW || ExtType == ARM64_AM::UXTX) {
1083 unsigned Dest = MI->getOperand(0).getReg();
1084 unsigned Src1 = MI->getOperand(1).getReg();
1085 if ( ((Dest == ARM64::SP || Src1 == ARM64::SP) &&
1086 ExtType == ARM64_AM::UXTX) ||
1087 ((Dest == ARM64::WSP || Src1 == ARM64::WSP) &&
1088 ExtType == ARM64_AM::UXTW) ) {
1090 O << ", lsl #" << ShiftVal;
1094 O << ", " << ARM64_AM::getShiftExtendName(ExtType);
1096 O << " #" << ShiftVal;
1099 void ARM64InstPrinter::printCondCode(const MCInst *MI, unsigned OpNum,
1101 ARM64CC::CondCode CC = (ARM64CC::CondCode)MI->getOperand(OpNum).getImm();
1102 O << ARM64CC::getCondCodeName(CC);
1105 void ARM64InstPrinter::printInverseCondCode(const MCInst *MI, unsigned OpNum,
1107 ARM64CC::CondCode CC = (ARM64CC::CondCode)MI->getOperand(OpNum).getImm();
1108 O << ARM64CC::getCondCodeName(ARM64CC::getInvertedCondCode(CC));
1111 void ARM64InstPrinter::printAMNoIndex(const MCInst *MI, unsigned OpNum,
1113 O << '[' << getRegisterName(MI->getOperand(OpNum).getReg()) << ']';
1117 void ARM64InstPrinter::printImmScale(const MCInst *MI, unsigned OpNum,
1119 O << '#' << Scale * MI->getOperand(OpNum).getImm();
1122 void ARM64InstPrinter::printAMIndexed(const MCInst *MI, unsigned OpNum,
1123 unsigned Scale, raw_ostream &O) {
1124 const MCOperand MO1 = MI->getOperand(OpNum + 1);
1125 O << '[' << getRegisterName(MI->getOperand(OpNum).getReg());
1127 if (MO1.getImm() != 0)
1128 O << ", #" << (MO1.getImm() * Scale);
1130 assert(MO1.isExpr() && "Unexpected operand type!");
1131 O << ", " << *MO1.getExpr();
1136 void ARM64InstPrinter::printAMIndexedWB(const MCInst *MI, unsigned OpNum,
1137 unsigned Scale, raw_ostream &O) {
1138 const MCOperand MO1 = MI->getOperand(OpNum + 1);
1139 O << '[' << getRegisterName(MI->getOperand(OpNum).getReg());
1141 O << ", #" << (MO1.getImm() * Scale);
1143 assert(MO1.isExpr() && "Unexpected operand type!");
1144 O << ", " << *MO1.getExpr();
1149 void ARM64InstPrinter::printPrefetchOp(const MCInst *MI, unsigned OpNum,
1151 unsigned prfop = MI->getOperand(OpNum).getImm();
1153 StringRef Name = ARM64PRFM::PRFMMapper().toString(prfop, Valid);
1160 void ARM64InstPrinter::printMemoryPostIndexed(const MCInst *MI, unsigned OpNum,
1161 raw_ostream &O, unsigned Scale) {
1162 O << '[' << getRegisterName(MI->getOperand(OpNum).getReg()) << ']' << ", #"
1163 << Scale * MI->getOperand(OpNum + 1).getImm();
1166 void ARM64InstPrinter::printMemoryRegOffset(const MCInst *MI, unsigned OpNum,
1167 raw_ostream &O, int Scale) {
1168 unsigned Val = MI->getOperand(OpNum + 2).getImm();
1169 ARM64_AM::ShiftExtendType ExtType = ARM64_AM::getMemExtendType(Val);
1171 O << '[' << getRegisterName(MI->getOperand(OpNum).getReg()) << ", ";
1172 if (ExtType == ARM64_AM::UXTW || ExtType == ARM64_AM::SXTW)
1173 O << getRegisterName(getWRegFromXReg(MI->getOperand(OpNum + 1).getReg()));
1175 O << getRegisterName(MI->getOperand(OpNum + 1).getReg());
1177 bool DoShift = ARM64_AM::getMemDoShift(Val);
1179 if (ExtType == ARM64_AM::UXTX) {
1183 O << ", " << ARM64_AM::getShiftExtendName(ExtType);
1186 O << " #" << Log2_32(Scale);
1191 void ARM64InstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
1193 const MCOperand &MO = MI->getOperand(OpNum);
1194 float FPImm = MO.isFPImm() ? MO.getFPImm() : ARM64_AM::getFPImmFloat(MO.getImm());
1196 // 8 decimal places are enough to perfectly represent permitted floats.
1197 O << format("#%.8f", FPImm);
1200 static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride = 1) {
1204 assert(0 && "Vector register expected!");
1205 case ARM64::Q0: Reg = ARM64::Q1; break;
1206 case ARM64::Q1: Reg = ARM64::Q2; break;
1207 case ARM64::Q2: Reg = ARM64::Q3; break;
1208 case ARM64::Q3: Reg = ARM64::Q4; break;
1209 case ARM64::Q4: Reg = ARM64::Q5; break;
1210 case ARM64::Q5: Reg = ARM64::Q6; break;
1211 case ARM64::Q6: Reg = ARM64::Q7; break;
1212 case ARM64::Q7: Reg = ARM64::Q8; break;
1213 case ARM64::Q8: Reg = ARM64::Q9; break;
1214 case ARM64::Q9: Reg = ARM64::Q10; break;
1215 case ARM64::Q10: Reg = ARM64::Q11; break;
1216 case ARM64::Q11: Reg = ARM64::Q12; break;
1217 case ARM64::Q12: Reg = ARM64::Q13; break;
1218 case ARM64::Q13: Reg = ARM64::Q14; break;
1219 case ARM64::Q14: Reg = ARM64::Q15; break;
1220 case ARM64::Q15: Reg = ARM64::Q16; break;
1221 case ARM64::Q16: Reg = ARM64::Q17; break;
1222 case ARM64::Q17: Reg = ARM64::Q18; break;
1223 case ARM64::Q18: Reg = ARM64::Q19; break;
1224 case ARM64::Q19: Reg = ARM64::Q20; break;
1225 case ARM64::Q20: Reg = ARM64::Q21; break;
1226 case ARM64::Q21: Reg = ARM64::Q22; break;
1227 case ARM64::Q22: Reg = ARM64::Q23; break;
1228 case ARM64::Q23: Reg = ARM64::Q24; break;
1229 case ARM64::Q24: Reg = ARM64::Q25; break;
1230 case ARM64::Q25: Reg = ARM64::Q26; break;
1231 case ARM64::Q26: Reg = ARM64::Q27; break;
1232 case ARM64::Q27: Reg = ARM64::Q28; break;
1233 case ARM64::Q28: Reg = ARM64::Q29; break;
1234 case ARM64::Q29: Reg = ARM64::Q30; break;
1235 case ARM64::Q30: Reg = ARM64::Q31; break;
1236 // Vector lists can wrap around.
1245 void ARM64InstPrinter::printVectorList(const MCInst *MI, unsigned OpNum,
1246 raw_ostream &O, StringRef LayoutSuffix) {
1247 unsigned Reg = MI->getOperand(OpNum).getReg();
1251 // Work out how many registers there are in the list (if there is an actual
1253 unsigned NumRegs = 1;
1254 if (MRI.getRegClass(ARM64::DDRegClassID).contains(Reg) ||
1255 MRI.getRegClass(ARM64::QQRegClassID).contains(Reg))
1257 else if (MRI.getRegClass(ARM64::DDDRegClassID).contains(Reg) ||
1258 MRI.getRegClass(ARM64::QQQRegClassID).contains(Reg))
1260 else if (MRI.getRegClass(ARM64::DDDDRegClassID).contains(Reg) ||
1261 MRI.getRegClass(ARM64::QQQQRegClassID).contains(Reg))
1264 // Now forget about the list and find out what the first register is.
1265 if (unsigned FirstReg = MRI.getSubReg(Reg, ARM64::dsub0))
1267 else if (unsigned FirstReg = MRI.getSubReg(Reg, ARM64::qsub0))
1270 // If it's a D-reg, we need to promote it to the equivalent Q-reg before
1271 // printing (otherwise getRegisterName fails).
1272 if (MRI.getRegClass(ARM64::FPR64RegClassID).contains(Reg)) {
1273 const MCRegisterClass &FPR128RC = MRI.getRegClass(ARM64::FPR128RegClassID);
1274 Reg = MRI.getMatchingSuperReg(Reg, ARM64::dsub, &FPR128RC);
1277 for (unsigned i = 0; i < NumRegs; ++i, Reg = getNextVectorRegister(Reg)) {
1278 O << getRegisterName(Reg, ARM64::vreg) << LayoutSuffix;
1279 if (i + 1 != NumRegs)
1286 void ARM64InstPrinter::printImplicitlyTypedVectorList(const MCInst *MI,
1289 printVectorList(MI, OpNum, O, "");
1292 template <unsigned NumLanes, char LaneKind>
1293 void ARM64InstPrinter::printTypedVectorList(const MCInst *MI, unsigned OpNum,
1295 std::string Suffix(".");
1297 Suffix += itostr(NumLanes) + LaneKind;
1301 printVectorList(MI, OpNum, O, Suffix);
1304 void ARM64InstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
1306 O << "[" << MI->getOperand(OpNum).getImm() << "]";
1309 void ARM64InstPrinter::printAlignedLabel(const MCInst *MI, unsigned OpNum,
1311 const MCOperand &Op = MI->getOperand(OpNum);
1313 // If the label has already been resolved to an immediate offset (say, when
1314 // we're running the disassembler), just print the immediate.
1316 O << "#" << (Op.getImm() << 2);
1320 // If the branch target is simply an address then print it in hex.
1321 const MCConstantExpr *BranchTarget =
1322 dyn_cast<MCConstantExpr>(MI->getOperand(OpNum).getExpr());
1324 if (BranchTarget && BranchTarget->EvaluateAsAbsolute(Address)) {
1326 O.write_hex(Address);
1328 // Otherwise, just print the expression.
1329 O << *MI->getOperand(OpNum).getExpr();
1333 void ARM64InstPrinter::printAdrpLabel(const MCInst *MI, unsigned OpNum,
1335 const MCOperand &Op = MI->getOperand(OpNum);
1337 // If the label has already been resolved to an immediate offset (say, when
1338 // we're running the disassembler), just print the immediate.
1340 O << "#" << (Op.getImm() << 12);
1344 // Otherwise, just print the expression.
1345 O << *MI->getOperand(OpNum).getExpr();
1348 void ARM64InstPrinter::printBarrierOption(const MCInst *MI, unsigned OpNo,
1350 unsigned Val = MI->getOperand(OpNo).getImm();
1351 unsigned Opcode = MI->getOpcode();
1355 if (Opcode == ARM64::ISB)
1356 Name = ARM64ISB::ISBMapper().toString(Val, Valid);
1358 Name = ARM64DB::DBarrierMapper().toString(Val, Valid);
1365 void ARM64InstPrinter::printMRSSystemRegister(const MCInst *MI, unsigned OpNo,
1367 unsigned Val = MI->getOperand(OpNo).getImm();
1370 auto Mapper = ARM64SysReg::MRSMapper(getAvailableFeatures());
1371 std::string Name = Mapper.toString(Val, Valid);
1374 O << StringRef(Name).upper();
1377 void ARM64InstPrinter::printMSRSystemRegister(const MCInst *MI, unsigned OpNo,
1379 unsigned Val = MI->getOperand(OpNo).getImm();
1382 auto Mapper = ARM64SysReg::MSRMapper(getAvailableFeatures());
1383 std::string Name = Mapper.toString(Val, Valid);
1386 O << StringRef(Name).upper();
1389 void ARM64InstPrinter::printSystemPStateField(const MCInst *MI, unsigned OpNo,
1391 unsigned Val = MI->getOperand(OpNo).getImm();
1394 StringRef Name = ARM64PState::PStateMapper().toString(Val, Valid);
1396 O << StringRef(Name.str()).upper();
1401 void ARM64InstPrinter::printSIMDType10Operand(const MCInst *MI, unsigned OpNo,
1403 unsigned RawVal = MI->getOperand(OpNo).getImm();
1404 uint64_t Val = ARM64_AM::decodeAdvSIMDModImmType10(RawVal);
1405 O << format("#%#016llx", Val);