lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp

   1 //===- ARM64Disassembler.cpp - Disassembler for ARM64 -----------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "ARM64Disassembler.h"
  14 #include "ARM64ExternalSymbolizer.h"
  15 #include "ARM64Subtarget.h"
  16 #include "MCTargetDesc/ARM64AddressingModes.h"
  17 #include "Utils/ARM64BaseInfo.h"
  18 #include "llvm/MC/MCInst.h"
  19 #include "llvm/MC/MCFixedLenDisassembler.h"
  20 #include "llvm/Support/Debug.h"
  21 #include "llvm/Support/MemoryObject.h"
  22 #include "llvm/Support/TargetRegistry.h"
  23 #include "llvm/Support/ErrorHandling.h"
  24
  25 using namespace llvm;
  26
  27 #define DEBUG_TYPE "arm64-disassembler"
  28
  29 // Pull DecodeStatus and its enum values into the global namespace.
  30 typedef llvm::MCDisassembler::DecodeStatus DecodeStatus;
  31
  32 // Forward declare these because the autogenerated code will reference them.
  33 // Definitions are further down.
  34 static DecodeStatus DecodeFPR128RegisterClass(llvm::MCInst &Inst,
  35                                               unsigned RegNo, uint64_t Address,
  36                                               const void *Decoder);
  37 static DecodeStatus DecodeFPR128_loRegisterClass(llvm::MCInst &Inst,
  38                                                  unsigned RegNo,
  39                                                  uint64_t Address,
  40                                                  const void *Decoder);
  41 static DecodeStatus DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  42                                              uint64_t Address,
  43                                              const void *Decoder);
  44 static DecodeStatus DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  45                                              uint64_t Address,
  46                                              const void *Decoder);
  47 static DecodeStatus DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  48                                              uint64_t Address,
  49                                              const void *Decoder);
  50 static DecodeStatus DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  51                                             uint64_t Address,
  52                                             const void *Decoder);
  53 static DecodeStatus DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  54                                              uint64_t Address,
  55                                              const void *Decoder);
  56 static DecodeStatus DecodeGPR64spRegisterClass(llvm::MCInst &Inst,
  57                                                unsigned RegNo, uint64_t Address,
  58                                                const void *Decoder);
  59 static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  60                                              uint64_t Address,
  61                                              const void *Decoder);
  62 static DecodeStatus DecodeGPR32spRegisterClass(llvm::MCInst &Inst,
  63                                                unsigned RegNo, uint64_t Address,
  64                                                const void *Decoder);
  65 static DecodeStatus DecodeQQRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  66                                           uint64_t Address,
  67                                           const void *Decoder);
  68 static DecodeStatus DecodeQQQRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  69                                            uint64_t Address,
  70                                            const void *Decoder);
  71 static DecodeStatus DecodeQQQQRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  72                                             uint64_t Address,
  73                                             const void *Decoder);
  74 static DecodeStatus DecodeDDRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  75                                           uint64_t Address,
  76                                           const void *Decoder);
  77 static DecodeStatus DecodeDDDRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  78                                            uint64_t Address,
  79                                            const void *Decoder);
  80 static DecodeStatus DecodeDDDDRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  81                                             uint64_t Address,
  82                                             const void *Decoder);
  83
  84 static DecodeStatus DecodeFixedPointScaleImm32(llvm::MCInst &Inst, unsigned Imm,
  85                                                uint64_t Address,
  86                                                const void *Decoder);
  87 static DecodeStatus DecodeFixedPointScaleImm64(llvm::MCInst &Inst, unsigned Imm,
  88                                                uint64_t Address,
  89                                                const void *Decoder);
  90 static DecodeStatus DecodePCRelLabel19(llvm::MCInst &Inst, unsigned Imm,
  91                                        uint64_t Address, const void *Decoder);
  92 static DecodeStatus DecodeMRSSystemRegister(llvm::MCInst &Inst, unsigned Imm,
  93                                             uint64_t Address, const void *Decoder);
  94 static DecodeStatus DecodeMSRSystemRegister(llvm::MCInst &Inst, unsigned Imm,
  95                                             uint64_t Address, const void *Decoder);
  96 static DecodeStatus DecodeThreeAddrSRegInstruction(llvm::MCInst &Inst,
  97                                                    uint32_t insn,
  98                                                    uint64_t Address,
  99                                                    const void *Decoder);
 100 static DecodeStatus DecodeMoveImmInstruction(llvm::MCInst &Inst, uint32_t insn,
 101                                              uint64_t Address,
 102                                              const void *Decoder);
 103 static DecodeStatus DecodeUnsignedLdStInstruction(llvm::MCInst &Inst,
 104                                                   uint32_t insn,
 105                                                   uint64_t Address,
 106                                                   const void *Decoder);
 107 static DecodeStatus DecodeSignedLdStInstruction(llvm::MCInst &Inst,
 108                                                 uint32_t insn, uint64_t Address,
 109                                                 const void *Decoder);
 110 static DecodeStatus DecodeExclusiveLdStInstruction(llvm::MCInst &Inst,
 111                                                    uint32_t insn,
 112                                                    uint64_t Address,
 113                                                    const void *Decoder);
 114 static DecodeStatus DecodePairLdStInstruction(llvm::MCInst &Inst, uint32_t insn,
 115                                               uint64_t Address,
 116                                               const void *Decoder);
 117 static DecodeStatus DecodeRegOffsetLdStInstruction(llvm::MCInst &Inst,
 118                                                    uint32_t insn,
 119                                                    uint64_t Address,
 120                                                    const void *Decoder);
 121 static DecodeStatus DecodeAddSubERegInstruction(llvm::MCInst &Inst,
 122                                                 uint32_t insn, uint64_t Address,
 123                                                 const void *Decoder);
 124 static DecodeStatus DecodeLogicalImmInstruction(llvm::MCInst &Inst,
 125                                                 uint32_t insn, uint64_t Address,
 126                                                 const void *Decoder);
 127 static DecodeStatus DecodeModImmInstruction(llvm::MCInst &Inst, uint32_t insn,
 128                                             uint64_t Address,
 129                                             const void *Decoder);
 130 static DecodeStatus DecodeModImmTiedInstruction(llvm::MCInst &Inst,
 131                                                 uint32_t insn, uint64_t Address,
 132                                                 const void *Decoder);
 133 static DecodeStatus DecodeAdrInstruction(llvm::MCInst &Inst, uint32_t insn,
 134                                          uint64_t Address, const void *Decoder);
 135 static DecodeStatus DecodeBaseAddSubImm(llvm::MCInst &Inst, uint32_t insn,
 136                                         uint64_t Address, const void *Decoder);
 137 static DecodeStatus DecodeUnconditionalBranch(llvm::MCInst &Inst, uint32_t insn,
 138                                               uint64_t Address,
 139                                               const void *Decoder);
 140 static DecodeStatus DecodeSystemPStateInstruction(llvm::MCInst &Inst,
 141                                                   uint32_t insn,
 142                                                   uint64_t Address,
 143                                                   const void *Decoder);
 144 static DecodeStatus DecodeTestAndBranch(llvm::MCInst &Inst, uint32_t insn,
 145                                         uint64_t Address, const void *Decoder);
 146
 147 static DecodeStatus DecodeVecShiftR64Imm(llvm::MCInst &Inst, unsigned Imm,
 148                                          uint64_t Addr, const void *Decoder);
 149 static DecodeStatus DecodeVecShiftR64ImmNarrow(llvm::MCInst &Inst, unsigned Imm,
 150                                                uint64_t Addr,
 151                                                const void *Decoder);
 152 static DecodeStatus DecodeVecShiftR32Imm(llvm::MCInst &Inst, unsigned Imm,
 153                                          uint64_t Addr, const void *Decoder);
 154 static DecodeStatus DecodeVecShiftR32ImmNarrow(llvm::MCInst &Inst, unsigned Imm,
 155                                                uint64_t Addr,
 156                                                const void *Decoder);
 157 static DecodeStatus DecodeVecShiftR16Imm(llvm::MCInst &Inst, unsigned Imm,
 158                                          uint64_t Addr, const void *Decoder);
 159 static DecodeStatus DecodeVecShiftR16ImmNarrow(llvm::MCInst &Inst, unsigned Imm,
 160                                                uint64_t Addr,
 161                                                const void *Decoder);
 162 static DecodeStatus DecodeVecShiftR8Imm(llvm::MCInst &Inst, unsigned Imm,
 163                                         uint64_t Addr, const void *Decoder);
 164 static DecodeStatus DecodeVecShiftL64Imm(llvm::MCInst &Inst, unsigned Imm,
 165                                          uint64_t Addr, const void *Decoder);
 166 static DecodeStatus DecodeVecShiftL32Imm(llvm::MCInst &Inst, unsigned Imm,
 167                                          uint64_t Addr, const void *Decoder);
 168 static DecodeStatus DecodeVecShiftL16Imm(llvm::MCInst &Inst, unsigned Imm,
 169                                          uint64_t Addr, const void *Decoder);
 170 static DecodeStatus DecodeVecShiftL8Imm(llvm::MCInst &Inst, unsigned Imm,
 171                                         uint64_t Addr, const void *Decoder);
 172
 173 #include "ARM64GenDisassemblerTables.inc"
 174 #include "ARM64GenInstrInfo.inc"
 175
 176 #define Success llvm::MCDisassembler::Success
 177 #define Fail llvm::MCDisassembler::Fail
 178
 179 static MCDisassembler *createARM64Disassembler(const Target &T,
 180                                                const MCSubtargetInfo &STI,
 181                                                MCContext &Ctx) {
 182   return new ARM64Disassembler(STI, Ctx);
 183 }
 184
 185 DecodeStatus ARM64Disassembler::getInstruction(MCInst &MI, uint64_t &Size,
 186                                                const MemoryObject &Region,
 187                                                uint64_t Address,
 188                                                raw_ostream &os,
 189                                                raw_ostream &cs) const {
 190   CommentStream = &cs;
 191
 192   uint8_t bytes[4];
 193
 194   Size = 0;
 195   // We want to read exactly 4 bytes of data.
 196   if (Region.readBytes(Address, 4, (uint8_t *)bytes) == -1)
 197     return Fail;
 198   Size = 4;
 199
 200   // Encoded as a small-endian 32-bit word in the stream.
 201   uint32_t insn =
 202       (bytes[3] << 24) | (bytes[2] << 16) | (bytes[1] << 8) | (bytes[0] << 0);
 203
 204   // Calling the auto-generated decoder function.
 205   DecodeStatus result =
 206       decodeInstruction(DecoderTable32, MI, insn, Address, this, STI);
 207   if (!result)
 208     return Fail;
 209
 210   return Success;
 211 }
 212
 213 static MCSymbolizer *
 214 createARM64ExternalSymbolizer(StringRef TT, LLVMOpInfoCallback GetOpInfo,
 215                               LLVMSymbolLookupCallback SymbolLookUp,
 216                               void *DisInfo, MCContext *Ctx,
 217                               MCRelocationInfo *RelInfo) {
 218   return new llvm::ARM64ExternalSymbolizer(
 219                                      *Ctx,
 220                                      std::unique_ptr<MCRelocationInfo>(RelInfo),
 221                                      GetOpInfo, SymbolLookUp, DisInfo);
 222 }
 223
 224 extern "C" void LLVMInitializeARM64Disassembler() {
 225   TargetRegistry::RegisterMCDisassembler(TheARM64leTarget,
 226                                          createARM64Disassembler);
 227   TargetRegistry::RegisterMCDisassembler(TheARM64beTarget,
 228                                          createARM64Disassembler);
 229   TargetRegistry::RegisterMCSymbolizer(TheARM64leTarget,
 230                                        createARM64ExternalSymbolizer);
 231   TargetRegistry::RegisterMCSymbolizer(TheARM64beTarget,
 232                                        createARM64ExternalSymbolizer);
 233 }
 234
 235 static const unsigned FPR128DecoderTable[] = {
 236   ARM64::Q0,  ARM64::Q1,  ARM64::Q2,  ARM64::Q3,  ARM64::Q4,  ARM64::Q5,
 237   ARM64::Q6,  ARM64::Q7,  ARM64::Q8,  ARM64::Q9,  ARM64::Q10, ARM64::Q11,
 238   ARM64::Q12, ARM64::Q13, ARM64::Q14, ARM64::Q15, ARM64::Q16, ARM64::Q17,
 239   ARM64::Q18, ARM64::Q19, ARM64::Q20, ARM64::Q21, ARM64::Q22, ARM64::Q23,
 240   ARM64::Q24, ARM64::Q25, ARM64::Q26, ARM64::Q27, ARM64::Q28, ARM64::Q29,
 241   ARM64::Q30, ARM64::Q31
 242 };
 243
 244 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo,
 245                                               uint64_t Addr,
 246                                               const void *Decoder) {
 247   if (RegNo > 31)
 248     return Fail;
 249
 250   unsigned Register = FPR128DecoderTable[RegNo];
 251   Inst.addOperand(MCOperand::CreateReg(Register));
 252   return Success;
 253 }
 254
 255 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo,
 256                                                  uint64_t Addr,
 257                                                  const void *Decoder) {
 258   if (RegNo > 15)
 259     return Fail;
 260   return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder);
 261 }
 262
 263 static const unsigned FPR64DecoderTable[] = {
 264   ARM64::D0,  ARM64::D1,  ARM64::D2,  ARM64::D3,  ARM64::D4,  ARM64::D5,
 265   ARM64::D6,  ARM64::D7,  ARM64::D8,  ARM64::D9,  ARM64::D10, ARM64::D11,
 266   ARM64::D12, ARM64::D13, ARM64::D14, ARM64::D15, ARM64::D16, ARM64::D17,
 267   ARM64::D18, ARM64::D19, ARM64::D20, ARM64::D21, ARM64::D22, ARM64::D23,
 268   ARM64::D24, ARM64::D25, ARM64::D26, ARM64::D27, ARM64::D28, ARM64::D29,
 269   ARM64::D30, ARM64::D31
 270 };
 271
 272 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
 273                                              uint64_t Addr,
 274                                              const void *Decoder) {
 275   if (RegNo > 31)
 276     return Fail;
 277
 278   unsigned Register = FPR64DecoderTable[RegNo];
 279   Inst.addOperand(MCOperand::CreateReg(Register));
 280   return Success;
 281 }
 282
 283 static const unsigned FPR32DecoderTable[] = {
 284   ARM64::S0,  ARM64::S1,  ARM64::S2,  ARM64::S3,  ARM64::S4,  ARM64::S5,
 285   ARM64::S6,  ARM64::S7,  ARM64::S8,  ARM64::S9,  ARM64::S10, ARM64::S11,
 286   ARM64::S12, ARM64::S13, ARM64::S14, ARM64::S15, ARM64::S16, ARM64::S17,
 287   ARM64::S18, ARM64::S19, ARM64::S20, ARM64::S21, ARM64::S22, ARM64::S23,
 288   ARM64::S24, ARM64::S25, ARM64::S26, ARM64::S27, ARM64::S28, ARM64::S29,
 289   ARM64::S30, ARM64::S31
 290 };
 291
 292 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
 293                                              uint64_t Addr,
 294                                              const void *Decoder) {
 295   if (RegNo > 31)
 296     return Fail;
 297
 298   unsigned Register = FPR32DecoderTable[RegNo];
 299   Inst.addOperand(MCOperand::CreateReg(Register));
 300   return Success;
 301 }
 302
 303 static const unsigned FPR16DecoderTable[] = {
 304   ARM64::H0,  ARM64::H1,  ARM64::H2,  ARM64::H3,  ARM64::H4,  ARM64::H5,
 305   ARM64::H6,  ARM64::H7,  ARM64::H8,  ARM64::H9,  ARM64::H10, ARM64::H11,
 306   ARM64::H12, ARM64::H13, ARM64::H14, ARM64::H15, ARM64::H16, ARM64::H17,
 307   ARM64::H18, ARM64::H19, ARM64::H20, ARM64::H21, ARM64::H22, ARM64::H23,
 308   ARM64::H24, ARM64::H25, ARM64::H26, ARM64::H27, ARM64::H28, ARM64::H29,
 309   ARM64::H30, ARM64::H31
 310 };
 311
 312 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
 313                                              uint64_t Addr,
 314                                              const void *Decoder) {
 315   if (RegNo > 31)
 316     return Fail;
 317
 318   unsigned Register = FPR16DecoderTable[RegNo];
 319   Inst.addOperand(MCOperand::CreateReg(Register));
 320   return Success;
 321 }
 322
 323 static const unsigned FPR8DecoderTable[] = {
 324   ARM64::B0,  ARM64::B1,  ARM64::B2,  ARM64::B3,  ARM64::B4,  ARM64::B5,
 325   ARM64::B6,  ARM64::B7,  ARM64::B8,  ARM64::B9,  ARM64::B10, ARM64::B11,
 326   ARM64::B12, ARM64::B13, ARM64::B14, ARM64::B15, ARM64::B16, ARM64::B17,
 327   ARM64::B18, ARM64::B19, ARM64::B20, ARM64::B21, ARM64::B22, ARM64::B23,
 328   ARM64::B24, ARM64::B25, ARM64::B26, ARM64::B27, ARM64::B28, ARM64::B29,
 329   ARM64::B30, ARM64::B31
 330 };
 331
 332 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
 333                                             uint64_t Addr,
 334                                             const void *Decoder) {
 335   if (RegNo > 31)
 336     return Fail;
 337
 338   unsigned Register = FPR8DecoderTable[RegNo];
 339   Inst.addOperand(MCOperand::CreateReg(Register));
 340   return Success;
 341 }
 342
 343 static const unsigned GPR64DecoderTable[] = {
 344   ARM64::X0,  ARM64::X1,  ARM64::X2,  ARM64::X3,  ARM64::X4,  ARM64::X5,
 345   ARM64::X6,  ARM64::X7,  ARM64::X8,  ARM64::X9,  ARM64::X10, ARM64::X11,
 346   ARM64::X12, ARM64::X13, ARM64::X14, ARM64::X15, ARM64::X16, ARM64::X17,
 347   ARM64::X18, ARM64::X19, ARM64::X20, ARM64::X21, ARM64::X22, ARM64::X23,
 348   ARM64::X24, ARM64::X25, ARM64::X26, ARM64::X27, ARM64::X28, ARM64::FP,
 349   ARM64::LR,  ARM64::XZR
 350 };
 351
 352 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
 353                                              uint64_t Addr,
 354                                              const void *Decoder) {
 355   if (RegNo > 31)
 356     return Fail;
 357
 358   unsigned Register = GPR64DecoderTable[RegNo];
 359   Inst.addOperand(MCOperand::CreateReg(Register));
 360   return Success;
 361 }
 362
 363 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo,
 364                                                uint64_t Addr,
 365                                                const void *Decoder) {
 366   if (RegNo > 31)
 367     return Fail;
 368   unsigned Register = GPR64DecoderTable[RegNo];
 369   if (Register == ARM64::XZR)
 370     Register = ARM64::SP;
 371   Inst.addOperand(MCOperand::CreateReg(Register));
 372   return Success;
 373 }
 374
 375 static const unsigned GPR32DecoderTable[] = {
 376   ARM64::W0,  ARM64::W1,  ARM64::W2,  ARM64::W3,  ARM64::W4,  ARM64::W5,
 377   ARM64::W6,  ARM64::W7,  ARM64::W8,  ARM64::W9,  ARM64::W10, ARM64::W11,
 378   ARM64::W12, ARM64::W13, ARM64::W14, ARM64::W15, ARM64::W16, ARM64::W17,
 379   ARM64::W18, ARM64::W19, ARM64::W20, ARM64::W21, ARM64::W22, ARM64::W23,
 380   ARM64::W24, ARM64::W25, ARM64::W26, ARM64::W27, ARM64::W28, ARM64::W29,
 381   ARM64::W30, ARM64::WZR
 382 };
 383
 384 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
 385                                              uint64_t Addr,
 386                                              const void *Decoder) {
 387   if (RegNo > 31)
 388     return Fail;
 389
 390   unsigned Register = GPR32DecoderTable[RegNo];
 391   Inst.addOperand(MCOperand::CreateReg(Register));
 392   return Success;
 393 }
 394
 395 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo,
 396                                                uint64_t Addr,
 397                                                const void *Decoder) {
 398   if (RegNo > 31)
 399     return Fail;
 400
 401   unsigned Register = GPR32DecoderTable[RegNo];
 402   if (Register == ARM64::WZR)
 403     Register = ARM64::WSP;
 404   Inst.addOperand(MCOperand::CreateReg(Register));
 405   return Success;
 406 }
 407
 408 static const unsigned VectorDecoderTable[] = {
 409   ARM64::Q0,  ARM64::Q1,  ARM64::Q2,  ARM64::Q3,  ARM64::Q4,  ARM64::Q5,
 410   ARM64::Q6,  ARM64::Q7,  ARM64::Q8,  ARM64::Q9,  ARM64::Q10, ARM64::Q11,
 411   ARM64::Q12, ARM64::Q13, ARM64::Q14, ARM64::Q15, ARM64::Q16, ARM64::Q17,
 412   ARM64::Q18, ARM64::Q19, ARM64::Q20, ARM64::Q21, ARM64::Q22, ARM64::Q23,
 413   ARM64::Q24, ARM64::Q25, ARM64::Q26, ARM64::Q27, ARM64::Q28, ARM64::Q29,
 414   ARM64::Q30, ARM64::Q31
 415 };
 416
 417 static DecodeStatus DecodeVectorRegisterClass(MCInst &Inst, unsigned RegNo,
 418                                               uint64_t Addr,
 419                                               const void *Decoder) {
 420   if (RegNo > 31)
 421     return Fail;
 422
 423   unsigned Register = VectorDecoderTable[RegNo];
 424   Inst.addOperand(MCOperand::CreateReg(Register));
 425   return Success;
 426 }
 427
 428 static const unsigned QQDecoderTable[] = {
 429   ARM64::Q0_Q1,   ARM64::Q1_Q2,   ARM64::Q2_Q3,   ARM64::Q3_Q4,
 430   ARM64::Q4_Q5,   ARM64::Q5_Q6,   ARM64::Q6_Q7,   ARM64::Q7_Q8,
 431   ARM64::Q8_Q9,   ARM64::Q9_Q10,  ARM64::Q10_Q11, ARM64::Q11_Q12,
 432   ARM64::Q12_Q13, ARM64::Q13_Q14, ARM64::Q14_Q15, ARM64::Q15_Q16,
 433   ARM64::Q16_Q17, ARM64::Q17_Q18, ARM64::Q18_Q19, ARM64::Q19_Q20,
 434   ARM64::Q20_Q21, ARM64::Q21_Q22, ARM64::Q22_Q23, ARM64::Q23_Q24,
 435   ARM64::Q24_Q25, ARM64::Q25_Q26, ARM64::Q26_Q27, ARM64::Q27_Q28,
 436   ARM64::Q28_Q29, ARM64::Q29_Q30, ARM64::Q30_Q31, ARM64::Q31_Q0
 437 };
 438
 439 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
 440                                           uint64_t Addr, const void *Decoder) {
 441   if (RegNo > 31)
 442     return Fail;
 443   unsigned Register = QQDecoderTable[RegNo];
 444   Inst.addOperand(MCOperand::CreateReg(Register));
 445   return Success;
 446 }
 447
 448 static const unsigned QQQDecoderTable[] = {
 449   ARM64::Q0_Q1_Q2,    ARM64::Q1_Q2_Q3,    ARM64::Q2_Q3_Q4,
 450   ARM64::Q3_Q4_Q5,    ARM64::Q4_Q5_Q6,    ARM64::Q5_Q6_Q7,
 451   ARM64::Q6_Q7_Q8,    ARM64::Q7_Q8_Q9,    ARM64::Q8_Q9_Q10,
 452   ARM64::Q9_Q10_Q11,  ARM64::Q10_Q11_Q12, ARM64::Q11_Q12_Q13,
 453   ARM64::Q12_Q13_Q14, ARM64::Q13_Q14_Q15, ARM64::Q14_Q15_Q16,
 454   ARM64::Q15_Q16_Q17, ARM64::Q16_Q17_Q18, ARM64::Q17_Q18_Q19,
 455   ARM64::Q18_Q19_Q20, ARM64::Q19_Q20_Q21, ARM64::Q20_Q21_Q22,
 456   ARM64::Q21_Q22_Q23, ARM64::Q22_Q23_Q24, ARM64::Q23_Q24_Q25,
 457   ARM64::Q24_Q25_Q26, ARM64::Q25_Q26_Q27, ARM64::Q26_Q27_Q28,
 458   ARM64::Q27_Q28_Q29, ARM64::Q28_Q29_Q30, ARM64::Q29_Q30_Q31,
 459   ARM64::Q30_Q31_Q0,  ARM64::Q31_Q0_Q1
 460 };
 461
 462 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo,
 463                                            uint64_t Addr, const void *Decoder) {
 464   if (RegNo > 31)
 465     return Fail;
 466   unsigned Register = QQQDecoderTable[RegNo];
 467   Inst.addOperand(MCOperand::CreateReg(Register));
 468   return Success;
 469 }
 470
 471 static const unsigned QQQQDecoderTable[] = {
 472   ARM64::Q0_Q1_Q2_Q3,     ARM64::Q1_Q2_Q3_Q4,     ARM64::Q2_Q3_Q4_Q5,
 473   ARM64::Q3_Q4_Q5_Q6,     ARM64::Q4_Q5_Q6_Q7,     ARM64::Q5_Q6_Q7_Q8,
 474   ARM64::Q6_Q7_Q8_Q9,     ARM64::Q7_Q8_Q9_Q10,    ARM64::Q8_Q9_Q10_Q11,
 475   ARM64::Q9_Q10_Q11_Q12,  ARM64::Q10_Q11_Q12_Q13, ARM64::Q11_Q12_Q13_Q14,
 476   ARM64::Q12_Q13_Q14_Q15, ARM64::Q13_Q14_Q15_Q16, ARM64::Q14_Q15_Q16_Q17,
 477   ARM64::Q15_Q16_Q17_Q18, ARM64::Q16_Q17_Q18_Q19, ARM64::Q17_Q18_Q19_Q20,
 478   ARM64::Q18_Q19_Q20_Q21, ARM64::Q19_Q20_Q21_Q22, ARM64::Q20_Q21_Q22_Q23,
 479   ARM64::Q21_Q22_Q23_Q24, ARM64::Q22_Q23_Q24_Q25, ARM64::Q23_Q24_Q25_Q26,
 480   ARM64::Q24_Q25_Q26_Q27, ARM64::Q25_Q26_Q27_Q28, ARM64::Q26_Q27_Q28_Q29,
 481   ARM64::Q27_Q28_Q29_Q30, ARM64::Q28_Q29_Q30_Q31, ARM64::Q29_Q30_Q31_Q0,
 482   ARM64::Q30_Q31_Q0_Q1,   ARM64::Q31_Q0_Q1_Q2
 483 };
 484
 485 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo,
 486                                             uint64_t Addr,
 487                                             const void *Decoder) {
 488   if (RegNo > 31)
 489     return Fail;
 490   unsigned Register = QQQQDecoderTable[RegNo];
 491   Inst.addOperand(MCOperand::CreateReg(Register));
 492   return Success;
 493 }
 494
 495 static const unsigned DDDecoderTable[] = {
 496   ARM64::D0_D1,   ARM64::D1_D2,   ARM64::D2_D3,   ARM64::D3_D4,
 497   ARM64::D4_D5,   ARM64::D5_D6,   ARM64::D6_D7,   ARM64::D7_D8,
 498   ARM64::D8_D9,   ARM64::D9_D10,  ARM64::D10_D11, ARM64::D11_D12,
 499   ARM64::D12_D13, ARM64::D13_D14, ARM64::D14_D15, ARM64::D15_D16,
 500   ARM64::D16_D17, ARM64::D17_D18, ARM64::D18_D19, ARM64::D19_D20,
 501   ARM64::D20_D21, ARM64::D21_D22, ARM64::D22_D23, ARM64::D23_D24,
 502   ARM64::D24_D25, ARM64::D25_D26, ARM64::D26_D27, ARM64::D27_D28,
 503   ARM64::D28_D29, ARM64::D29_D30, ARM64::D30_D31, ARM64::D31_D0
 504 };
 505
 506 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo,
 507                                           uint64_t Addr, const void *Decoder) {
 508   if (RegNo > 31)
 509     return Fail;
 510   unsigned Register = DDDecoderTable[RegNo];
 511   Inst.addOperand(MCOperand::CreateReg(Register));
 512   return Success;
 513 }
 514
 515 static const unsigned DDDDecoderTable[] = {
 516   ARM64::D0_D1_D2,    ARM64::D1_D2_D3,    ARM64::D2_D3_D4,
 517   ARM64::D3_D4_D5,    ARM64::D4_D5_D6,    ARM64::D5_D6_D7,
 518   ARM64::D6_D7_D8,    ARM64::D7_D8_D9,    ARM64::D8_D9_D10,
 519   ARM64::D9_D10_D11,  ARM64::D10_D11_D12, ARM64::D11_D12_D13,
 520   ARM64::D12_D13_D14, ARM64::D13_D14_D15, ARM64::D14_D15_D16,
 521   ARM64::D15_D16_D17, ARM64::D16_D17_D18, ARM64::D17_D18_D19,
 522   ARM64::D18_D19_D20, ARM64::D19_D20_D21, ARM64::D20_D21_D22,
 523   ARM64::D21_D22_D23, ARM64::D22_D23_D24, ARM64::D23_D24_D25,
 524   ARM64::D24_D25_D26, ARM64::D25_D26_D27, ARM64::D26_D27_D28,
 525   ARM64::D27_D28_D29, ARM64::D28_D29_D30, ARM64::D29_D30_D31,
 526   ARM64::D30_D31_D0,  ARM64::D31_D0_D1
 527 };
 528
 529 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo,
 530                                            uint64_t Addr, const void *Decoder) {
 531   if (RegNo > 31)
 532     return Fail;
 533   unsigned Register = DDDDecoderTable[RegNo];
 534   Inst.addOperand(MCOperand::CreateReg(Register));
 535   return Success;
 536 }
 537
 538 static const unsigned DDDDDecoderTable[] = {
 539   ARM64::D0_D1_D2_D3,     ARM64::D1_D2_D3_D4,     ARM64::D2_D3_D4_D5,
 540   ARM64::D3_D4_D5_D6,     ARM64::D4_D5_D6_D7,     ARM64::D5_D6_D7_D8,
 541   ARM64::D6_D7_D8_D9,     ARM64::D7_D8_D9_D10,    ARM64::D8_D9_D10_D11,
 542   ARM64::D9_D10_D11_D12,  ARM64::D10_D11_D12_D13, ARM64::D11_D12_D13_D14,
 543   ARM64::D12_D13_D14_D15, ARM64::D13_D14_D15_D16, ARM64::D14_D15_D16_D17,
 544   ARM64::D15_D16_D17_D18, ARM64::D16_D17_D18_D19, ARM64::D17_D18_D19_D20,
 545   ARM64::D18_D19_D20_D21, ARM64::D19_D20_D21_D22, ARM64::D20_D21_D22_D23,
 546   ARM64::D21_D22_D23_D24, ARM64::D22_D23_D24_D25, ARM64::D23_D24_D25_D26,
 547   ARM64::D24_D25_D26_D27, ARM64::D25_D26_D27_D28, ARM64::D26_D27_D28_D29,
 548   ARM64::D27_D28_D29_D30, ARM64::D28_D29_D30_D31, ARM64::D29_D30_D31_D0,
 549   ARM64::D30_D31_D0_D1,   ARM64::D31_D0_D1_D2
 550 };
 551
 552 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
 553                                             uint64_t Addr,
 554                                             const void *Decoder) {
 555   if (RegNo > 31)
 556     return Fail;
 557   unsigned Register = DDDDDecoderTable[RegNo];
 558   Inst.addOperand(MCOperand::CreateReg(Register));
 559   return Success;
 560 }
 561
 562 static DecodeStatus DecodeFixedPointScaleImm32(llvm::MCInst &Inst, unsigned Imm,
 563                                                uint64_t Addr,
 564                                                const void *Decoder) {
 565   // scale{5} is asserted as 1 in tblgen.
 566   Imm |= 0x20;
 567   Inst.addOperand(MCOperand::CreateImm(64 - Imm));
 568   return Success;
 569 }
 570
 571 static DecodeStatus DecodeFixedPointScaleImm64(llvm::MCInst &Inst, unsigned Imm,
 572                                                uint64_t Addr,
 573                                                const void *Decoder) {
 574   Inst.addOperand(MCOperand::CreateImm(64 - Imm));
 575   return Success;
 576 }
 577
 578 static DecodeStatus DecodePCRelLabel19(llvm::MCInst &Inst, unsigned Imm,
 579                                        uint64_t Addr, const void *Decoder) {
 580   int64_t ImmVal = Imm;
 581   const ARM64Disassembler *Dis =
 582       static_cast<const ARM64Disassembler *>(Decoder);
 583
 584   // Sign-extend 19-bit immediate.
 585   if (ImmVal & (1 << (19 - 1)))
 586     ImmVal |= ~((1LL << 19) - 1);
 587
 588   if (!Dis->tryAddingSymbolicOperand(Inst, ImmVal << 2, Addr,
 589                                      Inst.getOpcode() != ARM64::LDRXl, 0, 4))
 590     Inst.addOperand(MCOperand::CreateImm(ImmVal));
 591   return Success;
 592 }
 593
 594 static DecodeStatus DecodeMRSSystemRegister(llvm::MCInst &Inst, unsigned Imm,
 595                                             uint64_t Address,
 596                                             const void *Decoder) {
 597   const ARM64Disassembler *Dis =
 598       static_cast<const ARM64Disassembler *>(Decoder);
 599   const MCSubtargetInfo &STI = Dis->getSubtargetInfo();
 600
 601   Imm |= 0x8000;
 602   Inst.addOperand(MCOperand::CreateImm(Imm));
 603
 604   bool ValidNamed;
 605   (void)ARM64SysReg::MRSMapper(STI.getFeatureBits()).toString(Imm, ValidNamed);
 606
 607   return ValidNamed ? Success : Fail;
 608 }
 609
 610 static DecodeStatus DecodeMSRSystemRegister(llvm::MCInst &Inst, unsigned Imm,
 611                                             uint64_t Address,
 612                                             const void *Decoder) {
 613   const ARM64Disassembler *Dis =
 614       static_cast<const ARM64Disassembler *>(Decoder);
 615   const MCSubtargetInfo &STI = Dis->getSubtargetInfo();
 616
 617   Imm |= 0x8000;
 618   Inst.addOperand(MCOperand::CreateImm(Imm));
 619
 620   bool ValidNamed;
 621   (void)ARM64SysReg::MSRMapper(STI.getFeatureBits()).toString(Imm, ValidNamed);
 622
 623   return ValidNamed ? Success : Fail;
 624 }
 625
 626 static DecodeStatus DecodeVecShiftRImm(llvm::MCInst &Inst, unsigned Imm,
 627                                        unsigned Add) {
 628   Inst.addOperand(MCOperand::CreateImm(Add - Imm));
 629   return Success;
 630 }
 631
 632 static DecodeStatus DecodeVecShiftLImm(llvm::MCInst &Inst, unsigned Imm,
 633                                        unsigned Add) {
 634   Inst.addOperand(MCOperand::CreateImm((Imm + Add) & (Add - 1)));
 635   return Success;
 636 }
 637
 638 static DecodeStatus DecodeVecShiftR64Imm(llvm::MCInst &Inst, unsigned Imm,
 639                                          uint64_t Addr, const void *Decoder) {
 640   return DecodeVecShiftRImm(Inst, Imm, 64);
 641 }
 642
 643 static DecodeStatus DecodeVecShiftR64ImmNarrow(llvm::MCInst &Inst, unsigned Imm,
 644                                                uint64_t Addr,
 645                                                const void *Decoder) {
 646   return DecodeVecShiftRImm(Inst, Imm | 0x20, 64);
 647 }
 648
 649 static DecodeStatus DecodeVecShiftR32Imm(llvm::MCInst &Inst, unsigned Imm,
 650                                          uint64_t Addr, const void *Decoder) {
 651   return DecodeVecShiftRImm(Inst, Imm, 32);
 652 }
 653
 654 static DecodeStatus DecodeVecShiftR32ImmNarrow(llvm::MCInst &Inst, unsigned Imm,
 655                                                uint64_t Addr,
 656                                                const void *Decoder) {
 657   return DecodeVecShiftRImm(Inst, Imm | 0x10, 32);
 658 }
 659
 660 static DecodeStatus DecodeVecShiftR16Imm(llvm::MCInst &Inst, unsigned Imm,
 661                                          uint64_t Addr, const void *Decoder) {
 662   return DecodeVecShiftRImm(Inst, Imm, 16);
 663 }
 664
 665 static DecodeStatus DecodeVecShiftR16ImmNarrow(llvm::MCInst &Inst, unsigned Imm,
 666                                                uint64_t Addr,
 667                                                const void *Decoder) {
 668   return DecodeVecShiftRImm(Inst, Imm | 0x8, 16);
 669 }
 670
 671 static DecodeStatus DecodeVecShiftR8Imm(llvm::MCInst &Inst, unsigned Imm,
 672                                         uint64_t Addr, const void *Decoder) {
 673   return DecodeVecShiftRImm(Inst, Imm, 8);
 674 }
 675
 676 static DecodeStatus DecodeVecShiftL64Imm(llvm::MCInst &Inst, unsigned Imm,
 677                                          uint64_t Addr, const void *Decoder) {
 678   return DecodeVecShiftLImm(Inst, Imm, 64);
 679 }
 680
 681 static DecodeStatus DecodeVecShiftL32Imm(llvm::MCInst &Inst, unsigned Imm,
 682                                          uint64_t Addr, const void *Decoder) {
 683   return DecodeVecShiftLImm(Inst, Imm, 32);
 684 }
 685
 686 static DecodeStatus DecodeVecShiftL16Imm(llvm::MCInst &Inst, unsigned Imm,
 687                                          uint64_t Addr, const void *Decoder) {
 688   return DecodeVecShiftLImm(Inst, Imm, 16);
 689 }
 690
 691 static DecodeStatus DecodeVecShiftL8Imm(llvm::MCInst &Inst, unsigned Imm,
 692                                         uint64_t Addr, const void *Decoder) {
 693   return DecodeVecShiftLImm(Inst, Imm, 8);
 694 }
 695
 696 static DecodeStatus DecodeThreeAddrSRegInstruction(llvm::MCInst &Inst,
 697                                                    uint32_t insn, uint64_t Addr,
 698                                                    const void *Decoder) {
 699   unsigned Rd = fieldFromInstruction(insn, 0, 5);
 700   unsigned Rn = fieldFromInstruction(insn, 5, 5);
 701   unsigned Rm = fieldFromInstruction(insn, 16, 5);
 702   unsigned shiftHi = fieldFromInstruction(insn, 22, 2);
 703   unsigned shiftLo = fieldFromInstruction(insn, 10, 6);
 704   unsigned shift = (shiftHi << 6) | shiftLo;
 705   switch (Inst.getOpcode()) {
 706   default:
 707     return Fail;
 708   case ARM64::ADDWrs:
 709   case ARM64::ADDSWrs:
 710   case ARM64::SUBWrs:
 711   case ARM64::SUBSWrs:
 712     // if shift == '11' then ReservedValue()
 713     if (shiftHi == 0x3)
 714       return Fail;
 715     // Deliberate fallthrough
 716   case ARM64::ANDWrs:
 717   case ARM64::ANDSWrs:
 718   case ARM64::BICWrs:
 719   case ARM64::BICSWrs:
 720   case ARM64::ORRWrs:
 721   case ARM64::ORNWrs:
 722   case ARM64::EORWrs:
 723   case ARM64::EONWrs: {
 724     // if sf == '0' and imm6<5> == '1' then ReservedValue()
 725     if (shiftLo >> 5 == 1)
 726       return Fail;
 727     DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
 728     DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
 729     DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
 730     break;
 731   }
 732   case ARM64::ADDXrs:
 733   case ARM64::ADDSXrs:
 734   case ARM64::SUBXrs:
 735   case ARM64::SUBSXrs:
 736     // if shift == '11' then ReservedValue()
 737     if (shiftHi == 0x3)
 738       return Fail;
 739     // Deliberate fallthrough
 740   case ARM64::ANDXrs:
 741   case ARM64::ANDSXrs:
 742   case ARM64::BICXrs:
 743   case ARM64::BICSXrs:
 744   case ARM64::ORRXrs:
 745   case ARM64::ORNXrs:
 746   case ARM64::EORXrs:
 747   case ARM64::EONXrs:
 748     DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
 749     DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
 750     DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
 751     break;
 752   }
 753
 754   Inst.addOperand(MCOperand::CreateImm(shift));
 755   return Success;
 756 }
 757
 758 static DecodeStatus DecodeMoveImmInstruction(llvm::MCInst &Inst, uint32_t insn,
 759                                              uint64_t Addr,
 760                                              const void *Decoder) {
 761   unsigned Rd = fieldFromInstruction(insn, 0, 5);
 762   unsigned imm = fieldFromInstruction(insn, 5, 16);
 763   unsigned shift = fieldFromInstruction(insn, 21, 2);
 764   shift <<= 4;
 765   switch (Inst.getOpcode()) {
 766   default:
 767     return Fail;
 768   case ARM64::MOVZWi:
 769   case ARM64::MOVNWi:
 770   case ARM64::MOVKWi:
 771     if (shift & (1U << 5))
 772       return Fail;
 773     DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
 774     break;
 775   case ARM64::MOVZXi:
 776   case ARM64::MOVNXi:
 777   case ARM64::MOVKXi:
 778     DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
 779     break;
 780   }
 781
 782   if (Inst.getOpcode() == ARM64::MOVKWi || Inst.getOpcode() == ARM64::MOVKXi)
 783     Inst.addOperand(Inst.getOperand(0));
 784
 785   Inst.addOperand(MCOperand::CreateImm(imm));
 786   Inst.addOperand(MCOperand::CreateImm(shift));
 787   return Success;
 788 }
 789
 790 static DecodeStatus DecodeUnsignedLdStInstruction(llvm::MCInst &Inst,
 791                                                   uint32_t insn, uint64_t Addr,
 792                                                   const void *Decoder) {
 793   unsigned Rt = fieldFromInstruction(insn, 0, 5);
 794   unsigned Rn = fieldFromInstruction(insn, 5, 5);
 795   unsigned offset = fieldFromInstruction(insn, 10, 12);
 796   const ARM64Disassembler *Dis =
 797       static_cast<const ARM64Disassembler *>(Decoder);
 798
 799   switch (Inst.getOpcode()) {
 800   default:
 801     return Fail;
 802   case ARM64::PRFMui:
 803     // Rt is an immediate in prefetch.
 804     Inst.addOperand(MCOperand::CreateImm(Rt));
 805     break;
 806   case ARM64::STRBBui:
 807   case ARM64::LDRBBui:
 808   case ARM64::LDRSBWui:
 809   case ARM64::STRHHui:
 810   case ARM64::LDRHHui:
 811   case ARM64::LDRSHWui:
 812   case ARM64::STRWui:
 813   case ARM64::LDRWui:
 814     DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
 815     break;
 816   case ARM64::LDRSBXui:
 817   case ARM64::LDRSHXui:
 818   case ARM64::LDRSWui:
 819   case ARM64::STRXui:
 820   case ARM64::LDRXui:
 821     DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
 822     break;
 823   case ARM64::LDRQui:
 824   case ARM64::STRQui:
 825     DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
 826     break;
 827   case ARM64::LDRDui:
 828   case ARM64::STRDui:
 829     DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
 830     break;
 831   case ARM64::LDRSui:
 832   case ARM64::STRSui:
 833     DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
 834     break;
 835   case ARM64::LDRHui:
 836   case ARM64::STRHui:
 837     DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
 838     break;
 839   case ARM64::LDRBui:
 840   case ARM64::STRBui:
 841     DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
 842     break;
 843   }
 844
 845   DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
 846   if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4))
 847     Inst.addOperand(MCOperand::CreateImm(offset));
 848   return Success;
 849 }
 850
 851 static DecodeStatus DecodeSignedLdStInstruction(llvm::MCInst &Inst,
 852                                                 uint32_t insn, uint64_t Addr,
 853                                                 const void *Decoder) {
 854   unsigned Rt = fieldFromInstruction(insn, 0, 5);
 855   unsigned Rn = fieldFromInstruction(insn, 5, 5);
 856   int64_t offset = fieldFromInstruction(insn, 12, 9);
 857
 858   // offset is a 9-bit signed immediate, so sign extend it to
 859   // fill the unsigned.
 860   if (offset & (1 << (9 - 1)))
 861     offset |= ~((1LL << 9) - 1);
 862
 863   switch (Inst.getOpcode()) {
 864   default:
 865     return Fail;
 866   case ARM64::PRFUMi:
 867     // Rt is an immediate in prefetch.
 868     Inst.addOperand(MCOperand::CreateImm(Rt));
 869     break;
 870   case ARM64::STURBBi:
 871   case ARM64::LDURBBi:
 872   case ARM64::LDURSBWi:
 873   case ARM64::STURHHi:
 874   case ARM64::LDURHHi:
 875   case ARM64::LDURSHWi:
 876   case ARM64::STURWi:
 877   case ARM64::LDURWi:
 878   case ARM64::LDTRSBWi:
 879   case ARM64::LDTRSHWi:
 880   case ARM64::STTRWi:
 881   case ARM64::LDTRWi:
 882   case ARM64::STTRHi:
 883   case ARM64::LDTRHi:
 884   case ARM64::LDTRBi:
 885   case ARM64::STTRBi:
 886   case ARM64::LDRSBWpre:
 887   case ARM64::LDRSHWpre:
 888   case ARM64::STRBBpre:
 889   case ARM64::LDRBBpre:
 890   case ARM64::STRHHpre:
 891   case ARM64::LDRHHpre:
 892   case ARM64::STRWpre:
 893   case ARM64::LDRWpre:
 894   case ARM64::LDRSBWpost:
 895   case ARM64::LDRSHWpost:
 896   case ARM64::STRBBpost:
 897   case ARM64::LDRBBpost:
 898   case ARM64::STRHHpost:
 899   case ARM64::LDRHHpost:
 900   case ARM64::STRWpost:
 901   case ARM64::LDRWpost:
 902     DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
 903     break;
 904   case ARM64::LDURSBXi:
 905   case ARM64::LDURSHXi:
 906   case ARM64::LDURSWi:
 907   case ARM64::STURXi:
 908   case ARM64::LDURXi:
 909   case ARM64::LDTRSBXi:
 910   case ARM64::LDTRSHXi:
 911   case ARM64::LDTRSWi:
 912   case ARM64::STTRXi:
 913   case ARM64::LDTRXi:
 914   case ARM64::LDRSBXpre:
 915   case ARM64::LDRSHXpre:
 916   case ARM64::STRXpre:
 917   case ARM64::LDRSWpre:
 918   case ARM64::LDRXpre:
 919   case ARM64::LDRSBXpost:
 920   case ARM64::LDRSHXpost:
 921   case ARM64::STRXpost:
 922   case ARM64::LDRSWpost:
 923   case ARM64::LDRXpost:
 924     DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
 925     break;
 926   case ARM64::LDURQi:
 927   case ARM64::STURQi:
 928   case ARM64::LDRQpre:
 929   case ARM64::STRQpre:
 930   case ARM64::LDRQpost:
 931   case ARM64::STRQpost:
 932     DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
 933     break;
 934   case ARM64::LDURDi:
 935   case ARM64::STURDi:
 936   case ARM64::LDRDpre:
 937   case ARM64::STRDpre:
 938   case ARM64::LDRDpost:
 939   case ARM64::STRDpost:
 940     DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
 941     break;
 942   case ARM64::LDURSi:
 943   case ARM64::STURSi:
 944   case ARM64::LDRSpre:
 945   case ARM64::STRSpre:
 946   case ARM64::LDRSpost:
 947   case ARM64::STRSpost:
 948     DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
 949     break;
 950   case ARM64::LDURHi:
 951   case ARM64::STURHi:
 952   case ARM64::LDRHpre:
 953   case ARM64::STRHpre:
 954   case ARM64::LDRHpost:
 955   case ARM64::STRHpost:
 956     DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
 957     break;
 958   case ARM64::LDURBi:
 959   case ARM64::STURBi:
 960   case ARM64::LDRBpre:
 961   case ARM64::STRBpre:
 962   case ARM64::LDRBpost:
 963   case ARM64::STRBpost:
 964     DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
 965     break;
 966   }
 967
 968   DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
 969   Inst.addOperand(MCOperand::CreateImm(offset));
 970   return Success;
 971 }
 972
 973 static DecodeStatus DecodeExclusiveLdStInstruction(llvm::MCInst &Inst,
 974                                                    uint32_t insn, uint64_t Addr,
 975                                                    const void *Decoder) {
 976   unsigned Rt = fieldFromInstruction(insn, 0, 5);
 977   unsigned Rn = fieldFromInstruction(insn, 5, 5);
 978   unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
 979   unsigned Rs = fieldFromInstruction(insn, 16, 5);
 980
 981   switch (Inst.getOpcode()) {
 982   default:
 983     return Fail;
 984   case ARM64::STLXRW:
 985   case ARM64::STLXRB:
 986   case ARM64::STLXRH:
 987   case ARM64::STXRW:
 988   case ARM64::STXRB:
 989   case ARM64::STXRH:
 990     DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
 991   // FALLTHROUGH
 992   case ARM64::LDARW:
 993   case ARM64::LDARB:
 994   case ARM64::LDARH:
 995   case ARM64::LDAXRW:
 996   case ARM64::LDAXRB:
 997   case ARM64::LDAXRH:
 998   case ARM64::LDXRW:
 999   case ARM64::LDXRB:
1000   case ARM64::LDXRH:
1001   case ARM64::STLRW:
1002   case ARM64::STLRB:
1003   case ARM64::STLRH:
1004     DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1005     break;
1006   case ARM64::STLXRX:
1007   case ARM64::STXRX:
1008     DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1009   // FALLTHROUGH
1010   case ARM64::LDARX:
1011   case ARM64::LDAXRX:
1012   case ARM64::LDXRX:
1013   case ARM64::STLRX:
1014     DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1015     break;
1016   case ARM64::STLXPW:
1017   case ARM64::STXPW:
1018     DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1019   // FALLTHROUGH
1020   case ARM64::LDAXPW:
1021   case ARM64::LDXPW:
1022     DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1023     DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1024     break;
1025   case ARM64::STLXPX:
1026   case ARM64::STXPX:
1027     DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1028   // FALLTHROUGH
1029   case ARM64::LDAXPX:
1030   case ARM64::LDXPX:
1031     DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1032     DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1033     break;
1034   }
1035
1036   DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1037   return Success;
1038 }
1039
1040 static DecodeStatus DecodePairLdStInstruction(llvm::MCInst &Inst, uint32_t insn,
1041                                               uint64_t Addr,
1042                                               const void *Decoder) {
1043   unsigned Rt = fieldFromInstruction(insn, 0, 5);
1044   unsigned Rn = fieldFromInstruction(insn, 5, 5);
1045   unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1046   int64_t offset = fieldFromInstruction(insn, 15, 7);
1047
1048   // offset is a 7-bit signed immediate, so sign extend it to
1049   // fill the unsigned.
1050   if (offset & (1 << (7 - 1)))
1051     offset |= ~((1LL << 7) - 1);
1052
1053   switch (Inst.getOpcode()) {
1054   default:
1055     return Fail;
1056   case ARM64::LDNPXi:
1057   case ARM64::STNPXi:
1058   case ARM64::LDPXpost:
1059   case ARM64::STPXpost:
1060   case ARM64::LDPSWpost:
1061   case ARM64::LDPXi:
1062   case ARM64::STPXi:
1063   case ARM64::LDPSWi:
1064   case ARM64::LDPXpre:
1065   case ARM64::STPXpre:
1066   case ARM64::LDPSWpre:
1067     DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1068     DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1069     break;
1070   case ARM64::LDNPWi:
1071   case ARM64::STNPWi:
1072   case ARM64::LDPWpost:
1073   case ARM64::STPWpost:
1074   case ARM64::LDPWi:
1075   case ARM64::STPWi:
1076   case ARM64::LDPWpre:
1077   case ARM64::STPWpre:
1078     DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1079     DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1080     break;
1081   case ARM64::LDNPQi:
1082   case ARM64::STNPQi:
1083   case ARM64::LDPQpost:
1084   case ARM64::STPQpost:
1085   case ARM64::LDPQi:
1086   case ARM64::STPQi:
1087   case ARM64::LDPQpre:
1088   case ARM64::STPQpre:
1089     DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1090     DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder);
1091     break;
1092   case ARM64::LDNPDi:
1093   case ARM64::STNPDi:
1094   case ARM64::LDPDpost:
1095   case ARM64::STPDpost:
1096   case ARM64::LDPDi:
1097   case ARM64::STPDi:
1098   case ARM64::LDPDpre:
1099   case ARM64::STPDpre:
1100     DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1101     DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1102     break;
1103   case ARM64::LDNPSi:
1104   case ARM64::STNPSi:
1105   case ARM64::LDPSpost:
1106   case ARM64::STPSpost:
1107   case ARM64::LDPSi:
1108   case ARM64::STPSi:
1109   case ARM64::LDPSpre:
1110   case ARM64::STPSpre:
1111     DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1112     DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1113     break;
1114   }
1115
1116   DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1117   Inst.addOperand(MCOperand::CreateImm(offset));
1118   return Success;
1119 }
1120
1121 static DecodeStatus DecodeRegOffsetLdStInstruction(llvm::MCInst &Inst,
1122                                                    uint32_t insn, uint64_t Addr,
1123                                                    const void *Decoder) {
1124   unsigned Rt = fieldFromInstruction(insn, 0, 5);
1125   unsigned Rn = fieldFromInstruction(insn, 5, 5);
1126   unsigned Rm = fieldFromInstruction(insn, 16, 5);
1127   unsigned extendHi = fieldFromInstruction(insn, 13, 3);
1128   unsigned extendLo = fieldFromInstruction(insn, 12, 1);
1129   unsigned extend = (extendHi << 1) | extendLo;
1130
1131   // All RO load-store instructions are undefined if option == 00x or 10x.
1132   if (extend >> 2 == 0x0 || extend >> 2 == 0x2)
1133     return Fail;
1134
1135   switch (Inst.getOpcode()) {
1136   default:
1137     return Fail;
1138   case ARM64::LDRSWro:
1139     DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1140     break;
1141   case ARM64::LDRXro:
1142   case ARM64::STRXro:
1143     DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1144     break;
1145   case ARM64::LDRWro:
1146   case ARM64::STRWro:
1147     DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1148     break;
1149   case ARM64::LDRQro:
1150   case ARM64::STRQro:
1151     DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1152     break;
1153   case ARM64::LDRDro:
1154   case ARM64::STRDro:
1155     DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1156     break;
1157   case ARM64::LDRSro:
1158   case ARM64::STRSro:
1159     DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1160     break;
1161   case ARM64::LDRHro:
1162   case ARM64::STRHro:
1163     DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
1164     break;
1165   case ARM64::LDRBro:
1166   case ARM64::STRBro:
1167     DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
1168     break;
1169   case ARM64::LDRBBro:
1170   case ARM64::STRBBro:
1171   case ARM64::LDRSBWro:
1172     DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1173     break;
1174   case ARM64::LDRHHro:
1175   case ARM64::STRHHro:
1176   case ARM64::LDRSHWro:
1177     DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1178     break;
1179   case ARM64::LDRSHXro:
1180     DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1181     break;
1182   case ARM64::LDRSBXro:
1183     DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1184     break;
1185   case ARM64::PRFMro:
1186     Inst.addOperand(MCOperand::CreateImm(Rt));
1187   }
1188
1189   DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1190   DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1191
1192   Inst.addOperand(MCOperand::CreateImm(extend));
1193   return Success;
1194 }
1195
1196 static DecodeStatus DecodeAddSubERegInstruction(llvm::MCInst &Inst,
1197                                                 uint32_t insn, uint64_t Addr,
1198                                                 const void *Decoder) {
1199   unsigned Rd = fieldFromInstruction(insn, 0, 5);
1200   unsigned Rn = fieldFromInstruction(insn, 5, 5);
1201   unsigned Rm = fieldFromInstruction(insn, 16, 5);
1202   unsigned extend = fieldFromInstruction(insn, 10, 6);
1203
1204   unsigned shift = extend & 0x7;
1205   if (shift > 4)
1206     return Fail;
1207
1208   switch (Inst.getOpcode()) {
1209   default:
1210     return Fail;
1211   case ARM64::ADDWrx:
1212   case ARM64::SUBWrx:
1213     DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1214     DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1215     DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1216     break;
1217   case ARM64::ADDSWrx:
1218   case ARM64::SUBSWrx:
1219     DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1220     DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1221     DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1222     break;
1223   case ARM64::ADDXrx:
1224   case ARM64::SUBXrx:
1225     DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1226     DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1227     DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1228     break;
1229   case ARM64::ADDSXrx:
1230   case ARM64::SUBSXrx:
1231     DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1232     DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1233     DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1234     break;
1235   case ARM64::ADDXrx64:
1236   case ARM64::SUBXrx64:
1237     DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1238     DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1239     DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1240     break;
1241   case ARM64::SUBSXrx64:
1242   case ARM64::ADDSXrx64:
1243     DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1244     DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1245     DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1246     break;
1247   }
1248
1249   Inst.addOperand(MCOperand::CreateImm(extend));
1250   return Success;
1251 }
1252
1253 static DecodeStatus DecodeLogicalImmInstruction(llvm::MCInst &Inst,
1254                                                 uint32_t insn, uint64_t Addr,
1255                                                 const void *Decoder) {
1256   unsigned Rd = fieldFromInstruction(insn, 0, 5);
1257   unsigned Rn = fieldFromInstruction(insn, 5, 5);
1258   unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1259   unsigned imm;
1260
1261   if (Datasize) {
1262     if (Inst.getOpcode() == ARM64::ANDSXri)
1263       DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1264     else
1265       DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1266     DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
1267     imm = fieldFromInstruction(insn, 10, 13);
1268     if (!ARM64_AM::isValidDecodeLogicalImmediate(imm, 64))
1269       return Fail;
1270   } else {
1271     if (Inst.getOpcode() == ARM64::ANDSWri)
1272       DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1273     else
1274       DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1275     DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
1276     imm = fieldFromInstruction(insn, 10, 12);
1277     if (!ARM64_AM::isValidDecodeLogicalImmediate(imm, 32))
1278       return Fail;
1279   }
1280   Inst.addOperand(MCOperand::CreateImm(imm));
1281   return Success;
1282 }
1283
1284 static DecodeStatus DecodeModImmInstruction(llvm::MCInst &Inst, uint32_t insn,
1285                                             uint64_t Addr,
1286                                             const void *Decoder) {
1287   unsigned Rd = fieldFromInstruction(insn, 0, 5);
1288   unsigned cmode = fieldFromInstruction(insn, 12, 4);
1289   unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1290   imm |= fieldFromInstruction(insn, 5, 5);
1291
1292   if (Inst.getOpcode() == ARM64::MOVID)
1293     DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder);
1294   else
1295     DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1296
1297   Inst.addOperand(MCOperand::CreateImm(imm));
1298
1299   switch (Inst.getOpcode()) {
1300   default:
1301     break;
1302   case ARM64::MOVIv4i16:
1303   case ARM64::MOVIv8i16:
1304   case ARM64::MVNIv4i16:
1305   case ARM64::MVNIv8i16:
1306   case ARM64::MOVIv2i32:
1307   case ARM64::MOVIv4i32:
1308   case ARM64::MVNIv2i32:
1309   case ARM64::MVNIv4i32:
1310     Inst.addOperand(MCOperand::CreateImm((cmode & 6) << 2));
1311     break;
1312   case ARM64::MOVIv2s_msl:
1313   case ARM64::MOVIv4s_msl:
1314   case ARM64::MVNIv2s_msl:
1315   case ARM64::MVNIv4s_msl:
1316     Inst.addOperand(MCOperand::CreateImm(cmode & 1 ? 0x110 : 0x108));
1317     break;
1318   }
1319
1320   return Success;
1321 }
1322
1323 static DecodeStatus DecodeModImmTiedInstruction(llvm::MCInst &Inst,
1324                                                 uint32_t insn, uint64_t Addr,
1325                                                 const void *Decoder) {
1326   unsigned Rd = fieldFromInstruction(insn, 0, 5);
1327   unsigned cmode = fieldFromInstruction(insn, 12, 4);
1328   unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1329   imm |= fieldFromInstruction(insn, 5, 5);
1330
1331   // Tied operands added twice.
1332   DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1333   DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1334
1335   Inst.addOperand(MCOperand::CreateImm(imm));
1336   Inst.addOperand(MCOperand::CreateImm((cmode & 6) << 2));
1337
1338   return Success;
1339 }
1340
1341 static DecodeStatus DecodeAdrInstruction(llvm::MCInst &Inst, uint32_t insn,
1342                                          uint64_t Addr, const void *Decoder) {
1343   unsigned Rd = fieldFromInstruction(insn, 0, 5);
1344   int64_t imm = fieldFromInstruction(insn, 5, 19) << 2;
1345   imm |= fieldFromInstruction(insn, 29, 2);
1346   const ARM64Disassembler *Dis =
1347       static_cast<const ARM64Disassembler *>(Decoder);
1348
1349   // Sign-extend the 21-bit immediate.
1350   if (imm & (1 << (21 - 1)))
1351     imm |= ~((1LL << 21) - 1);
1352
1353   DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1354   if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4))
1355     Inst.addOperand(MCOperand::CreateImm(imm));
1356
1357   return Success;
1358 }
1359
1360 static DecodeStatus DecodeBaseAddSubImm(llvm::MCInst &Inst, uint32_t insn,
1361                                         uint64_t Addr, const void *Decoder) {
1362   unsigned Rd = fieldFromInstruction(insn, 0, 5);
1363   unsigned Rn = fieldFromInstruction(insn, 5, 5);
1364   unsigned Imm = fieldFromInstruction(insn, 10, 14);
1365   unsigned S = fieldFromInstruction(insn, 29, 1);
1366   unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1367
1368   unsigned ShifterVal = (Imm >> 12) & 3;
1369   unsigned ImmVal = Imm & 0xFFF;
1370   const ARM64Disassembler *Dis =
1371       static_cast<const ARM64Disassembler *>(Decoder);
1372
1373   if (ShifterVal != 0 && ShifterVal != 1)
1374     return Fail;
1375
1376   if (Datasize) {
1377     if (Rd == 31 && !S)
1378       DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1379     else
1380       DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1381     DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1382   } else {
1383     if (Rd == 31 && !S)
1384       DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1385     else
1386       DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1387     DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1388   }
1389
1390   if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4))
1391     Inst.addOperand(MCOperand::CreateImm(ImmVal));
1392   Inst.addOperand(MCOperand::CreateImm(12 * ShifterVal));
1393   return Success;
1394 }
1395
1396 static DecodeStatus DecodeUnconditionalBranch(llvm::MCInst &Inst, uint32_t insn,
1397                                               uint64_t Addr,
1398                                               const void *Decoder) {
1399   int64_t imm = fieldFromInstruction(insn, 0, 26);
1400   const ARM64Disassembler *Dis =
1401       static_cast<const ARM64Disassembler *>(Decoder);
1402
1403   // Sign-extend the 26-bit immediate.
1404   if (imm & (1 << (26 - 1)))
1405     imm |= ~((1LL << 26) - 1);
1406
1407   if (!Dis->tryAddingSymbolicOperand(Inst, imm << 2, Addr, true, 0, 4))
1408     Inst.addOperand(MCOperand::CreateImm(imm));
1409
1410   return Success;
1411 }
1412
1413 static DecodeStatus DecodeSystemPStateInstruction(llvm::MCInst &Inst,
1414                                                   uint32_t insn, uint64_t Addr,
1415                                                   const void *Decoder) {
1416   uint64_t op1 = fieldFromInstruction(insn, 16, 3);
1417   uint64_t op2 = fieldFromInstruction(insn, 5, 3);
1418   uint64_t crm = fieldFromInstruction(insn, 8, 4);
1419
1420   uint64_t pstate_field = (op1 << 3) | op2;
1421
1422   Inst.addOperand(MCOperand::CreateImm(pstate_field));
1423   Inst.addOperand(MCOperand::CreateImm(crm));
1424
1425   bool ValidNamed;
1426   (void)ARM64PState::PStateMapper().toString(pstate_field, ValidNamed);
1427
1428   return ValidNamed ? Success : Fail;
1429 }
1430
1431 static DecodeStatus DecodeTestAndBranch(llvm::MCInst &Inst, uint32_t insn,
1432                                         uint64_t Addr, const void *Decoder) {
1433   uint64_t Rt = fieldFromInstruction(insn, 0, 5);
1434   uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5;
1435   bit |= fieldFromInstruction(insn, 19, 5);
1436   int64_t dst = fieldFromInstruction(insn, 5, 14);
1437   const ARM64Disassembler *Dis =
1438       static_cast<const ARM64Disassembler *>(Decoder);
1439
1440   // Sign-extend 14-bit immediate.
1441   if (dst & (1 << (14 - 1)))
1442     dst |= ~((1LL << 14) - 1);
1443
1444   DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1445   Inst.addOperand(MCOperand::CreateImm(bit));
1446   if (!Dis->tryAddingSymbolicOperand(Inst, dst << 2, Addr, true, 0, 4))
1447     Inst.addOperand(MCOperand::CreateImm(dst));
1448
1449   return Success;
1450 }