1 //===-- ARM64ISelDAGToDAG.cpp - A dag to dag inst selector for ARM64 ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the ARM64 target.
12 //===----------------------------------------------------------------------===//
14 #include "ARM64TargetMachine.h"
15 #include "MCTargetDesc/ARM64AddressingModes.h"
16 #include "llvm/ADT/APSInt.h"
17 #include "llvm/CodeGen/SelectionDAGISel.h"
18 #include "llvm/IR/Function.h" // To access function attributes.
19 #include "llvm/IR/GlobalValue.h"
20 #include "llvm/IR/Intrinsics.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/MathExtras.h"
24 #include "llvm/Support/raw_ostream.h"
28 #define DEBUG_TYPE "arm64-isel"
30 //===--------------------------------------------------------------------===//
31 /// ARM64DAGToDAGISel - ARM64 specific code to select ARM64 machine
32 /// instructions for SelectionDAG operations.
36 class ARM64DAGToDAGISel : public SelectionDAGISel {
37 ARM64TargetMachine &TM;
39 /// Subtarget - Keep a pointer to the ARM64Subtarget around so that we can
40 /// make the right decision when generating code for different targets.
41 const ARM64Subtarget *Subtarget;
46 explicit ARM64DAGToDAGISel(ARM64TargetMachine &tm, CodeGenOpt::Level OptLevel)
47 : SelectionDAGISel(tm, OptLevel), TM(tm),
48 Subtarget(&TM.getSubtarget<ARM64Subtarget>()), ForCodeSize(false) {}
50 const char *getPassName() const override {
51 return "ARM64 Instruction Selection";
54 bool runOnMachineFunction(MachineFunction &MF) override {
55 AttributeSet FnAttrs = MF.getFunction()->getAttributes();
57 FnAttrs.hasAttribute(AttributeSet::FunctionIndex,
58 Attribute::OptimizeForSize) ||
59 FnAttrs.hasAttribute(AttributeSet::FunctionIndex, Attribute::MinSize);
60 return SelectionDAGISel::runOnMachineFunction(MF);
63 SDNode *Select(SDNode *Node) override;
65 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
66 /// inline asm expressions.
67 bool SelectInlineAsmMemoryOperand(const SDValue &Op,
69 std::vector<SDValue> &OutOps) override;
71 SDNode *SelectMLAV64LaneV128(SDNode *N);
72 SDNode *SelectMULLV64LaneV128(unsigned IntNo, SDNode *N);
73 bool SelectArithExtendedRegister(SDValue N, SDValue &Reg, SDValue &Shift);
74 bool SelectArithImmed(SDValue N, SDValue &Val, SDValue &Shift);
75 bool SelectNegArithImmed(SDValue N, SDValue &Val, SDValue &Shift);
76 bool SelectArithShiftedRegister(SDValue N, SDValue &Reg, SDValue &Shift) {
77 return SelectShiftedRegister(N, false, Reg, Shift);
79 bool SelectLogicalShiftedRegister(SDValue N, SDValue &Reg, SDValue &Shift) {
80 return SelectShiftedRegister(N, true, Reg, Shift);
82 bool SelectAddrModeIndexed8(SDValue N, SDValue &Base, SDValue &OffImm) {
83 return SelectAddrModeIndexed(N, 1, Base, OffImm);
85 bool SelectAddrModeIndexed16(SDValue N, SDValue &Base, SDValue &OffImm) {
86 return SelectAddrModeIndexed(N, 2, Base, OffImm);
88 bool SelectAddrModeIndexed32(SDValue N, SDValue &Base, SDValue &OffImm) {
89 return SelectAddrModeIndexed(N, 4, Base, OffImm);
91 bool SelectAddrModeIndexed64(SDValue N, SDValue &Base, SDValue &OffImm) {
92 return SelectAddrModeIndexed(N, 8, Base, OffImm);
94 bool SelectAddrModeIndexed128(SDValue N, SDValue &Base, SDValue &OffImm) {
95 return SelectAddrModeIndexed(N, 16, Base, OffImm);
97 bool SelectAddrModeUnscaled8(SDValue N, SDValue &Base, SDValue &OffImm) {
98 return SelectAddrModeUnscaled(N, 1, Base, OffImm);
100 bool SelectAddrModeUnscaled16(SDValue N, SDValue &Base, SDValue &OffImm) {
101 return SelectAddrModeUnscaled(N, 2, Base, OffImm);
103 bool SelectAddrModeUnscaled32(SDValue N, SDValue &Base, SDValue &OffImm) {
104 return SelectAddrModeUnscaled(N, 4, Base, OffImm);
106 bool SelectAddrModeUnscaled64(SDValue N, SDValue &Base, SDValue &OffImm) {
107 return SelectAddrModeUnscaled(N, 8, Base, OffImm);
109 bool SelectAddrModeUnscaled128(SDValue N, SDValue &Base, SDValue &OffImm) {
110 return SelectAddrModeUnscaled(N, 16, Base, OffImm);
113 bool SelectAddrModeRO8(SDValue N, SDValue &Base, SDValue &Offset,
115 return SelectAddrModeRO(N, 1, Base, Offset, Imm);
117 bool SelectAddrModeRO16(SDValue N, SDValue &Base, SDValue &Offset,
119 return SelectAddrModeRO(N, 2, Base, Offset, Imm);
121 bool SelectAddrModeRO32(SDValue N, SDValue &Base, SDValue &Offset,
123 return SelectAddrModeRO(N, 4, Base, Offset, Imm);
125 bool SelectAddrModeRO64(SDValue N, SDValue &Base, SDValue &Offset,
127 return SelectAddrModeRO(N, 8, Base, Offset, Imm);
129 bool SelectAddrModeRO128(SDValue N, SDValue &Base, SDValue &Offset,
131 return SelectAddrModeRO(N, 16, Base, Offset, Imm);
133 bool SelectAddrModeNoIndex(SDValue N, SDValue &Val);
135 /// Form sequences of consecutive 64/128-bit registers for use in NEON
136 /// instructions making use of a vector-list (e.g. ldN, tbl). Vecs must have
137 /// between 1 and 4 elements. If it contains a single element that is returned
138 /// unchanged; otherwise a REG_SEQUENCE value is returned.
139 SDValue createDTuple(ArrayRef<SDValue> Vecs);
140 SDValue createQTuple(ArrayRef<SDValue> Vecs);
142 /// Generic helper for the createDTuple/createQTuple
143 /// functions. Those should almost always be called instead.
144 SDValue createTuple(ArrayRef<SDValue> Vecs, unsigned RegClassIDs[],
147 SDNode *SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc, bool isExt);
149 SDNode *SelectIndexedLoad(SDNode *N, bool &Done);
151 SDNode *SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
153 SDNode *SelectPostLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
155 SDNode *SelectLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
156 SDNode *SelectPostLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
158 SDNode *SelectStore(SDNode *N, unsigned NumVecs, unsigned Opc);
159 SDNode *SelectPostStore(SDNode *N, unsigned NumVecs, unsigned Opc);
160 SDNode *SelectStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
161 SDNode *SelectPostStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
163 SDNode *SelectSIMDAddSubNarrowing(unsigned IntNo, SDNode *Node);
164 SDNode *SelectSIMDXtnNarrowing(unsigned IntNo, SDNode *Node);
166 SDNode *SelectBitfieldExtractOp(SDNode *N);
167 SDNode *SelectBitfieldInsertOp(SDNode *N);
169 SDNode *SelectLIBM(SDNode *N);
171 // Include the pieces autogenerated from the target description.
172 #include "ARM64GenDAGISel.inc"
175 bool SelectShiftedRegister(SDValue N, bool AllowROR, SDValue &Reg,
177 bool SelectAddrModeIndexed(SDValue N, unsigned Size, SDValue &Base,
179 bool SelectAddrModeUnscaled(SDValue N, unsigned Size, SDValue &Base,
181 bool SelectAddrModeRO(SDValue N, unsigned Size, SDValue &Base,
182 SDValue &Offset, SDValue &Imm);
183 bool isWorthFolding(SDValue V) const;
184 bool SelectExtendedSHL(SDValue N, unsigned Size, SDValue &Offset,
187 template<unsigned RegWidth>
188 bool SelectCVTFixedPosOperand(SDValue N, SDValue &FixedPos) {
189 return SelectCVTFixedPosOperand(N, FixedPos, RegWidth);
192 bool SelectCVTFixedPosOperand(SDValue N, SDValue &FixedPos, unsigned Width);
194 } // end anonymous namespace
196 /// isIntImmediate - This method tests to see if the node is a constant
197 /// operand. If so Imm will receive the 32-bit value.
198 static bool isIntImmediate(const SDNode *N, uint64_t &Imm) {
199 if (const ConstantSDNode *C = dyn_cast<const ConstantSDNode>(N)) {
200 Imm = C->getZExtValue();
206 // isIntImmediate - This method tests to see if a constant operand.
207 // If so Imm will receive the value.
208 static bool isIntImmediate(SDValue N, uint64_t &Imm) {
209 return isIntImmediate(N.getNode(), Imm);
212 // isOpcWithIntImmediate - This method tests to see if the node is a specific
213 // opcode and that it has a immediate integer right operand.
214 // If so Imm will receive the 32 bit value.
215 static bool isOpcWithIntImmediate(const SDNode *N, unsigned Opc,
217 return N->getOpcode() == Opc &&
218 isIntImmediate(N->getOperand(1).getNode(), Imm);
221 bool ARM64DAGToDAGISel::SelectAddrModeNoIndex(SDValue N, SDValue &Val) {
222 EVT ValTy = N.getValueType();
223 if (ValTy != MVT::i64)
229 bool ARM64DAGToDAGISel::SelectInlineAsmMemoryOperand(
230 const SDValue &Op, char ConstraintCode, std::vector<SDValue> &OutOps) {
231 assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
232 // Require the address to be in a register. That is safe for all ARM64
233 // variants and it is hard to do anything much smarter without knowing
234 // how the operand is used.
235 OutOps.push_back(Op);
239 /// SelectArithImmed - Select an immediate value that can be represented as
240 /// a 12-bit value shifted left by either 0 or 12. If so, return true with
241 /// Val set to the 12-bit value and Shift set to the shifter operand.
242 bool ARM64DAGToDAGISel::SelectArithImmed(SDValue N, SDValue &Val,
244 // This function is called from the addsub_shifted_imm ComplexPattern,
245 // which lists [imm] as the list of opcode it's interested in, however
246 // we still need to check whether the operand is actually an immediate
247 // here because the ComplexPattern opcode list is only used in
248 // root-level opcode matching.
249 if (!isa<ConstantSDNode>(N.getNode()))
252 uint64_t Immed = cast<ConstantSDNode>(N.getNode())->getZExtValue();
255 if (Immed >> 12 == 0) {
257 } else if ((Immed & 0xfff) == 0 && Immed >> 24 == 0) {
263 unsigned ShVal = ARM64_AM::getShifterImm(ARM64_AM::LSL, ShiftAmt);
264 Val = CurDAG->getTargetConstant(Immed, MVT::i32);
265 Shift = CurDAG->getTargetConstant(ShVal, MVT::i32);
269 /// SelectNegArithImmed - As above, but negates the value before trying to
271 bool ARM64DAGToDAGISel::SelectNegArithImmed(SDValue N, SDValue &Val,
273 // This function is called from the addsub_shifted_imm ComplexPattern,
274 // which lists [imm] as the list of opcode it's interested in, however
275 // we still need to check whether the operand is actually an immediate
276 // here because the ComplexPattern opcode list is only used in
277 // root-level opcode matching.
278 if (!isa<ConstantSDNode>(N.getNode()))
281 // The immediate operand must be a 24-bit zero-extended immediate.
282 uint64_t Immed = cast<ConstantSDNode>(N.getNode())->getZExtValue();
284 // This negation is almost always valid, but "cmp wN, #0" and "cmn wN, #0"
285 // have the opposite effect on the C flag, so this pattern mustn't match under
286 // those circumstances.
290 if (N.getValueType() == MVT::i32)
291 Immed = ~((uint32_t)Immed) + 1;
293 Immed = ~Immed + 1ULL;
294 if (Immed & 0xFFFFFFFFFF000000ULL)
297 Immed &= 0xFFFFFFULL;
298 return SelectArithImmed(CurDAG->getConstant(Immed, MVT::i32), Val, Shift);
301 /// getShiftTypeForNode - Translate a shift node to the corresponding
303 static ARM64_AM::ShiftType getShiftTypeForNode(SDValue N) {
304 switch (N.getOpcode()) {
306 return ARM64_AM::InvalidShift;
308 return ARM64_AM::LSL;
310 return ARM64_AM::LSR;
312 return ARM64_AM::ASR;
314 return ARM64_AM::ROR;
318 /// \brief Determine wether it is worth to fold V into an extended register.
319 bool ARM64DAGToDAGISel::isWorthFolding(SDValue V) const {
320 // it hurts if the a value is used at least twice, unless we are optimizing
322 if (ForCodeSize || V.hasOneUse())
327 /// SelectShiftedRegister - Select a "shifted register" operand. If the value
328 /// is not shifted, set the Shift operand to default of "LSL 0". The logical
329 /// instructions allow the shifted register to be rotated, but the arithmetic
330 /// instructions do not. The AllowROR parameter specifies whether ROR is
332 bool ARM64DAGToDAGISel::SelectShiftedRegister(SDValue N, bool AllowROR,
333 SDValue &Reg, SDValue &Shift) {
334 ARM64_AM::ShiftType ShType = getShiftTypeForNode(N);
335 if (ShType == ARM64_AM::InvalidShift)
337 if (!AllowROR && ShType == ARM64_AM::ROR)
340 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
341 unsigned BitSize = N.getValueType().getSizeInBits();
342 unsigned Val = RHS->getZExtValue() & (BitSize - 1);
343 unsigned ShVal = ARM64_AM::getShifterImm(ShType, Val);
345 Reg = N.getOperand(0);
346 Shift = CurDAG->getTargetConstant(ShVal, MVT::i32);
347 return isWorthFolding(N);
353 /// getExtendTypeForNode - Translate an extend node to the corresponding
354 /// ExtendType value.
355 static ARM64_AM::ExtendType getExtendTypeForNode(SDValue N,
356 bool IsLoadStore = false) {
357 if (N.getOpcode() == ISD::SIGN_EXTEND ||
358 N.getOpcode() == ISD::SIGN_EXTEND_INREG) {
360 if (N.getOpcode() == ISD::SIGN_EXTEND_INREG)
361 SrcVT = cast<VTSDNode>(N.getOperand(1))->getVT();
363 SrcVT = N.getOperand(0).getValueType();
365 if (!IsLoadStore && SrcVT == MVT::i8)
366 return ARM64_AM::SXTB;
367 else if (!IsLoadStore && SrcVT == MVT::i16)
368 return ARM64_AM::SXTH;
369 else if (SrcVT == MVT::i32)
370 return ARM64_AM::SXTW;
371 else if (SrcVT == MVT::i64)
372 return ARM64_AM::SXTX;
374 return ARM64_AM::InvalidExtend;
375 } else if (N.getOpcode() == ISD::ZERO_EXTEND ||
376 N.getOpcode() == ISD::ANY_EXTEND) {
377 EVT SrcVT = N.getOperand(0).getValueType();
378 if (!IsLoadStore && SrcVT == MVT::i8)
379 return ARM64_AM::UXTB;
380 else if (!IsLoadStore && SrcVT == MVT::i16)
381 return ARM64_AM::UXTH;
382 else if (SrcVT == MVT::i32)
383 return ARM64_AM::UXTW;
384 else if (SrcVT == MVT::i64)
385 return ARM64_AM::UXTX;
387 return ARM64_AM::InvalidExtend;
388 } else if (N.getOpcode() == ISD::AND) {
389 ConstantSDNode *CSD = dyn_cast<ConstantSDNode>(N.getOperand(1));
391 return ARM64_AM::InvalidExtend;
392 uint64_t AndMask = CSD->getZExtValue();
396 return ARM64_AM::InvalidExtend;
398 return !IsLoadStore ? ARM64_AM::UXTB : ARM64_AM::InvalidExtend;
400 return !IsLoadStore ? ARM64_AM::UXTH : ARM64_AM::InvalidExtend;
402 return ARM64_AM::UXTW;
406 return ARM64_AM::InvalidExtend;
409 // Helper for SelectMLAV64LaneV128 - Recognize high lane extracts.
410 static bool checkHighLaneIndex(SDNode *DL, SDValue &LaneOp, int &LaneIdx) {
411 if (DL->getOpcode() != ARM64ISD::DUPLANE16 &&
412 DL->getOpcode() != ARM64ISD::DUPLANE32)
415 SDValue SV = DL->getOperand(0);
416 if (SV.getOpcode() != ISD::INSERT_SUBVECTOR)
419 SDValue EV = SV.getOperand(1);
420 if (EV.getOpcode() != ISD::EXTRACT_SUBVECTOR)
423 ConstantSDNode *DLidx = cast<ConstantSDNode>(DL->getOperand(1).getNode());
424 ConstantSDNode *EVidx = cast<ConstantSDNode>(EV.getOperand(1).getNode());
425 LaneIdx = DLidx->getSExtValue() + EVidx->getSExtValue();
426 LaneOp = EV.getOperand(0);
431 // Helper for SelectOpcV64LaneV128 - Recogzine operatinos where one operand is a
432 // high lane extract.
433 static bool checkV64LaneV128(SDValue Op0, SDValue Op1, SDValue &StdOp,
434 SDValue &LaneOp, int &LaneIdx) {
436 if (!checkHighLaneIndex(Op0.getNode(), LaneOp, LaneIdx)) {
438 if (!checkHighLaneIndex(Op0.getNode(), LaneOp, LaneIdx))
445 /// SelectMLAV64LaneV128 - ARM64 supports vector MLAs where one multiplicand is
446 /// a lane in the upper half of a 128-bit vector. Recognize and select this so
447 /// that we don't emit unnecessary lane extracts.
448 SDNode *ARM64DAGToDAGISel::SelectMLAV64LaneV128(SDNode *N) {
449 SDValue Op0 = N->getOperand(0);
450 SDValue Op1 = N->getOperand(1);
451 SDValue MLAOp1; // Will hold ordinary multiplicand for MLA.
452 SDValue MLAOp2; // Will hold lane-accessed multiplicand for MLA.
453 int LaneIdx = -1; // Will hold the lane index.
455 if (Op1.getOpcode() != ISD::MUL ||
456 !checkV64LaneV128(Op1.getOperand(0), Op1.getOperand(1), MLAOp1, MLAOp2,
459 if (Op1.getOpcode() != ISD::MUL ||
460 !checkV64LaneV128(Op1.getOperand(0), Op1.getOperand(1), MLAOp1, MLAOp2,
465 SDValue LaneIdxVal = CurDAG->getTargetConstant(LaneIdx, MVT::i64);
467 SDValue Ops[] = { Op0, MLAOp1, MLAOp2, LaneIdxVal };
469 unsigned MLAOpc = ~0U;
471 switch (N->getSimpleValueType(0).SimpleTy) {
473 llvm_unreachable("Unrecognized MLA.");
475 MLAOpc = ARM64::MLAv4i16_indexed;
478 MLAOpc = ARM64::MLAv8i16_indexed;
481 MLAOpc = ARM64::MLAv2i32_indexed;
484 MLAOpc = ARM64::MLAv4i32_indexed;
488 return CurDAG->getMachineNode(MLAOpc, SDLoc(N), N->getValueType(0), Ops);
491 SDNode *ARM64DAGToDAGISel::SelectMULLV64LaneV128(unsigned IntNo, SDNode *N) {
496 if (!checkV64LaneV128(N->getOperand(1), N->getOperand(2), SMULLOp0, SMULLOp1,
500 SDValue LaneIdxVal = CurDAG->getTargetConstant(LaneIdx, MVT::i64);
502 SDValue Ops[] = { SMULLOp0, SMULLOp1, LaneIdxVal };
504 unsigned SMULLOpc = ~0U;
506 if (IntNo == Intrinsic::arm64_neon_smull) {
507 switch (N->getSimpleValueType(0).SimpleTy) {
509 llvm_unreachable("Unrecognized SMULL.");
511 SMULLOpc = ARM64::SMULLv4i16_indexed;
514 SMULLOpc = ARM64::SMULLv2i32_indexed;
517 } else if (IntNo == Intrinsic::arm64_neon_umull) {
518 switch (N->getSimpleValueType(0).SimpleTy) {
520 llvm_unreachable("Unrecognized SMULL.");
522 SMULLOpc = ARM64::UMULLv4i16_indexed;
525 SMULLOpc = ARM64::UMULLv2i32_indexed;
529 llvm_unreachable("Unrecognized intrinsic.");
531 return CurDAG->getMachineNode(SMULLOpc, SDLoc(N), N->getValueType(0), Ops);
534 /// SelectArithExtendedRegister - Select a "extended register" operand. This
535 /// operand folds in an extend followed by an optional left shift.
536 bool ARM64DAGToDAGISel::SelectArithExtendedRegister(SDValue N, SDValue &Reg,
538 unsigned ShiftVal = 0;
539 ARM64_AM::ExtendType Ext;
541 if (N.getOpcode() == ISD::SHL) {
542 ConstantSDNode *CSD = dyn_cast<ConstantSDNode>(N.getOperand(1));
545 ShiftVal = CSD->getZExtValue();
549 Ext = getExtendTypeForNode(N.getOperand(0));
550 if (Ext == ARM64_AM::InvalidExtend)
553 Reg = N.getOperand(0).getOperand(0);
555 Ext = getExtendTypeForNode(N);
556 if (Ext == ARM64_AM::InvalidExtend)
559 Reg = N.getOperand(0);
562 // ARM64 mandates that the RHS of the operation must use the smallest
563 // register classs that could contain the size being extended from. Thus,
564 // if we're folding a (sext i8), we need the RHS to be a GPR32, even though
565 // there might not be an actual 32-bit value in the program. We can
566 // (harmlessly) synthesize one by injected an EXTRACT_SUBREG here.
567 if (Reg.getValueType() == MVT::i64 && Ext != ARM64_AM::UXTX &&
568 Ext != ARM64_AM::SXTX) {
569 SDValue SubReg = CurDAG->getTargetConstant(ARM64::sub_32, MVT::i32);
570 MachineSDNode *Node = CurDAG->getMachineNode(
571 TargetOpcode::EXTRACT_SUBREG, SDLoc(N), MVT::i32, Reg, SubReg);
572 Reg = SDValue(Node, 0);
575 Shift = CurDAG->getTargetConstant(getArithExtendImm(Ext, ShiftVal), MVT::i32);
576 return isWorthFolding(N);
579 /// SelectAddrModeIndexed - Select a "register plus scaled unsigned 12-bit
580 /// immediate" address. The "Size" argument is the size in bytes of the memory
581 /// reference, which determines the scale.
582 bool ARM64DAGToDAGISel::SelectAddrModeIndexed(SDValue N, unsigned Size,
583 SDValue &Base, SDValue &OffImm) {
584 const TargetLowering *TLI = getTargetLowering();
585 if (N.getOpcode() == ISD::FrameIndex) {
586 int FI = cast<FrameIndexSDNode>(N)->getIndex();
587 Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy());
588 OffImm = CurDAG->getTargetConstant(0, MVT::i64);
592 if (N.getOpcode() == ARM64ISD::ADDlow) {
593 GlobalAddressSDNode *GAN =
594 dyn_cast<GlobalAddressSDNode>(N.getOperand(1).getNode());
595 Base = N.getOperand(0);
596 OffImm = N.getOperand(1);
600 const GlobalValue *GV = GAN->getGlobal();
601 unsigned Alignment = GV->getAlignment();
602 const DataLayout *DL = TLI->getDataLayout();
603 if (Alignment == 0 && !Subtarget->isTargetDarwin())
604 Alignment = DL->getABITypeAlignment(GV->getType()->getElementType());
606 if (Alignment >= Size)
610 if (CurDAG->isBaseWithConstantOffset(N)) {
611 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
612 int64_t RHSC = (int64_t)RHS->getZExtValue();
613 unsigned Scale = Log2_32(Size);
614 if ((RHSC & (Size - 1)) == 0 && RHSC >= 0 && RHSC < (0x1000 << Scale)) {
615 Base = N.getOperand(0);
616 if (Base.getOpcode() == ISD::FrameIndex) {
617 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
618 Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy());
620 OffImm = CurDAG->getTargetConstant(RHSC >> Scale, MVT::i64);
626 // Before falling back to our general case, check if the unscaled
627 // instructions can handle this. If so, that's preferable.
628 if (SelectAddrModeUnscaled(N, Size, Base, OffImm))
631 // Base only. The address will be materialized into a register before
632 // the memory is accessed.
633 // add x0, Xbase, #offset
636 OffImm = CurDAG->getTargetConstant(0, MVT::i64);
640 /// SelectAddrModeUnscaled - Select a "register plus unscaled signed 9-bit
641 /// immediate" address. This should only match when there is an offset that
642 /// is not valid for a scaled immediate addressing mode. The "Size" argument
643 /// is the size in bytes of the memory reference, which is needed here to know
644 /// what is valid for a scaled immediate.
645 bool ARM64DAGToDAGISel::SelectAddrModeUnscaled(SDValue N, unsigned Size,
646 SDValue &Base, SDValue &OffImm) {
647 if (!CurDAG->isBaseWithConstantOffset(N))
649 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
650 int64_t RHSC = RHS->getSExtValue();
651 // If the offset is valid as a scaled immediate, don't match here.
652 if ((RHSC & (Size - 1)) == 0 && RHSC >= 0 &&
653 RHSC < (0x1000 << Log2_32(Size)))
655 if (RHSC >= -256 && RHSC < 256) {
656 Base = N.getOperand(0);
657 if (Base.getOpcode() == ISD::FrameIndex) {
658 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
659 const TargetLowering *TLI = getTargetLowering();
660 Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy());
662 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i64);
669 static SDValue Widen(SelectionDAG *CurDAG, SDValue N) {
670 SDValue SubReg = CurDAG->getTargetConstant(ARM64::sub_32, MVT::i32);
671 SDValue ImpDef = SDValue(
672 CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, SDLoc(N), MVT::i64),
674 MachineSDNode *Node = CurDAG->getMachineNode(
675 TargetOpcode::INSERT_SUBREG, SDLoc(N), MVT::i64, ImpDef, N, SubReg);
676 return SDValue(Node, 0);
679 static SDValue WidenIfNeeded(SelectionDAG *CurDAG, SDValue N) {
680 if (N.getValueType() == MVT::i32) {
681 return Widen(CurDAG, N);
687 /// \brief Check if the given SHL node (\p N), can be used to form an
688 /// extended register for an addressing mode.
689 bool ARM64DAGToDAGISel::SelectExtendedSHL(SDValue N, unsigned Size,
690 SDValue &Offset, SDValue &Imm) {
691 assert(N.getOpcode() == ISD::SHL && "Invalid opcode.");
692 ConstantSDNode *CSD = dyn_cast<ConstantSDNode>(N.getOperand(1));
693 if (CSD && (CSD->getZExtValue() & 0x7) == CSD->getZExtValue()) {
695 ARM64_AM::ExtendType Ext = getExtendTypeForNode(N.getOperand(0), true);
696 if (Ext == ARM64_AM::InvalidExtend) {
697 Ext = ARM64_AM::UXTX;
698 Offset = WidenIfNeeded(CurDAG, N.getOperand(0));
700 Offset = WidenIfNeeded(CurDAG, N.getOperand(0).getOperand(0));
703 unsigned LegalShiftVal = Log2_32(Size);
704 unsigned ShiftVal = CSD->getZExtValue();
706 if (ShiftVal != 0 && ShiftVal != LegalShiftVal)
709 Imm = CurDAG->getTargetConstant(
710 ARM64_AM::getMemExtendImm(Ext, ShiftVal != 0), MVT::i32);
711 if (isWorthFolding(N))
717 bool ARM64DAGToDAGISel::SelectAddrModeRO(SDValue N, unsigned Size,
718 SDValue &Base, SDValue &Offset,
720 if (N.getOpcode() != ISD::ADD)
722 SDValue LHS = N.getOperand(0);
723 SDValue RHS = N.getOperand(1);
725 // We don't want to match immediate adds here, because they are better lowered
726 // to the register-immediate addressing modes.
727 if (isa<ConstantSDNode>(LHS) || isa<ConstantSDNode>(RHS))
730 // Check if this particular node is reused in any non-memory related
731 // operation. If yes, do not try to fold this node into the address
732 // computation, since the computation will be kept.
733 const SDNode *Node = N.getNode();
734 for (SDNode *UI : Node->uses()) {
735 if (!isa<MemSDNode>(*UI))
739 // Remember if it is worth folding N when it produces extended register.
740 bool IsExtendedRegisterWorthFolding = isWorthFolding(N);
742 // Try to match a shifted extend on the RHS.
743 if (IsExtendedRegisterWorthFolding && RHS.getOpcode() == ISD::SHL &&
744 SelectExtendedSHL(RHS, Size, Offset, Imm)) {
749 // Try to match a shifted extend on the LHS.
750 if (IsExtendedRegisterWorthFolding && LHS.getOpcode() == ISD::SHL &&
751 SelectExtendedSHL(LHS, Size, Offset, Imm)) {
756 ARM64_AM::ExtendType Ext = ARM64_AM::UXTX;
757 // Try to match an unshifted extend on the LHS.
758 if (IsExtendedRegisterWorthFolding &&
759 (Ext = getExtendTypeForNode(LHS, true)) != ARM64_AM::InvalidExtend) {
761 Offset = WidenIfNeeded(CurDAG, LHS.getOperand(0));
762 Imm = CurDAG->getTargetConstant(ARM64_AM::getMemExtendImm(Ext, false),
764 if (isWorthFolding(LHS))
768 // Try to match an unshifted extend on the RHS.
769 if (IsExtendedRegisterWorthFolding &&
770 (Ext = getExtendTypeForNode(RHS, true)) != ARM64_AM::InvalidExtend) {
772 Offset = WidenIfNeeded(CurDAG, RHS.getOperand(0));
773 Imm = CurDAG->getTargetConstant(ARM64_AM::getMemExtendImm(Ext, false),
775 if (isWorthFolding(RHS))
779 // Match any non-shifted, non-extend, non-immediate add expression.
781 Offset = WidenIfNeeded(CurDAG, RHS);
782 Ext = ARM64_AM::UXTX;
783 Imm = CurDAG->getTargetConstant(ARM64_AM::getMemExtendImm(Ext, false),
785 // Reg1 + Reg2 is free: no check needed.
789 SDValue ARM64DAGToDAGISel::createDTuple(ArrayRef<SDValue> Regs) {
790 static unsigned RegClassIDs[] = { ARM64::DDRegClassID, ARM64::DDDRegClassID,
791 ARM64::DDDDRegClassID };
792 static unsigned SubRegs[] = { ARM64::dsub0, ARM64::dsub1,
793 ARM64::dsub2, ARM64::dsub3 };
795 return createTuple(Regs, RegClassIDs, SubRegs);
798 SDValue ARM64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) {
799 static unsigned RegClassIDs[] = { ARM64::QQRegClassID, ARM64::QQQRegClassID,
800 ARM64::QQQQRegClassID };
801 static unsigned SubRegs[] = { ARM64::qsub0, ARM64::qsub1,
802 ARM64::qsub2, ARM64::qsub3 };
804 return createTuple(Regs, RegClassIDs, SubRegs);
807 SDValue ARM64DAGToDAGISel::createTuple(ArrayRef<SDValue> Regs,
808 unsigned RegClassIDs[],
809 unsigned SubRegs[]) {
810 // There's no special register-class for a vector-list of 1 element: it's just
812 if (Regs.size() == 1)
815 assert(Regs.size() >= 2 && Regs.size() <= 4);
817 SDLoc DL(Regs[0].getNode());
819 SmallVector<SDValue, 4> Ops;
821 // First operand of REG_SEQUENCE is the desired RegClass.
823 CurDAG->getTargetConstant(RegClassIDs[Regs.size() - 2], MVT::i32));
825 // Then we get pairs of source & subregister-position for the components.
826 for (unsigned i = 0; i < Regs.size(); ++i) {
827 Ops.push_back(Regs[i]);
828 Ops.push_back(CurDAG->getTargetConstant(SubRegs[i], MVT::i32));
832 CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL, MVT::Untyped, Ops);
833 return SDValue(N, 0);
836 SDNode *ARM64DAGToDAGISel::SelectTable(SDNode *N, unsigned NumVecs,
837 unsigned Opc, bool isExt) {
839 EVT VT = N->getValueType(0);
841 unsigned ExtOff = isExt;
843 // Form a REG_SEQUENCE to force register allocation.
844 unsigned Vec0Off = ExtOff + 1;
845 SmallVector<SDValue, 4> Regs(N->op_begin() + Vec0Off,
846 N->op_begin() + Vec0Off + NumVecs);
847 SDValue RegSeq = createQTuple(Regs);
849 SmallVector<SDValue, 6> Ops;
851 Ops.push_back(N->getOperand(1));
852 Ops.push_back(RegSeq);
853 Ops.push_back(N->getOperand(NumVecs + ExtOff + 1));
854 return CurDAG->getMachineNode(Opc, dl, VT, Ops);
857 SDNode *ARM64DAGToDAGISel::SelectIndexedLoad(SDNode *N, bool &Done) {
858 LoadSDNode *LD = cast<LoadSDNode>(N);
859 if (LD->isUnindexed())
861 EVT VT = LD->getMemoryVT();
862 EVT DstVT = N->getValueType(0);
863 ISD::MemIndexedMode AM = LD->getAddressingMode();
864 bool IsPre = AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
866 // We're not doing validity checking here. That was done when checking
867 // if we should mark the load as indexed or not. We're just selecting
868 // the right instruction.
871 ISD::LoadExtType ExtType = LD->getExtensionType();
872 bool InsertTo64 = false;
874 Opcode = IsPre ? ARM64::LDRXpre_isel : ARM64::LDRXpost_isel;
875 else if (VT == MVT::i32) {
876 if (ExtType == ISD::NON_EXTLOAD)
877 Opcode = IsPre ? ARM64::LDRWpre_isel : ARM64::LDRWpost_isel;
878 else if (ExtType == ISD::SEXTLOAD)
879 Opcode = IsPre ? ARM64::LDRSWpre_isel : ARM64::LDRSWpost_isel;
881 Opcode = IsPre ? ARM64::LDRWpre_isel : ARM64::LDRWpost_isel;
883 // The result of the load is only i32. It's the subreg_to_reg that makes
887 } else if (VT == MVT::i16) {
888 if (ExtType == ISD::SEXTLOAD) {
889 if (DstVT == MVT::i64)
890 Opcode = IsPre ? ARM64::LDRSHXpre_isel : ARM64::LDRSHXpost_isel;
892 Opcode = IsPre ? ARM64::LDRSHWpre_isel : ARM64::LDRSHWpost_isel;
894 Opcode = IsPre ? ARM64::LDRHHpre_isel : ARM64::LDRHHpost_isel;
895 InsertTo64 = DstVT == MVT::i64;
896 // The result of the load is only i32. It's the subreg_to_reg that makes
900 } else if (VT == MVT::i8) {
901 if (ExtType == ISD::SEXTLOAD) {
902 if (DstVT == MVT::i64)
903 Opcode = IsPre ? ARM64::LDRSBXpre_isel : ARM64::LDRSBXpost_isel;
905 Opcode = IsPre ? ARM64::LDRSBWpre_isel : ARM64::LDRSBWpost_isel;
907 Opcode = IsPre ? ARM64::LDRBBpre_isel : ARM64::LDRBBpost_isel;
908 InsertTo64 = DstVT == MVT::i64;
909 // The result of the load is only i32. It's the subreg_to_reg that makes
913 } else if (VT == MVT::f32) {
914 Opcode = IsPre ? ARM64::LDRSpre_isel : ARM64::LDRSpost_isel;
915 } else if (VT == MVT::f64 || VT.is64BitVector()) {
916 Opcode = IsPre ? ARM64::LDRDpre_isel : ARM64::LDRDpost_isel;
917 } else if (VT.is128BitVector()) {
918 Opcode = IsPre ? ARM64::LDRQpre_isel : ARM64::LDRQpost_isel;
921 SDValue Chain = LD->getChain();
922 SDValue Base = LD->getBasePtr();
923 ConstantSDNode *OffsetOp = cast<ConstantSDNode>(LD->getOffset());
924 int OffsetVal = (int)OffsetOp->getZExtValue();
925 SDValue Offset = CurDAG->getTargetConstant(OffsetVal, MVT::i64);
926 SDValue Ops[] = { Base, Offset, Chain };
927 SDNode *Res = CurDAG->getMachineNode(Opcode, SDLoc(N), DstVT, MVT::i64,
929 // Either way, we're replacing the node, so tell the caller that.
932 SDValue SubReg = CurDAG->getTargetConstant(ARM64::sub_32, MVT::i32);
933 SDNode *Sub = CurDAG->getMachineNode(
934 ARM64::SUBREG_TO_REG, SDLoc(N), MVT::i64,
935 CurDAG->getTargetConstant(0, MVT::i64), SDValue(Res, 0), SubReg);
936 ReplaceUses(SDValue(N, 0), SDValue(Sub, 0));
937 ReplaceUses(SDValue(N, 1), SDValue(Res, 1));
938 ReplaceUses(SDValue(N, 2), SDValue(Res, 2));
944 SDNode *ARM64DAGToDAGISel::SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
945 unsigned SubRegIdx) {
947 EVT VT = N->getValueType(0);
948 SDValue Chain = N->getOperand(0);
950 SmallVector<SDValue, 6> Ops;
951 Ops.push_back(N->getOperand(2)); // Mem operand;
952 Ops.push_back(Chain);
954 std::vector<EVT> ResTys;
955 ResTys.push_back(MVT::Untyped);
956 ResTys.push_back(MVT::Other);
958 SDNode *Ld = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
959 SDValue SuperReg = SDValue(Ld, 0);
960 for (unsigned i = 0; i < NumVecs; ++i)
961 ReplaceUses(SDValue(N, i),
962 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg));
964 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1));
968 SDNode *ARM64DAGToDAGISel::SelectPostLoad(SDNode *N, unsigned NumVecs,
969 unsigned Opc, unsigned SubRegIdx) {
971 EVT VT = N->getValueType(0);
972 SDValue Chain = N->getOperand(0);
974 SmallVector<SDValue, 6> Ops;
975 Ops.push_back(N->getOperand(1)); // Mem operand
976 Ops.push_back(N->getOperand(2)); // Incremental
977 Ops.push_back(Chain);
979 std::vector<EVT> ResTys;
980 ResTys.push_back(MVT::i64); // Type of the write back register
981 ResTys.push_back(MVT::Untyped);
982 ResTys.push_back(MVT::Other);
984 SDNode *Ld = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
986 // Update uses of write back register
987 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 0));
989 // Update uses of vector list
990 SDValue SuperReg = SDValue(Ld, 1);
991 for (unsigned i = 0; i < NumVecs; ++i)
992 ReplaceUses(SDValue(N, i),
993 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg));
996 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(Ld, 2));
1000 SDNode *ARM64DAGToDAGISel::SelectStore(SDNode *N, unsigned NumVecs,
1003 EVT VT = N->getOperand(2)->getValueType(0);
1005 // Form a REG_SEQUENCE to force register allocation.
1006 bool Is128Bit = VT.getSizeInBits() == 128;
1007 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);
1008 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs);
1010 SmallVector<SDValue, 6> Ops;
1011 Ops.push_back(RegSeq);
1012 Ops.push_back(N->getOperand(NumVecs + 2));
1013 Ops.push_back(N->getOperand(0));
1014 SDNode *St = CurDAG->getMachineNode(Opc, dl, N->getValueType(0), Ops);
1019 SDNode *ARM64DAGToDAGISel::SelectPostStore(SDNode *N, unsigned NumVecs,
1022 EVT VT = N->getOperand(2)->getValueType(0);
1023 SmallVector<EVT, 2> ResTys;
1024 ResTys.push_back(MVT::i64); // Type of the write back register
1025 ResTys.push_back(MVT::Other); // Type for the Chain
1027 // Form a REG_SEQUENCE to force register allocation.
1028 bool Is128Bit = VT.getSizeInBits() == 128;
1029 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs);
1030 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs);
1032 SmallVector<SDValue, 6> Ops;
1033 Ops.push_back(RegSeq);
1034 Ops.push_back(N->getOperand(NumVecs + 1)); // base register
1035 Ops.push_back(N->getOperand(NumVecs + 2)); // Incremental
1036 Ops.push_back(N->getOperand(0)); // Chain
1037 SDNode *St = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
1042 /// WidenVector - Given a value in the V64 register class, produce the
1043 /// equivalent value in the V128 register class.
1048 WidenVector(SelectionDAG &DAG) : DAG(DAG) {}
1050 SDValue operator()(SDValue V64Reg) {
1051 EVT VT = V64Reg.getValueType();
1052 unsigned NarrowSize = VT.getVectorNumElements();
1053 MVT EltTy = VT.getVectorElementType().getSimpleVT();
1054 MVT WideTy = MVT::getVectorVT(EltTy, 2 * NarrowSize);
1058 SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, WideTy), 0);
1059 return DAG.getTargetInsertSubreg(ARM64::dsub, DL, WideTy, Undef, V64Reg);
1063 /// NarrowVector - Given a value in the V128 register class, produce the
1064 /// equivalent value in the V64 register class.
1065 static SDValue NarrowVector(SDValue V128Reg, SelectionDAG &DAG) {
1066 EVT VT = V128Reg.getValueType();
1067 unsigned WideSize = VT.getVectorNumElements();
1068 MVT EltTy = VT.getVectorElementType().getSimpleVT();
1069 MVT NarrowTy = MVT::getVectorVT(EltTy, WideSize / 2);
1071 return DAG.getTargetExtractSubreg(ARM64::dsub, SDLoc(V128Reg), NarrowTy,
1075 SDNode *ARM64DAGToDAGISel::SelectLoadLane(SDNode *N, unsigned NumVecs,
1078 EVT VT = N->getValueType(0);
1079 bool Narrow = VT.getSizeInBits() == 64;
1081 // Form a REG_SEQUENCE to force register allocation.
1082 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);
1085 std::transform(Regs.begin(), Regs.end(), Regs.begin(),
1086 WidenVector(*CurDAG));
1088 SDValue RegSeq = createQTuple(Regs);
1090 std::vector<EVT> ResTys;
1091 ResTys.push_back(MVT::Untyped);
1092 ResTys.push_back(MVT::Other);
1095 cast<ConstantSDNode>(N->getOperand(NumVecs + 2))->getZExtValue();
1097 SmallVector<SDValue, 6> Ops;
1098 Ops.push_back(RegSeq);
1099 Ops.push_back(CurDAG->getTargetConstant(LaneNo, MVT::i64));
1100 Ops.push_back(N->getOperand(NumVecs + 3));
1101 Ops.push_back(N->getOperand(0));
1102 SDNode *Ld = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
1103 SDValue SuperReg = SDValue(Ld, 0);
1105 EVT WideVT = RegSeq.getOperand(1)->getValueType(0);
1106 static unsigned QSubs[] = { ARM64::qsub0, ARM64::qsub1, ARM64::qsub2,
1108 for (unsigned i = 0; i < NumVecs; ++i) {
1109 SDValue NV = CurDAG->getTargetExtractSubreg(QSubs[i], dl, WideVT, SuperReg);
1111 NV = NarrowVector(NV, *CurDAG);
1112 ReplaceUses(SDValue(N, i), NV);
1115 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1));
1120 SDNode *ARM64DAGToDAGISel::SelectPostLoadLane(SDNode *N, unsigned NumVecs,
1123 EVT VT = N->getValueType(0);
1124 bool Narrow = VT.getSizeInBits() == 64;
1126 // Form a REG_SEQUENCE to force register allocation.
1127 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs);
1130 std::transform(Regs.begin(), Regs.end(), Regs.begin(),
1131 WidenVector(*CurDAG));
1133 SDValue RegSeq = createQTuple(Regs);
1135 std::vector<EVT> ResTys;
1136 ResTys.push_back(MVT::i64); // Type of the write back register
1137 ResTys.push_back(MVT::Untyped);
1138 ResTys.push_back(MVT::Other);
1141 cast<ConstantSDNode>(N->getOperand(NumVecs + 1))->getZExtValue();
1143 SmallVector<SDValue, 6> Ops;
1144 Ops.push_back(RegSeq);
1145 Ops.push_back(CurDAG->getTargetConstant(LaneNo, MVT::i64)); // Lane Number
1146 Ops.push_back(N->getOperand(NumVecs + 2)); // Base register
1147 Ops.push_back(N->getOperand(NumVecs + 3)); // Incremental
1148 Ops.push_back(N->getOperand(0));
1149 SDNode *Ld = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
1151 // Update uses of the write back register
1152 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 0));
1154 // Update uses of the vector list
1155 SDValue SuperReg = SDValue(Ld, 1);
1156 EVT WideVT = RegSeq.getOperand(1)->getValueType(0);
1157 static unsigned QSubs[] = { ARM64::qsub0, ARM64::qsub1, ARM64::qsub2,
1159 for (unsigned i = 0; i < NumVecs; ++i) {
1160 SDValue NV = CurDAG->getTargetExtractSubreg(QSubs[i], dl, WideVT, SuperReg);
1162 NV = NarrowVector(NV, *CurDAG);
1163 ReplaceUses(SDValue(N, i), NV);
1167 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(Ld, 2));
1172 SDNode *ARM64DAGToDAGISel::SelectStoreLane(SDNode *N, unsigned NumVecs,
1175 EVT VT = N->getOperand(2)->getValueType(0);
1176 bool Narrow = VT.getSizeInBits() == 64;
1178 // Form a REG_SEQUENCE to force register allocation.
1179 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);
1182 std::transform(Regs.begin(), Regs.end(), Regs.begin(),
1183 WidenVector(*CurDAG));
1185 SDValue RegSeq = createQTuple(Regs);
1188 cast<ConstantSDNode>(N->getOperand(NumVecs + 2))->getZExtValue();
1190 SmallVector<SDValue, 6> Ops;
1191 Ops.push_back(RegSeq);
1192 Ops.push_back(CurDAG->getTargetConstant(LaneNo, MVT::i64));
1193 Ops.push_back(N->getOperand(NumVecs + 3));
1194 Ops.push_back(N->getOperand(0));
1195 SDNode *St = CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops);
1197 // Transfer memoperands.
1198 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1199 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1200 cast<MachineSDNode>(St)->setMemRefs(MemOp, MemOp + 1);
1205 SDNode *ARM64DAGToDAGISel::SelectPostStoreLane(SDNode *N, unsigned NumVecs,
1208 EVT VT = N->getOperand(2)->getValueType(0);
1209 bool Narrow = VT.getSizeInBits() == 64;
1211 // Form a REG_SEQUENCE to force register allocation.
1212 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs);
1215 std::transform(Regs.begin(), Regs.end(), Regs.begin(),
1216 WidenVector(*CurDAG));
1218 SDValue RegSeq = createQTuple(Regs);
1220 SmallVector<EVT, 2> ResTys;
1221 ResTys.push_back(MVT::i64); // Type of the write back register
1222 ResTys.push_back(MVT::Other);
1225 cast<ConstantSDNode>(N->getOperand(NumVecs + 1))->getZExtValue();
1227 SmallVector<SDValue, 6> Ops;
1228 Ops.push_back(RegSeq);
1229 Ops.push_back(CurDAG->getTargetConstant(LaneNo, MVT::i64));
1230 Ops.push_back(N->getOperand(NumVecs + 2)); // Base Register
1231 Ops.push_back(N->getOperand(NumVecs + 3)); // Incremental
1232 Ops.push_back(N->getOperand(0));
1233 SDNode *St = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
1235 // Transfer memoperands.
1236 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1237 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1238 cast<MachineSDNode>(St)->setMemRefs(MemOp, MemOp + 1);
1243 static bool isBitfieldExtractOpFromAnd(SelectionDAG *CurDAG, SDNode *N,
1244 unsigned &Opc, SDValue &Opd0,
1245 unsigned &LSB, unsigned &MSB,
1246 unsigned NumberOfIgnoredLowBits,
1247 bool BiggerPattern) {
1248 assert(N->getOpcode() == ISD::AND &&
1249 "N must be a AND operation to call this function");
1251 EVT VT = N->getValueType(0);
1253 // Here we can test the type of VT and return false when the type does not
1254 // match, but since it is done prior to that call in the current context
1255 // we turned that into an assert to avoid redundant code.
1256 assert((VT == MVT::i32 || VT == MVT::i64) &&
1257 "Type checking must have been done before calling this function");
1259 // FIXME: simplify-demanded-bits in DAGCombine will probably have
1260 // changed the AND node to a 32-bit mask operation. We'll have to
1261 // undo that as part of the transform here if we want to catch all
1262 // the opportunities.
1263 // Currently the NumberOfIgnoredLowBits argument helps to recover
1264 // form these situations when matching bigger pattern (bitfield insert).
1266 // For unsigned extracts, check for a shift right and mask
1267 uint64_t And_imm = 0;
1268 if (!isOpcWithIntImmediate(N, ISD::AND, And_imm))
1271 const SDNode *Op0 = N->getOperand(0).getNode();
1273 // Because of simplify-demanded-bits in DAGCombine, the mask may have been
1274 // simplified. Try to undo that
1275 And_imm |= (1 << NumberOfIgnoredLowBits) - 1;
1277 // The immediate is a mask of the low bits iff imm & (imm+1) == 0
1278 if (And_imm & (And_imm + 1))
1281 bool ClampMSB = false;
1282 uint64_t Srl_imm = 0;
1283 // Handle the SRL + ANY_EXTEND case.
1284 if (VT == MVT::i64 && Op0->getOpcode() == ISD::ANY_EXTEND &&
1285 isOpcWithIntImmediate(Op0->getOperand(0).getNode(), ISD::SRL, Srl_imm)) {
1286 // Extend the incoming operand of the SRL to 64-bit.
1287 Opd0 = Widen(CurDAG, Op0->getOperand(0).getOperand(0));
1288 // Make sure to clamp the MSB so that we preserve the semantics of the
1289 // original operations.
1291 } else if (VT == MVT::i32 && Op0->getOpcode() == ISD::TRUNCATE &&
1292 isOpcWithIntImmediate(Op0->getOperand(0).getNode(), ISD::SRL,
1294 // If the shift result was truncated, we can still combine them.
1295 Opd0 = Op0->getOperand(0).getOperand(0);
1297 // Use the type of SRL node.
1298 VT = Opd0->getValueType(0);
1299 } else if (isOpcWithIntImmediate(Op0, ISD::SRL, Srl_imm)) {
1300 Opd0 = Op0->getOperand(0);
1301 } else if (BiggerPattern) {
1302 // Let's pretend a 0 shift right has been performed.
1303 // The resulting code will be at least as good as the original one
1304 // plus it may expose more opportunities for bitfield insert pattern.
1305 // FIXME: Currently we limit this to the bigger pattern, because
1306 // some optimizations expect AND and not UBFM
1307 Opd0 = N->getOperand(0);
1311 assert((BiggerPattern || (Srl_imm > 0 && Srl_imm < VT.getSizeInBits())) &&
1312 "bad amount in shift node!");
1315 MSB = Srl_imm + (VT == MVT::i32 ? CountTrailingOnes_32(And_imm)
1316 : CountTrailingOnes_64(And_imm)) -
1319 // Since we're moving the extend before the right shift operation, we need
1320 // to clamp the MSB to make sure we don't shift in undefined bits instead of
1321 // the zeros which would get shifted in with the original right shift
1323 MSB = MSB > 31 ? 31 : MSB;
1325 Opc = VT == MVT::i32 ? ARM64::UBFMWri : ARM64::UBFMXri;
1329 static bool isOneBitExtractOpFromShr(SDNode *N, unsigned &Opc, SDValue &Opd0,
1330 unsigned &LSB, unsigned &MSB) {
1331 // We are looking for the following pattern which basically extracts a single
1332 // bit from the source value and places it in the LSB of the destination
1333 // value, all other bits of the destination value or set to zero:
1335 // Value2 = AND Value, MaskImm
1336 // SRL Value2, ShiftImm
1338 // with MaskImm >> ShiftImm == 1.
1340 // This gets selected into a single UBFM:
1342 // UBFM Value, ShiftImm, ShiftImm
1345 if (N->getOpcode() != ISD::SRL)
1348 uint64_t And_mask = 0;
1349 if (!isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, And_mask))
1352 Opd0 = N->getOperand(0).getOperand(0);
1354 uint64_t Srl_imm = 0;
1355 if (!isIntImmediate(N->getOperand(1), Srl_imm))
1358 // Check whether we really have a one bit extract here.
1359 if (And_mask >> Srl_imm == 0x1) {
1360 if (N->getValueType(0) == MVT::i32)
1361 Opc = ARM64::UBFMWri;
1363 Opc = ARM64::UBFMXri;
1365 LSB = MSB = Srl_imm;
1373 static bool isBitfieldExtractOpFromShr(SDNode *N, unsigned &Opc, SDValue &Opd0,
1374 unsigned &LSB, unsigned &MSB,
1375 bool BiggerPattern) {
1376 assert((N->getOpcode() == ISD::SRA || N->getOpcode() == ISD::SRL) &&
1377 "N must be a SHR/SRA operation to call this function");
1379 EVT VT = N->getValueType(0);
1381 // Here we can test the type of VT and return false when the type does not
1382 // match, but since it is done prior to that call in the current context
1383 // we turned that into an assert to avoid redundant code.
1384 assert((VT == MVT::i32 || VT == MVT::i64) &&
1385 "Type checking must have been done before calling this function");
1387 // Check for AND + SRL doing a one bit extract.
1388 if (isOneBitExtractOpFromShr(N, Opc, Opd0, LSB, MSB))
1391 // we're looking for a shift of a shift
1392 uint64_t Shl_imm = 0;
1393 uint64_t Trunc_bits = 0;
1394 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SHL, Shl_imm)) {
1395 Opd0 = N->getOperand(0).getOperand(0);
1396 } else if (VT == MVT::i32 && N->getOpcode() == ISD::SRL &&
1397 N->getOperand(0).getNode()->getOpcode() == ISD::TRUNCATE) {
1398 // We are looking for a shift of truncate. Truncate from i64 to i32 could
1399 // be considered as setting high 32 bits as zero. Our strategy here is to
1400 // always generate 64bit UBFM. This consistency will help the CSE pass
1401 // later find more redundancy.
1402 Opd0 = N->getOperand(0).getOperand(0);
1403 Trunc_bits = Opd0->getValueType(0).getSizeInBits() - VT.getSizeInBits();
1404 VT = Opd0->getValueType(0);
1405 assert(VT == MVT::i64 && "the promoted type should be i64");
1406 } else if (BiggerPattern) {
1407 // Let's pretend a 0 shift left has been performed.
1408 // FIXME: Currently we limit this to the bigger pattern case,
1409 // because some optimizations expect AND and not UBFM
1410 Opd0 = N->getOperand(0);
1414 assert(Shl_imm < VT.getSizeInBits() && "bad amount in shift node!");
1415 uint64_t Srl_imm = 0;
1416 if (!isIntImmediate(N->getOperand(1), Srl_imm))
1419 assert(Srl_imm > 0 && Srl_imm < VT.getSizeInBits() &&
1420 "bad amount in shift node!");
1421 // Note: The width operand is encoded as width-1.
1422 unsigned Width = VT.getSizeInBits() - Trunc_bits - Srl_imm - 1;
1423 int sLSB = Srl_imm - Shl_imm;
1428 // SRA requires a signed extraction
1430 Opc = N->getOpcode() == ISD::SRA ? ARM64::SBFMWri : ARM64::UBFMWri;
1432 Opc = N->getOpcode() == ISD::SRA ? ARM64::SBFMXri : ARM64::UBFMXri;
1436 static bool isBitfieldExtractOp(SelectionDAG *CurDAG, SDNode *N, unsigned &Opc,
1437 SDValue &Opd0, unsigned &LSB, unsigned &MSB,
1438 unsigned NumberOfIgnoredLowBits = 0,
1439 bool BiggerPattern = false) {
1440 if (N->getValueType(0) != MVT::i32 && N->getValueType(0) != MVT::i64)
1443 switch (N->getOpcode()) {
1445 if (!N->isMachineOpcode())
1449 return isBitfieldExtractOpFromAnd(CurDAG, N, Opc, Opd0, LSB, MSB,
1450 NumberOfIgnoredLowBits, BiggerPattern);
1453 return isBitfieldExtractOpFromShr(N, Opc, Opd0, LSB, MSB, BiggerPattern);
1456 unsigned NOpc = N->getMachineOpcode();
1460 case ARM64::SBFMWri:
1461 case ARM64::UBFMWri:
1462 case ARM64::SBFMXri:
1463 case ARM64::UBFMXri:
1465 Opd0 = N->getOperand(0);
1466 LSB = cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
1467 MSB = cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
1474 SDNode *ARM64DAGToDAGISel::SelectBitfieldExtractOp(SDNode *N) {
1475 unsigned Opc, LSB, MSB;
1477 if (!isBitfieldExtractOp(CurDAG, N, Opc, Opd0, LSB, MSB))
1480 EVT VT = N->getValueType(0);
1482 // If the bit extract operation is 64bit but the original type is 32bit, we
1483 // need to add one EXTRACT_SUBREG.
1484 if ((Opc == ARM64::SBFMXri || Opc == ARM64::UBFMXri) && VT == MVT::i32) {
1485 SDValue Ops64[] = {Opd0, CurDAG->getTargetConstant(LSB, MVT::i64),
1486 CurDAG->getTargetConstant(MSB, MVT::i64)};
1488 SDNode *BFM = CurDAG->getMachineNode(Opc, SDLoc(N), MVT::i64, Ops64);
1489 SDValue SubReg = CurDAG->getTargetConstant(ARM64::sub_32, MVT::i32);
1490 MachineSDNode *Node =
1491 CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, SDLoc(N), MVT::i32,
1492 SDValue(BFM, 0), SubReg);
1496 SDValue Ops[] = {Opd0, CurDAG->getTargetConstant(LSB, VT),
1497 CurDAG->getTargetConstant(MSB, VT)};
1498 return CurDAG->SelectNodeTo(N, Opc, VT, Ops);
1501 /// Does DstMask form a complementary pair with the mask provided by
1502 /// BitsToBeInserted, suitable for use in a BFI instruction. Roughly speaking,
1503 /// this asks whether DstMask zeroes precisely those bits that will be set by
1505 static bool isBitfieldDstMask(uint64_t DstMask, APInt BitsToBeInserted,
1506 unsigned NumberOfIgnoredHighBits, EVT VT) {
1507 assert((VT == MVT::i32 || VT == MVT::i64) &&
1508 "i32 or i64 mask type expected!");
1509 unsigned BitWidth = VT.getSizeInBits() - NumberOfIgnoredHighBits;
1511 APInt SignificantDstMask = APInt(BitWidth, DstMask);
1512 APInt SignificantBitsToBeInserted = BitsToBeInserted.zextOrTrunc(BitWidth);
1514 return (SignificantDstMask & SignificantBitsToBeInserted) == 0 &&
1515 (SignificantDstMask | SignificantBitsToBeInserted).isAllOnesValue();
1518 // Look for bits that will be useful for later uses.
1519 // A bit is consider useless as soon as it is dropped and never used
1520 // before it as been dropped.
1521 // E.g., looking for useful bit of x
1524 // After #1, x useful bits are 0x7, then the useful bits of x, live through
1526 // After #2, the useful bits of x are 0x4.
1527 // However, if x is used on an unpredicatable instruction, then all its bits
1533 static void getUsefulBits(SDValue Op, APInt &UsefulBits, unsigned Depth = 0);
1535 static void getUsefulBitsFromAndWithImmediate(SDValue Op, APInt &UsefulBits,
1538 cast<const ConstantSDNode>(Op.getOperand(1).getNode())->getZExtValue();
1539 Imm = ARM64_AM::decodeLogicalImmediate(Imm, UsefulBits.getBitWidth());
1540 UsefulBits &= APInt(UsefulBits.getBitWidth(), Imm);
1541 getUsefulBits(Op, UsefulBits, Depth + 1);
1544 static void getUsefulBitsFromBitfieldMoveOpd(SDValue Op, APInt &UsefulBits,
1545 uint64_t Imm, uint64_t MSB,
1547 // inherit the bitwidth value
1548 APInt OpUsefulBits(UsefulBits);
1552 OpUsefulBits = OpUsefulBits.shl(MSB - Imm + 1);
1554 // The interesting part will be in the lower part of the result
1555 getUsefulBits(Op, OpUsefulBits, Depth + 1);
1556 // The interesting part was starting at Imm in the argument
1557 OpUsefulBits = OpUsefulBits.shl(Imm);
1559 OpUsefulBits = OpUsefulBits.shl(MSB + 1);
1561 // The interesting part will be shifted in the result
1562 OpUsefulBits = OpUsefulBits.shl(OpUsefulBits.getBitWidth() - Imm);
1563 getUsefulBits(Op, OpUsefulBits, Depth + 1);
1564 // The interesting part was at zero in the argument
1565 OpUsefulBits = OpUsefulBits.lshr(OpUsefulBits.getBitWidth() - Imm);
1568 UsefulBits &= OpUsefulBits;
1571 static void getUsefulBitsFromUBFM(SDValue Op, APInt &UsefulBits,
1574 cast<const ConstantSDNode>(Op.getOperand(1).getNode())->getZExtValue();
1576 cast<const ConstantSDNode>(Op.getOperand(2).getNode())->getZExtValue();
1578 getUsefulBitsFromBitfieldMoveOpd(Op, UsefulBits, Imm, MSB, Depth);
1581 static void getUsefulBitsFromOrWithShiftedReg(SDValue Op, APInt &UsefulBits,
1583 uint64_t ShiftTypeAndValue =
1584 cast<const ConstantSDNode>(Op.getOperand(2).getNode())->getZExtValue();
1585 APInt Mask(UsefulBits);
1586 Mask.clearAllBits();
1589 if (ARM64_AM::getShiftType(ShiftTypeAndValue) == ARM64_AM::LSL) {
1591 uint64_t ShiftAmt = ARM64_AM::getShiftValue(ShiftTypeAndValue);
1592 Mask = Mask.shl(ShiftAmt);
1593 getUsefulBits(Op, Mask, Depth + 1);
1594 Mask = Mask.lshr(ShiftAmt);
1595 } else if (ARM64_AM::getShiftType(ShiftTypeAndValue) == ARM64_AM::LSR) {
1597 // We do not handle ARM64_AM::ASR, because the sign will change the
1598 // number of useful bits
1599 uint64_t ShiftAmt = ARM64_AM::getShiftValue(ShiftTypeAndValue);
1600 Mask = Mask.lshr(ShiftAmt);
1601 getUsefulBits(Op, Mask, Depth + 1);
1602 Mask = Mask.shl(ShiftAmt);
1609 static void getUsefulBitsFromBFM(SDValue Op, SDValue Orig, APInt &UsefulBits,
1612 cast<const ConstantSDNode>(Op.getOperand(2).getNode())->getZExtValue();
1614 cast<const ConstantSDNode>(Op.getOperand(3).getNode())->getZExtValue();
1616 if (Op.getOperand(1) == Orig)
1617 return getUsefulBitsFromBitfieldMoveOpd(Op, UsefulBits, Imm, MSB, Depth);
1619 APInt OpUsefulBits(UsefulBits);
1623 OpUsefulBits = OpUsefulBits.shl(MSB - Imm + 1);
1625 UsefulBits &= ~OpUsefulBits;
1626 getUsefulBits(Op, UsefulBits, Depth + 1);
1628 OpUsefulBits = OpUsefulBits.shl(MSB + 1);
1630 UsefulBits = ~(OpUsefulBits.shl(OpUsefulBits.getBitWidth() - Imm));
1631 getUsefulBits(Op, UsefulBits, Depth + 1);
1635 static void getUsefulBitsForUse(SDNode *UserNode, APInt &UsefulBits,
1636 SDValue Orig, unsigned Depth) {
1638 // Users of this node should have already been instruction selected
1639 // FIXME: Can we turn that into an assert?
1640 if (!UserNode->isMachineOpcode())
1643 switch (UserNode->getMachineOpcode()) {
1646 case ARM64::ANDSWri:
1647 case ARM64::ANDSXri:
1650 // We increment Depth only when we call the getUsefulBits
1651 return getUsefulBitsFromAndWithImmediate(SDValue(UserNode, 0), UsefulBits,
1653 case ARM64::UBFMWri:
1654 case ARM64::UBFMXri:
1655 return getUsefulBitsFromUBFM(SDValue(UserNode, 0), UsefulBits, Depth);
1659 if (UserNode->getOperand(1) != Orig)
1661 return getUsefulBitsFromOrWithShiftedReg(SDValue(UserNode, 0), UsefulBits,
1665 return getUsefulBitsFromBFM(SDValue(UserNode, 0), Orig, UsefulBits, Depth);
1669 static void getUsefulBits(SDValue Op, APInt &UsefulBits, unsigned Depth) {
1672 // Initialize UsefulBits
1674 unsigned Bitwidth = Op.getValueType().getScalarType().getSizeInBits();
1675 // At the beginning, assume every produced bits is useful
1676 UsefulBits = APInt(Bitwidth, 0);
1677 UsefulBits.flipAllBits();
1679 APInt UsersUsefulBits(UsefulBits.getBitWidth(), 0);
1681 for (SDNode *Node : Op.getNode()->uses()) {
1682 // A use cannot produce useful bits
1683 APInt UsefulBitsForUse = APInt(UsefulBits);
1684 getUsefulBitsForUse(Node, UsefulBitsForUse, Op, Depth);
1685 UsersUsefulBits |= UsefulBitsForUse;
1687 // UsefulBits contains the produced bits that are meaningful for the
1688 // current definition, thus a user cannot make a bit meaningful at
1690 UsefulBits &= UsersUsefulBits;
1693 /// Create a machine node performing a notional SHL of Op by ShlAmount. If
1694 /// ShlAmount is negative, do a (logical) right-shift instead. If ShlAmount is
1695 /// 0, return Op unchanged.
1696 static SDValue getLeftShift(SelectionDAG *CurDAG, SDValue Op, int ShlAmount) {
1700 EVT VT = Op.getValueType();
1701 unsigned BitWidth = VT.getSizeInBits();
1702 unsigned UBFMOpc = BitWidth == 32 ? ARM64::UBFMWri : ARM64::UBFMXri;
1705 if (ShlAmount > 0) {
1706 // LSL wD, wN, #Amt == UBFM wD, wN, #32-Amt, #31-Amt
1707 ShiftNode = CurDAG->getMachineNode(
1708 UBFMOpc, SDLoc(Op), VT, Op,
1709 CurDAG->getTargetConstant(BitWidth - ShlAmount, VT),
1710 CurDAG->getTargetConstant(BitWidth - 1 - ShlAmount, VT));
1712 // LSR wD, wN, #Amt == UBFM wD, wN, #Amt, #32-1
1713 assert(ShlAmount < 0 && "expected right shift");
1714 int ShrAmount = -ShlAmount;
1715 ShiftNode = CurDAG->getMachineNode(
1716 UBFMOpc, SDLoc(Op), VT, Op, CurDAG->getTargetConstant(ShrAmount, VT),
1717 CurDAG->getTargetConstant(BitWidth - 1, VT));
1720 return SDValue(ShiftNode, 0);
1723 /// Does this tree qualify as an attempt to move a bitfield into position,
1724 /// essentially "(and (shl VAL, N), Mask)".
1725 static bool isBitfieldPositioningOp(SelectionDAG *CurDAG, SDValue Op,
1726 SDValue &Src, int &ShiftAmount,
1728 EVT VT = Op.getValueType();
1729 unsigned BitWidth = VT.getSizeInBits();
1731 assert(BitWidth == 32 || BitWidth == 64);
1733 APInt KnownZero, KnownOne;
1734 CurDAG->ComputeMaskedBits(Op, KnownZero, KnownOne);
1736 // Non-zero in the sense that they're not provably zero, which is the key
1737 // point if we want to use this value
1738 uint64_t NonZeroBits = (~KnownZero).getZExtValue();
1740 // Discard a constant AND mask if present. It's safe because the node will
1741 // already have been factored into the ComputeMaskedBits calculation above.
1743 if (isOpcWithIntImmediate(Op.getNode(), ISD::AND, AndImm)) {
1744 assert((~APInt(BitWidth, AndImm) & ~KnownZero) == 0);
1745 Op = Op.getOperand(0);
1749 if (!isOpcWithIntImmediate(Op.getNode(), ISD::SHL, ShlImm))
1751 Op = Op.getOperand(0);
1753 if (!isShiftedMask_64(NonZeroBits))
1756 ShiftAmount = countTrailingZeros(NonZeroBits);
1757 MaskWidth = CountTrailingOnes_64(NonZeroBits >> ShiftAmount);
1759 // BFI encompasses sufficiently many nodes that it's worth inserting an extra
1760 // LSL/LSR if the mask in NonZeroBits doesn't quite match up with the ISD::SHL
1762 Src = getLeftShift(CurDAG, Op, ShlImm - ShiftAmount);
1767 // Given a OR operation, check if we have the following pattern
1768 // ubfm c, b, imm, imm2 (or something that does the same jobs, see
1769 // isBitfieldExtractOp)
1770 // d = e & mask2 ; where mask is a binary sequence of 1..10..0 and
1771 // countTrailingZeros(mask2) == imm2 - imm + 1
1773 // if yes, given reference arguments will be update so that one can replace
1774 // the OR instruction with:
1775 // f = Opc Opd0, Opd1, LSB, MSB ; where Opc is a BFM, LSB = imm, and MSB = imm2
1776 static bool isBitfieldInsertOpFromOr(SDNode *N, unsigned &Opc, SDValue &Dst,
1777 SDValue &Src, unsigned &ImmR,
1778 unsigned &ImmS, SelectionDAG *CurDAG) {
1779 assert(N->getOpcode() == ISD::OR && "Expect a OR operation");
1782 EVT VT = N->getValueType(0);
1784 Opc = ARM64::BFMWri;
1785 else if (VT == MVT::i64)
1786 Opc = ARM64::BFMXri;
1790 // Because of simplify-demanded-bits in DAGCombine, involved masks may not
1791 // have the expected shape. Try to undo that.
1793 getUsefulBits(SDValue(N, 0), UsefulBits);
1795 unsigned NumberOfIgnoredLowBits = UsefulBits.countTrailingZeros();
1796 unsigned NumberOfIgnoredHighBits = UsefulBits.countLeadingZeros();
1798 // OR is commutative, check both possibilities (does llvm provide a
1799 // way to do that directely, e.g., via code matcher?)
1800 SDValue OrOpd1Val = N->getOperand(1);
1801 SDNode *OrOpd0 = N->getOperand(0).getNode();
1802 SDNode *OrOpd1 = N->getOperand(1).getNode();
1803 for (int i = 0; i < 2;
1804 ++i, std::swap(OrOpd0, OrOpd1), OrOpd1Val = N->getOperand(0)) {
1807 if (isBitfieldExtractOp(CurDAG, OrOpd0, BFXOpc, Src, ImmR, ImmS,
1808 NumberOfIgnoredLowBits, true)) {
1809 // Check that the returned opcode is compatible with the pattern,
1810 // i.e., same type and zero extended (U and not S)
1811 if ((BFXOpc != ARM64::UBFMXri && VT == MVT::i64) ||
1812 (BFXOpc != ARM64::UBFMWri && VT == MVT::i32))
1815 // Compute the width of the bitfield insertion
1817 Width = ImmS - ImmR + 1;
1818 // FIXME: This constraint is to catch bitfield insertion we may
1819 // want to widen the pattern if we want to grab general bitfied
1824 // If the mask on the insertee is correct, we have a BFXIL operation. We
1825 // can share the ImmR and ImmS values from the already-computed UBFM.
1826 } else if (isBitfieldPositioningOp(CurDAG, SDValue(OrOpd0, 0), Src,
1828 ImmR = (VT.getSizeInBits() - DstLSB) % VT.getSizeInBits();
1833 // Check the second part of the pattern
1834 EVT VT = OrOpd1->getValueType(0);
1835 assert((VT == MVT::i32 || VT == MVT::i64) && "unexpected OR operand");
1837 // Compute the Known Zero for the candidate of the first operand.
1838 // This allows to catch more general case than just looking for
1839 // AND with imm. Indeed, simplify-demanded-bits may have removed
1840 // the AND instruction because it proves it was useless.
1841 APInt KnownZero, KnownOne;
1842 CurDAG->ComputeMaskedBits(OrOpd1Val, KnownZero, KnownOne);
1844 // Check if there is enough room for the second operand to appear
1846 APInt BitsToBeInserted =
1847 APInt::getBitsSet(KnownZero.getBitWidth(), DstLSB, DstLSB + Width);
1849 if ((BitsToBeInserted & ~KnownZero) != 0)
1852 // Set the first operand
1854 if (isOpcWithIntImmediate(OrOpd1, ISD::AND, Imm) &&
1855 isBitfieldDstMask(Imm, BitsToBeInserted, NumberOfIgnoredHighBits, VT))
1856 // In that case, we can eliminate the AND
1857 Dst = OrOpd1->getOperand(0);
1859 // Maybe the AND has been removed by simplify-demanded-bits
1860 // or is useful because it discards more bits
1870 SDNode *ARM64DAGToDAGISel::SelectBitfieldInsertOp(SDNode *N) {
1871 if (N->getOpcode() != ISD::OR)
1878 if (!isBitfieldInsertOpFromOr(N, Opc, Opd0, Opd1, LSB, MSB, CurDAG))
1881 EVT VT = N->getValueType(0);
1882 SDValue Ops[] = { Opd0,
1884 CurDAG->getTargetConstant(LSB, VT),
1885 CurDAG->getTargetConstant(MSB, VT) };
1886 return CurDAG->SelectNodeTo(N, Opc, VT, Ops);
1889 SDNode *ARM64DAGToDAGISel::SelectLIBM(SDNode *N) {
1890 EVT VT = N->getValueType(0);
1893 unsigned FRINTXOpcs[] = { ARM64::FRINTXSr, ARM64::FRINTXDr };
1895 if (VT == MVT::f32) {
1897 } else if (VT == MVT::f64) {
1900 return nullptr; // Unrecognized argument type. Fall back on default codegen.
1902 // Pick the FRINTX variant needed to set the flags.
1903 unsigned FRINTXOpc = FRINTXOpcs[Variant];
1905 switch (N->getOpcode()) {
1907 return nullptr; // Unrecognized libm ISD node. Fall back on default codegen.
1909 unsigned FRINTPOpcs[] = { ARM64::FRINTPSr, ARM64::FRINTPDr };
1910 Opc = FRINTPOpcs[Variant];
1914 unsigned FRINTMOpcs[] = { ARM64::FRINTMSr, ARM64::FRINTMDr };
1915 Opc = FRINTMOpcs[Variant];
1919 unsigned FRINTZOpcs[] = { ARM64::FRINTZSr, ARM64::FRINTZDr };
1920 Opc = FRINTZOpcs[Variant];
1924 unsigned FRINTAOpcs[] = { ARM64::FRINTASr, ARM64::FRINTADr };
1925 Opc = FRINTAOpcs[Variant];
1931 SDValue In = N->getOperand(0);
1932 SmallVector<SDValue, 2> Ops;
1935 if (!TM.Options.UnsafeFPMath) {
1936 SDNode *FRINTX = CurDAG->getMachineNode(FRINTXOpc, dl, VT, MVT::Glue, In);
1937 Ops.push_back(SDValue(FRINTX, 1));
1940 return CurDAG->getMachineNode(Opc, dl, VT, Ops);
1944 ARM64DAGToDAGISel::SelectCVTFixedPosOperand(SDValue N, SDValue &FixedPos,
1945 unsigned RegWidth) {
1947 if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N))
1948 FVal = CN->getValueAPF();
1949 else if (LoadSDNode *LN = dyn_cast<LoadSDNode>(N)) {
1950 // Some otherwise illegal constants are allowed in this case.
1951 if (LN->getOperand(1).getOpcode() != ARM64ISD::ADDlow ||
1952 !isa<ConstantPoolSDNode>(LN->getOperand(1)->getOperand(1)))
1955 ConstantPoolSDNode *CN =
1956 dyn_cast<ConstantPoolSDNode>(LN->getOperand(1)->getOperand(1));
1957 FVal = cast<ConstantFP>(CN->getConstVal())->getValueAPF();
1961 // An FCVT[SU] instruction performs: convertToInt(Val * 2^fbits) where fbits
1962 // is between 1 and 32 for a destination w-register, or 1 and 64 for an
1965 // By this stage, we've detected (fp_to_[su]int (fmul Val, THIS_NODE)) so we
1966 // want THIS_NODE to be 2^fbits. This is much easier to deal with using
1970 // fbits is between 1 and 64 in the worst-case, which means the fmul
1971 // could have 2^64 as an actual operand. Need 65 bits of precision.
1972 APSInt IntVal(65, true);
1973 FVal.convertToInteger(IntVal, APFloat::rmTowardZero, &IsExact);
1975 // N.b. isPowerOf2 also checks for > 0.
1976 if (!IsExact || !IntVal.isPowerOf2()) return false;
1977 unsigned FBits = IntVal.logBase2();
1979 // Checks above should have guaranteed that we haven't lost information in
1980 // finding FBits, but it must still be in range.
1981 if (FBits == 0 || FBits > RegWidth) return false;
1983 FixedPos = CurDAG->getTargetConstant(FBits, MVT::i32);
1987 SDNode *ARM64DAGToDAGISel::Select(SDNode *Node) {
1988 // Dump information about the Node being selected
1989 DEBUG(errs() << "Selecting: ");
1990 DEBUG(Node->dump(CurDAG));
1991 DEBUG(errs() << "\n");
1993 // If we have a custom node, we already have selected!
1994 if (Node->isMachineOpcode()) {
1995 DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
1996 Node->setNodeId(-1);
2000 // Few custom selection stuff.
2001 SDNode *ResNode = nullptr;
2002 EVT VT = Node->getValueType(0);
2004 switch (Node->getOpcode()) {
2009 if (SDNode *I = SelectMLAV64LaneV128(Node))
2014 // Try to select as an indexed load. Fall through to normal processing
2017 SDNode *I = SelectIndexedLoad(Node, Done);
2026 if (SDNode *I = SelectBitfieldExtractOp(Node))
2031 if (SDNode *I = SelectBitfieldInsertOp(Node))
2035 case ISD::EXTRACT_VECTOR_ELT: {
2036 // Extracting lane zero is a special case where we can just use a plain
2037 // EXTRACT_SUBREG instruction, which will become FMOV. This is easier for
2038 // the rest of the compiler, especially the register allocator and copyi
2039 // propagation, to reason about, so is preferred when it's possible to
2041 ConstantSDNode *LaneNode = cast<ConstantSDNode>(Node->getOperand(1));
2042 // Bail and use the default Select() for non-zero lanes.
2043 if (LaneNode->getZExtValue() != 0)
2045 // If the element type is not the same as the result type, likewise
2046 // bail and use the default Select(), as there's more to do than just
2047 // a cross-class COPY. This catches extracts of i8 and i16 elements
2048 // since they will need an explicit zext.
2049 if (VT != Node->getOperand(0).getValueType().getVectorElementType())
2052 switch (Node->getOperand(0)
2054 .getVectorElementType()
2057 assert(0 && "Unexpected vector element type!");
2059 SubReg = ARM64::dsub;
2062 SubReg = ARM64::ssub;
2064 case 16: // FALLTHROUGH
2066 llvm_unreachable("unexpected zext-requiring extract element!");
2068 SDValue Extract = CurDAG->getTargetExtractSubreg(SubReg, SDLoc(Node), VT,
2069 Node->getOperand(0));
2070 DEBUG(dbgs() << "ISEL: Custom selection!\n=> ");
2071 DEBUG(Extract->dumpr(CurDAG));
2072 DEBUG(dbgs() << "\n");
2073 return Extract.getNode();
2075 case ISD::Constant: {
2076 // Materialize zero constants as copies from WZR/XZR. This allows
2077 // the coalescer to propagate these into other instructions.
2078 ConstantSDNode *ConstNode = cast<ConstantSDNode>(Node);
2079 if (ConstNode->isNullValue()) {
2081 return CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node),
2082 ARM64::WZR, MVT::i32).getNode();
2083 else if (VT == MVT::i64)
2084 return CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node),
2085 ARM64::XZR, MVT::i64).getNode();
2090 case ISD::FrameIndex: {
2091 // Selects to ADDXri FI, 0 which in turn will become ADDXri SP, imm.
2092 int FI = cast<FrameIndexSDNode>(Node)->getIndex();
2093 unsigned Shifter = ARM64_AM::getShifterImm(ARM64_AM::LSL, 0);
2094 const TargetLowering *TLI = getTargetLowering();
2095 SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy());
2096 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
2097 CurDAG->getTargetConstant(Shifter, MVT::i32) };
2098 return CurDAG->SelectNodeTo(Node, ARM64::ADDXri, MVT::i64, Ops);
2100 case ISD::INTRINSIC_W_CHAIN: {
2101 unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
2105 case Intrinsic::arm64_ldaxp:
2106 case Intrinsic::arm64_ldxp: {
2108 IntNo == Intrinsic::arm64_ldaxp ? ARM64::LDAXPX : ARM64::LDXPX;
2109 SDValue MemAddr = Node->getOperand(2);
2111 SDValue Chain = Node->getOperand(0);
2113 SDNode *Ld = CurDAG->getMachineNode(Op, DL, MVT::i64, MVT::i64,
2114 MVT::Other, MemAddr, Chain);
2116 // Transfer memoperands.
2117 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
2118 MemOp[0] = cast<MemIntrinsicSDNode>(Node)->getMemOperand();
2119 cast<MachineSDNode>(Ld)->setMemRefs(MemOp, MemOp + 1);
2122 case Intrinsic::arm64_stlxp:
2123 case Intrinsic::arm64_stxp: {
2125 IntNo == Intrinsic::arm64_stlxp ? ARM64::STLXPX : ARM64::STXPX;
2127 SDValue Chain = Node->getOperand(0);
2128 SDValue ValLo = Node->getOperand(2);
2129 SDValue ValHi = Node->getOperand(3);
2130 SDValue MemAddr = Node->getOperand(4);
2132 // Place arguments in the right order.
2133 SmallVector<SDValue, 7> Ops;
2134 Ops.push_back(ValLo);
2135 Ops.push_back(ValHi);
2136 Ops.push_back(MemAddr);
2137 Ops.push_back(Chain);
2139 SDNode *St = CurDAG->getMachineNode(Op, DL, MVT::i32, MVT::Other, Ops);
2140 // Transfer memoperands.
2141 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
2142 MemOp[0] = cast<MemIntrinsicSDNode>(Node)->getMemOperand();
2143 cast<MachineSDNode>(St)->setMemRefs(MemOp, MemOp + 1);
2147 case Intrinsic::arm64_neon_ld1x2:
2148 if (VT == MVT::v8i8)
2149 return SelectLoad(Node, 2, ARM64::LD1Twov8b, ARM64::dsub0);
2150 else if (VT == MVT::v16i8)
2151 return SelectLoad(Node, 2, ARM64::LD1Twov16b, ARM64::qsub0);
2152 else if (VT == MVT::v4i16)
2153 return SelectLoad(Node, 2, ARM64::LD1Twov4h, ARM64::dsub0);
2154 else if (VT == MVT::v8i16)
2155 return SelectLoad(Node, 2, ARM64::LD1Twov8h, ARM64::qsub0);
2156 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2157 return SelectLoad(Node, 2, ARM64::LD1Twov2s, ARM64::dsub0);
2158 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2159 return SelectLoad(Node, 2, ARM64::LD1Twov4s, ARM64::qsub0);
2160 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2161 return SelectLoad(Node, 2, ARM64::LD1Twov1d, ARM64::dsub0);
2162 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2163 return SelectLoad(Node, 2, ARM64::LD1Twov2d, ARM64::qsub0);
2165 case Intrinsic::arm64_neon_ld1x3:
2166 if (VT == MVT::v8i8)
2167 return SelectLoad(Node, 3, ARM64::LD1Threev8b, ARM64::dsub0);
2168 else if (VT == MVT::v16i8)
2169 return SelectLoad(Node, 3, ARM64::LD1Threev16b, ARM64::qsub0);
2170 else if (VT == MVT::v4i16)
2171 return SelectLoad(Node, 3, ARM64::LD1Threev4h, ARM64::dsub0);
2172 else if (VT == MVT::v8i16)
2173 return SelectLoad(Node, 3, ARM64::LD1Threev8h, ARM64::qsub0);
2174 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2175 return SelectLoad(Node, 3, ARM64::LD1Threev2s, ARM64::dsub0);
2176 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2177 return SelectLoad(Node, 3, ARM64::LD1Threev4s, ARM64::qsub0);
2178 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2179 return SelectLoad(Node, 3, ARM64::LD1Threev1d, ARM64::dsub0);
2180 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2181 return SelectLoad(Node, 3, ARM64::LD1Threev2d, ARM64::qsub0);
2183 case Intrinsic::arm64_neon_ld1x4:
2184 if (VT == MVT::v8i8)
2185 return SelectLoad(Node, 4, ARM64::LD1Fourv8b, ARM64::dsub0);
2186 else if (VT == MVT::v16i8)
2187 return SelectLoad(Node, 4, ARM64::LD1Fourv16b, ARM64::qsub0);
2188 else if (VT == MVT::v4i16)
2189 return SelectLoad(Node, 4, ARM64::LD1Fourv4h, ARM64::dsub0);
2190 else if (VT == MVT::v8i16)
2191 return SelectLoad(Node, 4, ARM64::LD1Fourv8h, ARM64::qsub0);
2192 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2193 return SelectLoad(Node, 4, ARM64::LD1Fourv2s, ARM64::dsub0);
2194 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2195 return SelectLoad(Node, 4, ARM64::LD1Fourv4s, ARM64::qsub0);
2196 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2197 return SelectLoad(Node, 4, ARM64::LD1Fourv1d, ARM64::dsub0);
2198 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2199 return SelectLoad(Node, 4, ARM64::LD1Fourv2d, ARM64::qsub0);
2201 case Intrinsic::arm64_neon_ld2:
2202 if (VT == MVT::v8i8)
2203 return SelectLoad(Node, 2, ARM64::LD2Twov8b, ARM64::dsub0);
2204 else if (VT == MVT::v16i8)
2205 return SelectLoad(Node, 2, ARM64::LD2Twov16b, ARM64::qsub0);
2206 else if (VT == MVT::v4i16)
2207 return SelectLoad(Node, 2, ARM64::LD2Twov4h, ARM64::dsub0);
2208 else if (VT == MVT::v8i16)
2209 return SelectLoad(Node, 2, ARM64::LD2Twov8h, ARM64::qsub0);
2210 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2211 return SelectLoad(Node, 2, ARM64::LD2Twov2s, ARM64::dsub0);
2212 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2213 return SelectLoad(Node, 2, ARM64::LD2Twov4s, ARM64::qsub0);
2214 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2215 return SelectLoad(Node, 2, ARM64::LD1Twov1d, ARM64::dsub0);
2216 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2217 return SelectLoad(Node, 2, ARM64::LD2Twov2d, ARM64::qsub0);
2219 case Intrinsic::arm64_neon_ld3:
2220 if (VT == MVT::v8i8)
2221 return SelectLoad(Node, 3, ARM64::LD3Threev8b, ARM64::dsub0);
2222 else if (VT == MVT::v16i8)
2223 return SelectLoad(Node, 3, ARM64::LD3Threev16b, ARM64::qsub0);
2224 else if (VT == MVT::v4i16)
2225 return SelectLoad(Node, 3, ARM64::LD3Threev4h, ARM64::dsub0);
2226 else if (VT == MVT::v8i16)
2227 return SelectLoad(Node, 3, ARM64::LD3Threev8h, ARM64::qsub0);
2228 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2229 return SelectLoad(Node, 3, ARM64::LD3Threev2s, ARM64::dsub0);
2230 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2231 return SelectLoad(Node, 3, ARM64::LD3Threev4s, ARM64::qsub0);
2232 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2233 return SelectLoad(Node, 3, ARM64::LD1Threev1d, ARM64::dsub0);
2234 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2235 return SelectLoad(Node, 3, ARM64::LD3Threev2d, ARM64::qsub0);
2237 case Intrinsic::arm64_neon_ld4:
2238 if (VT == MVT::v8i8)
2239 return SelectLoad(Node, 4, ARM64::LD4Fourv8b, ARM64::dsub0);
2240 else if (VT == MVT::v16i8)
2241 return SelectLoad(Node, 4, ARM64::LD4Fourv16b, ARM64::qsub0);
2242 else if (VT == MVT::v4i16)
2243 return SelectLoad(Node, 4, ARM64::LD4Fourv4h, ARM64::dsub0);
2244 else if (VT == MVT::v8i16)
2245 return SelectLoad(Node, 4, ARM64::LD4Fourv8h, ARM64::qsub0);
2246 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2247 return SelectLoad(Node, 4, ARM64::LD4Fourv2s, ARM64::dsub0);
2248 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2249 return SelectLoad(Node, 4, ARM64::LD4Fourv4s, ARM64::qsub0);
2250 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2251 return SelectLoad(Node, 4, ARM64::LD1Fourv1d, ARM64::dsub0);
2252 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2253 return SelectLoad(Node, 4, ARM64::LD4Fourv2d, ARM64::qsub0);
2255 case Intrinsic::arm64_neon_ld2r:
2256 if (VT == MVT::v8i8)
2257 return SelectLoad(Node, 2, ARM64::LD2Rv8b, ARM64::dsub0);
2258 else if (VT == MVT::v16i8)
2259 return SelectLoad(Node, 2, ARM64::LD2Rv16b, ARM64::qsub0);
2260 else if (VT == MVT::v4i16)
2261 return SelectLoad(Node, 2, ARM64::LD2Rv4h, ARM64::dsub0);
2262 else if (VT == MVT::v8i16)
2263 return SelectLoad(Node, 2, ARM64::LD2Rv8h, ARM64::qsub0);
2264 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2265 return SelectLoad(Node, 2, ARM64::LD2Rv2s, ARM64::dsub0);
2266 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2267 return SelectLoad(Node, 2, ARM64::LD2Rv4s, ARM64::qsub0);
2268 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2269 return SelectLoad(Node, 2, ARM64::LD2Rv1d, ARM64::dsub0);
2270 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2271 return SelectLoad(Node, 2, ARM64::LD2Rv2d, ARM64::qsub0);
2273 case Intrinsic::arm64_neon_ld3r:
2274 if (VT == MVT::v8i8)
2275 return SelectLoad(Node, 3, ARM64::LD3Rv8b, ARM64::dsub0);
2276 else if (VT == MVT::v16i8)
2277 return SelectLoad(Node, 3, ARM64::LD3Rv16b, ARM64::qsub0);
2278 else if (VT == MVT::v4i16)
2279 return SelectLoad(Node, 3, ARM64::LD3Rv4h, ARM64::dsub0);
2280 else if (VT == MVT::v8i16)
2281 return SelectLoad(Node, 3, ARM64::LD3Rv8h, ARM64::qsub0);
2282 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2283 return SelectLoad(Node, 3, ARM64::LD3Rv2s, ARM64::dsub0);
2284 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2285 return SelectLoad(Node, 3, ARM64::LD3Rv4s, ARM64::qsub0);
2286 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2287 return SelectLoad(Node, 3, ARM64::LD3Rv1d, ARM64::dsub0);
2288 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2289 return SelectLoad(Node, 3, ARM64::LD3Rv2d, ARM64::qsub0);
2291 case Intrinsic::arm64_neon_ld4r:
2292 if (VT == MVT::v8i8)
2293 return SelectLoad(Node, 4, ARM64::LD4Rv8b, ARM64::dsub0);
2294 else if (VT == MVT::v16i8)
2295 return SelectLoad(Node, 4, ARM64::LD4Rv16b, ARM64::qsub0);
2296 else if (VT == MVT::v4i16)
2297 return SelectLoad(Node, 4, ARM64::LD4Rv4h, ARM64::dsub0);
2298 else if (VT == MVT::v8i16)
2299 return SelectLoad(Node, 4, ARM64::LD4Rv8h, ARM64::qsub0);
2300 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2301 return SelectLoad(Node, 4, ARM64::LD4Rv2s, ARM64::dsub0);
2302 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2303 return SelectLoad(Node, 4, ARM64::LD4Rv4s, ARM64::qsub0);
2304 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2305 return SelectLoad(Node, 4, ARM64::LD4Rv1d, ARM64::dsub0);
2306 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2307 return SelectLoad(Node, 4, ARM64::LD4Rv2d, ARM64::qsub0);
2309 case Intrinsic::arm64_neon_ld2lane:
2310 if (VT == MVT::v16i8 || VT == MVT::v8i8)
2311 return SelectLoadLane(Node, 2, ARM64::LD2i8);
2312 else if (VT == MVT::v8i16 || VT == MVT::v4i16)
2313 return SelectLoadLane(Node, 2, ARM64::LD2i16);
2314 else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
2316 return SelectLoadLane(Node, 2, ARM64::LD2i32);
2317 else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
2319 return SelectLoadLane(Node, 2, ARM64::LD2i64);
2321 case Intrinsic::arm64_neon_ld3lane:
2322 if (VT == MVT::v16i8 || VT == MVT::v8i8)
2323 return SelectLoadLane(Node, 3, ARM64::LD3i8);
2324 else if (VT == MVT::v8i16 || VT == MVT::v4i16)
2325 return SelectLoadLane(Node, 3, ARM64::LD3i16);
2326 else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
2328 return SelectLoadLane(Node, 3, ARM64::LD3i32);
2329 else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
2331 return SelectLoadLane(Node, 3, ARM64::LD3i64);
2333 case Intrinsic::arm64_neon_ld4lane:
2334 if (VT == MVT::v16i8 || VT == MVT::v8i8)
2335 return SelectLoadLane(Node, 4, ARM64::LD4i8);
2336 else if (VT == MVT::v8i16 || VT == MVT::v4i16)
2337 return SelectLoadLane(Node, 4, ARM64::LD4i16);
2338 else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
2340 return SelectLoadLane(Node, 4, ARM64::LD4i32);
2341 else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
2343 return SelectLoadLane(Node, 4, ARM64::LD4i64);
2347 case ISD::INTRINSIC_WO_CHAIN: {
2348 unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
2352 case Intrinsic::arm64_neon_tbl2:
2353 return SelectTable(Node, 2, VT == MVT::v8i8 ? ARM64::TBLv8i8Two
2354 : ARM64::TBLv16i8Two,
2356 case Intrinsic::arm64_neon_tbl3:
2357 return SelectTable(Node, 3, VT == MVT::v8i8 ? ARM64::TBLv8i8Three
2358 : ARM64::TBLv16i8Three,
2360 case Intrinsic::arm64_neon_tbl4:
2361 return SelectTable(Node, 4, VT == MVT::v8i8 ? ARM64::TBLv8i8Four
2362 : ARM64::TBLv16i8Four,
2364 case Intrinsic::arm64_neon_tbx2:
2365 return SelectTable(Node, 2, VT == MVT::v8i8 ? ARM64::TBXv8i8Two
2366 : ARM64::TBXv16i8Two,
2368 case Intrinsic::arm64_neon_tbx3:
2369 return SelectTable(Node, 3, VT == MVT::v8i8 ? ARM64::TBXv8i8Three
2370 : ARM64::TBXv16i8Three,
2372 case Intrinsic::arm64_neon_tbx4:
2373 return SelectTable(Node, 4, VT == MVT::v8i8 ? ARM64::TBXv8i8Four
2374 : ARM64::TBXv16i8Four,
2376 case Intrinsic::arm64_neon_smull:
2377 case Intrinsic::arm64_neon_umull:
2378 if (SDNode *N = SelectMULLV64LaneV128(IntNo, Node))
2384 case ISD::INTRINSIC_VOID: {
2385 unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
2386 if (Node->getNumOperands() >= 3)
2387 VT = Node->getOperand(2)->getValueType(0);
2391 case Intrinsic::arm64_neon_st1x2: {
2392 if (VT == MVT::v8i8)
2393 return SelectStore(Node, 2, ARM64::ST1Twov8b);
2394 else if (VT == MVT::v16i8)
2395 return SelectStore(Node, 2, ARM64::ST1Twov16b);
2396 else if (VT == MVT::v4i16)
2397 return SelectStore(Node, 2, ARM64::ST1Twov4h);
2398 else if (VT == MVT::v8i16)
2399 return SelectStore(Node, 2, ARM64::ST1Twov8h);
2400 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2401 return SelectStore(Node, 2, ARM64::ST1Twov2s);
2402 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2403 return SelectStore(Node, 2, ARM64::ST1Twov4s);
2404 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2405 return SelectStore(Node, 2, ARM64::ST1Twov2d);
2406 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2407 return SelectStore(Node, 2, ARM64::ST1Twov1d);
2410 case Intrinsic::arm64_neon_st1x3: {
2411 if (VT == MVT::v8i8)
2412 return SelectStore(Node, 3, ARM64::ST1Threev8b);
2413 else if (VT == MVT::v16i8)
2414 return SelectStore(Node, 3, ARM64::ST1Threev16b);
2415 else if (VT == MVT::v4i16)
2416 return SelectStore(Node, 3, ARM64::ST1Threev4h);
2417 else if (VT == MVT::v8i16)
2418 return SelectStore(Node, 3, ARM64::ST1Threev8h);
2419 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2420 return SelectStore(Node, 3, ARM64::ST1Threev2s);
2421 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2422 return SelectStore(Node, 3, ARM64::ST1Threev4s);
2423 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2424 return SelectStore(Node, 3, ARM64::ST1Threev2d);
2425 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2426 return SelectStore(Node, 3, ARM64::ST1Threev1d);
2429 case Intrinsic::arm64_neon_st1x4: {
2430 if (VT == MVT::v8i8)
2431 return SelectStore(Node, 4, ARM64::ST1Fourv8b);
2432 else if (VT == MVT::v16i8)
2433 return SelectStore(Node, 4, ARM64::ST1Fourv16b);
2434 else if (VT == MVT::v4i16)
2435 return SelectStore(Node, 4, ARM64::ST1Fourv4h);
2436 else if (VT == MVT::v8i16)
2437 return SelectStore(Node, 4, ARM64::ST1Fourv8h);
2438 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2439 return SelectStore(Node, 4, ARM64::ST1Fourv2s);
2440 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2441 return SelectStore(Node, 4, ARM64::ST1Fourv4s);
2442 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2443 return SelectStore(Node, 4, ARM64::ST1Fourv2d);
2444 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2445 return SelectStore(Node, 4, ARM64::ST1Fourv1d);
2448 case Intrinsic::arm64_neon_st2: {
2449 if (VT == MVT::v8i8)
2450 return SelectStore(Node, 2, ARM64::ST2Twov8b);
2451 else if (VT == MVT::v16i8)
2452 return SelectStore(Node, 2, ARM64::ST2Twov16b);
2453 else if (VT == MVT::v4i16)
2454 return SelectStore(Node, 2, ARM64::ST2Twov4h);
2455 else if (VT == MVT::v8i16)
2456 return SelectStore(Node, 2, ARM64::ST2Twov8h);
2457 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2458 return SelectStore(Node, 2, ARM64::ST2Twov2s);
2459 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2460 return SelectStore(Node, 2, ARM64::ST2Twov4s);
2461 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2462 return SelectStore(Node, 2, ARM64::ST2Twov2d);
2463 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2464 return SelectStore(Node, 2, ARM64::ST1Twov1d);
2467 case Intrinsic::arm64_neon_st3: {
2468 if (VT == MVT::v8i8)
2469 return SelectStore(Node, 3, ARM64::ST3Threev8b);
2470 else if (VT == MVT::v16i8)
2471 return SelectStore(Node, 3, ARM64::ST3Threev16b);
2472 else if (VT == MVT::v4i16)
2473 return SelectStore(Node, 3, ARM64::ST3Threev4h);
2474 else if (VT == MVT::v8i16)
2475 return SelectStore(Node, 3, ARM64::ST3Threev8h);
2476 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2477 return SelectStore(Node, 3, ARM64::ST3Threev2s);
2478 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2479 return SelectStore(Node, 3, ARM64::ST3Threev4s);
2480 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2481 return SelectStore(Node, 3, ARM64::ST3Threev2d);
2482 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2483 return SelectStore(Node, 3, ARM64::ST1Threev1d);
2486 case Intrinsic::arm64_neon_st4: {
2487 if (VT == MVT::v8i8)
2488 return SelectStore(Node, 4, ARM64::ST4Fourv8b);
2489 else if (VT == MVT::v16i8)
2490 return SelectStore(Node, 4, ARM64::ST4Fourv16b);
2491 else if (VT == MVT::v4i16)
2492 return SelectStore(Node, 4, ARM64::ST4Fourv4h);
2493 else if (VT == MVT::v8i16)
2494 return SelectStore(Node, 4, ARM64::ST4Fourv8h);
2495 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2496 return SelectStore(Node, 4, ARM64::ST4Fourv2s);
2497 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2498 return SelectStore(Node, 4, ARM64::ST4Fourv4s);
2499 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2500 return SelectStore(Node, 4, ARM64::ST4Fourv2d);
2501 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2502 return SelectStore(Node, 4, ARM64::ST1Fourv1d);
2505 case Intrinsic::arm64_neon_st2lane: {
2506 if (VT == MVT::v16i8 || VT == MVT::v8i8)
2507 return SelectStoreLane(Node, 2, ARM64::ST2i8);
2508 else if (VT == MVT::v8i16 || VT == MVT::v4i16)
2509 return SelectStoreLane(Node, 2, ARM64::ST2i16);
2510 else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
2512 return SelectStoreLane(Node, 2, ARM64::ST2i32);
2513 else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
2515 return SelectStoreLane(Node, 2, ARM64::ST2i64);
2518 case Intrinsic::arm64_neon_st3lane: {
2519 if (VT == MVT::v16i8 || VT == MVT::v8i8)
2520 return SelectStoreLane(Node, 3, ARM64::ST3i8);
2521 else if (VT == MVT::v8i16 || VT == MVT::v4i16)
2522 return SelectStoreLane(Node, 3, ARM64::ST3i16);
2523 else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
2525 return SelectStoreLane(Node, 3, ARM64::ST3i32);
2526 else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
2528 return SelectStoreLane(Node, 3, ARM64::ST3i64);
2531 case Intrinsic::arm64_neon_st4lane: {
2532 if (VT == MVT::v16i8 || VT == MVT::v8i8)
2533 return SelectStoreLane(Node, 4, ARM64::ST4i8);
2534 else if (VT == MVT::v8i16 || VT == MVT::v4i16)
2535 return SelectStoreLane(Node, 4, ARM64::ST4i16);
2536 else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
2538 return SelectStoreLane(Node, 4, ARM64::ST4i32);
2539 else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
2541 return SelectStoreLane(Node, 4, ARM64::ST4i64);
2546 case ARM64ISD::LD2post: {
2547 if (VT == MVT::v8i8)
2548 return SelectPostLoad(Node, 2, ARM64::LD2Twov8b_POST, ARM64::dsub0);
2549 else if (VT == MVT::v16i8)
2550 return SelectPostLoad(Node, 2, ARM64::LD2Twov16b_POST, ARM64::qsub0);
2551 else if (VT == MVT::v4i16)
2552 return SelectPostLoad(Node, 2, ARM64::LD2Twov4h_POST, ARM64::dsub0);
2553 else if (VT == MVT::v8i16)
2554 return SelectPostLoad(Node, 2, ARM64::LD2Twov8h_POST, ARM64::qsub0);
2555 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2556 return SelectPostLoad(Node, 2, ARM64::LD2Twov2s_POST, ARM64::dsub0);
2557 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2558 return SelectPostLoad(Node, 2, ARM64::LD2Twov4s_POST, ARM64::qsub0);
2559 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2560 return SelectPostLoad(Node, 2, ARM64::LD1Twov1d_POST, ARM64::dsub0);
2561 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2562 return SelectPostLoad(Node, 2, ARM64::LD2Twov2d_POST, ARM64::qsub0);
2565 case ARM64ISD::LD3post: {
2566 if (VT == MVT::v8i8)
2567 return SelectPostLoad(Node, 3, ARM64::LD3Threev8b_POST, ARM64::dsub0);
2568 else if (VT == MVT::v16i8)
2569 return SelectPostLoad(Node, 3, ARM64::LD3Threev16b_POST, ARM64::qsub0);
2570 else if (VT == MVT::v4i16)
2571 return SelectPostLoad(Node, 3, ARM64::LD3Threev4h_POST, ARM64::dsub0);
2572 else if (VT == MVT::v8i16)
2573 return SelectPostLoad(Node, 3, ARM64::LD3Threev8h_POST, ARM64::qsub0);
2574 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2575 return SelectPostLoad(Node, 3, ARM64::LD3Threev2s_POST, ARM64::dsub0);
2576 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2577 return SelectPostLoad(Node, 3, ARM64::LD3Threev4s_POST, ARM64::qsub0);
2578 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2579 return SelectPostLoad(Node, 3, ARM64::LD1Threev1d_POST, ARM64::dsub0);
2580 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2581 return SelectPostLoad(Node, 3, ARM64::LD3Threev2d_POST, ARM64::qsub0);
2584 case ARM64ISD::LD4post: {
2585 if (VT == MVT::v8i8)
2586 return SelectPostLoad(Node, 4, ARM64::LD4Fourv8b_POST, ARM64::dsub0);
2587 else if (VT == MVT::v16i8)
2588 return SelectPostLoad(Node, 4, ARM64::LD4Fourv16b_POST, ARM64::qsub0);
2589 else if (VT == MVT::v4i16)
2590 return SelectPostLoad(Node, 4, ARM64::LD4Fourv4h_POST, ARM64::dsub0);
2591 else if (VT == MVT::v8i16)
2592 return SelectPostLoad(Node, 4, ARM64::LD4Fourv8h_POST, ARM64::qsub0);
2593 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2594 return SelectPostLoad(Node, 4, ARM64::LD4Fourv2s_POST, ARM64::dsub0);
2595 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2596 return SelectPostLoad(Node, 4, ARM64::LD4Fourv4s_POST, ARM64::qsub0);
2597 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2598 return SelectPostLoad(Node, 4, ARM64::LD1Fourv1d_POST, ARM64::dsub0);
2599 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2600 return SelectPostLoad(Node, 4, ARM64::LD4Fourv2d_POST, ARM64::qsub0);
2603 case ARM64ISD::LD1x2post: {
2604 if (VT == MVT::v8i8)
2605 return SelectPostLoad(Node, 2, ARM64::LD1Twov8b_POST, ARM64::dsub0);
2606 else if (VT == MVT::v16i8)
2607 return SelectPostLoad(Node, 2, ARM64::LD1Twov16b_POST, ARM64::qsub0);
2608 else if (VT == MVT::v4i16)
2609 return SelectPostLoad(Node, 2, ARM64::LD1Twov4h_POST, ARM64::dsub0);
2610 else if (VT == MVT::v8i16)
2611 return SelectPostLoad(Node, 2, ARM64::LD1Twov8h_POST, ARM64::qsub0);
2612 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2613 return SelectPostLoad(Node, 2, ARM64::LD1Twov2s_POST, ARM64::dsub0);
2614 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2615 return SelectPostLoad(Node, 2, ARM64::LD1Twov4s_POST, ARM64::qsub0);
2616 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2617 return SelectPostLoad(Node, 2, ARM64::LD1Twov1d_POST, ARM64::dsub0);
2618 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2619 return SelectPostLoad(Node, 2, ARM64::LD1Twov2d_POST, ARM64::qsub0);
2622 case ARM64ISD::LD1x3post: {
2623 if (VT == MVT::v8i8)
2624 return SelectPostLoad(Node, 3, ARM64::LD1Threev8b_POST, ARM64::dsub0);
2625 else if (VT == MVT::v16i8)
2626 return SelectPostLoad(Node, 3, ARM64::LD1Threev16b_POST, ARM64::qsub0);
2627 else if (VT == MVT::v4i16)
2628 return SelectPostLoad(Node, 3, ARM64::LD1Threev4h_POST, ARM64::dsub0);
2629 else if (VT == MVT::v8i16)
2630 return SelectPostLoad(Node, 3, ARM64::LD1Threev8h_POST, ARM64::qsub0);
2631 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2632 return SelectPostLoad(Node, 3, ARM64::LD1Threev2s_POST, ARM64::dsub0);
2633 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2634 return SelectPostLoad(Node, 3, ARM64::LD1Threev4s_POST, ARM64::qsub0);
2635 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2636 return SelectPostLoad(Node, 3, ARM64::LD1Threev1d_POST, ARM64::dsub0);
2637 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2638 return SelectPostLoad(Node, 3, ARM64::LD1Threev2d_POST, ARM64::qsub0);
2641 case ARM64ISD::LD1x4post: {
2642 if (VT == MVT::v8i8)
2643 return SelectPostLoad(Node, 4, ARM64::LD1Fourv8b_POST, ARM64::dsub0);
2644 else if (VT == MVT::v16i8)
2645 return SelectPostLoad(Node, 4, ARM64::LD1Fourv16b_POST, ARM64::qsub0);
2646 else if (VT == MVT::v4i16)
2647 return SelectPostLoad(Node, 4, ARM64::LD1Fourv4h_POST, ARM64::dsub0);
2648 else if (VT == MVT::v8i16)
2649 return SelectPostLoad(Node, 4, ARM64::LD1Fourv8h_POST, ARM64::qsub0);
2650 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2651 return SelectPostLoad(Node, 4, ARM64::LD1Fourv2s_POST, ARM64::dsub0);
2652 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2653 return SelectPostLoad(Node, 4, ARM64::LD1Fourv4s_POST, ARM64::qsub0);
2654 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2655 return SelectPostLoad(Node, 4, ARM64::LD1Fourv1d_POST, ARM64::dsub0);
2656 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2657 return SelectPostLoad(Node, 4, ARM64::LD1Fourv2d_POST, ARM64::qsub0);
2660 case ARM64ISD::LD2DUPpost: {
2661 if (VT == MVT::v8i8)
2662 return SelectPostLoad(Node, 2, ARM64::LD2Rv8b_POST, ARM64::dsub0);
2663 else if (VT == MVT::v16i8)
2664 return SelectPostLoad(Node, 2, ARM64::LD2Rv16b_POST, ARM64::qsub0);
2665 else if (VT == MVT::v4i16)
2666 return SelectPostLoad(Node, 2, ARM64::LD2Rv4h_POST, ARM64::dsub0);
2667 else if (VT == MVT::v8i16)
2668 return SelectPostLoad(Node, 2, ARM64::LD2Rv8h_POST, ARM64::qsub0);
2669 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2670 return SelectPostLoad(Node, 2, ARM64::LD2Rv2s_POST, ARM64::dsub0);
2671 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2672 return SelectPostLoad(Node, 2, ARM64::LD2Rv4s_POST, ARM64::qsub0);
2673 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2674 return SelectPostLoad(Node, 2, ARM64::LD2Rv1d_POST, ARM64::dsub0);
2675 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2676 return SelectPostLoad(Node, 2, ARM64::LD2Rv2d_POST, ARM64::qsub0);
2679 case ARM64ISD::LD3DUPpost: {
2680 if (VT == MVT::v8i8)
2681 return SelectPostLoad(Node, 3, ARM64::LD3Rv8b_POST, ARM64::dsub0);
2682 else if (VT == MVT::v16i8)
2683 return SelectPostLoad(Node, 3, ARM64::LD3Rv16b_POST, ARM64::qsub0);
2684 else if (VT == MVT::v4i16)
2685 return SelectPostLoad(Node, 3, ARM64::LD3Rv4h_POST, ARM64::dsub0);
2686 else if (VT == MVT::v8i16)
2687 return SelectPostLoad(Node, 3, ARM64::LD3Rv8h_POST, ARM64::qsub0);
2688 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2689 return SelectPostLoad(Node, 3, ARM64::LD3Rv2s_POST, ARM64::dsub0);
2690 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2691 return SelectPostLoad(Node, 3, ARM64::LD3Rv4s_POST, ARM64::qsub0);
2692 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2693 return SelectPostLoad(Node, 3, ARM64::LD3Rv1d_POST, ARM64::dsub0);
2694 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2695 return SelectPostLoad(Node, 3, ARM64::LD3Rv2d_POST, ARM64::qsub0);
2698 case ARM64ISD::LD4DUPpost: {
2699 if (VT == MVT::v8i8)
2700 return SelectPostLoad(Node, 4, ARM64::LD4Rv8b_POST, ARM64::dsub0);
2701 else if (VT == MVT::v16i8)
2702 return SelectPostLoad(Node, 4, ARM64::LD4Rv16b_POST, ARM64::qsub0);
2703 else if (VT == MVT::v4i16)
2704 return SelectPostLoad(Node, 4, ARM64::LD4Rv4h_POST, ARM64::dsub0);
2705 else if (VT == MVT::v8i16)
2706 return SelectPostLoad(Node, 4, ARM64::LD4Rv8h_POST, ARM64::qsub0);
2707 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2708 return SelectPostLoad(Node, 4, ARM64::LD4Rv2s_POST, ARM64::dsub0);
2709 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2710 return SelectPostLoad(Node, 4, ARM64::LD4Rv4s_POST, ARM64::qsub0);
2711 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2712 return SelectPostLoad(Node, 4, ARM64::LD4Rv1d_POST, ARM64::dsub0);
2713 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2714 return SelectPostLoad(Node, 4, ARM64::LD4Rv2d_POST, ARM64::qsub0);
2717 case ARM64ISD::LD2LANEpost: {
2718 if (VT == MVT::v16i8 || VT == MVT::v8i8)
2719 return SelectPostLoadLane(Node, 2, ARM64::LD2i8_POST);
2720 else if (VT == MVT::v8i16 || VT == MVT::v4i16)
2721 return SelectPostLoadLane(Node, 2, ARM64::LD2i16_POST);
2722 else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
2724 return SelectPostLoadLane(Node, 2, ARM64::LD2i32_POST);
2725 else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
2727 return SelectPostLoadLane(Node, 2, ARM64::LD2i64_POST);
2730 case ARM64ISD::LD3LANEpost: {
2731 if (VT == MVT::v16i8 || VT == MVT::v8i8)
2732 return SelectPostLoadLane(Node, 3, ARM64::LD3i8_POST);
2733 else if (VT == MVT::v8i16 || VT == MVT::v4i16)
2734 return SelectPostLoadLane(Node, 3, ARM64::LD3i16_POST);
2735 else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
2737 return SelectPostLoadLane(Node, 3, ARM64::LD3i32_POST);
2738 else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
2740 return SelectPostLoadLane(Node, 3, ARM64::LD3i64_POST);
2743 case ARM64ISD::LD4LANEpost: {
2744 if (VT == MVT::v16i8 || VT == MVT::v8i8)
2745 return SelectPostLoadLane(Node, 4, ARM64::LD4i8_POST);
2746 else if (VT == MVT::v8i16 || VT == MVT::v4i16)
2747 return SelectPostLoadLane(Node, 4, ARM64::LD4i16_POST);
2748 else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
2750 return SelectPostLoadLane(Node, 4, ARM64::LD4i32_POST);
2751 else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
2753 return SelectPostLoadLane(Node, 4, ARM64::LD4i64_POST);
2756 case ARM64ISD::ST2post: {
2757 VT = Node->getOperand(1).getValueType();
2758 if (VT == MVT::v8i8)
2759 return SelectPostStore(Node, 2, ARM64::ST2Twov8b_POST);
2760 else if (VT == MVT::v16i8)
2761 return SelectPostStore(Node, 2, ARM64::ST2Twov16b_POST);
2762 else if (VT == MVT::v4i16)
2763 return SelectPostStore(Node, 2, ARM64::ST2Twov4h_POST);
2764 else if (VT == MVT::v8i16)
2765 return SelectPostStore(Node, 2, ARM64::ST2Twov8h_POST);
2766 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2767 return SelectPostStore(Node, 2, ARM64::ST2Twov2s_POST);
2768 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2769 return SelectPostStore(Node, 2, ARM64::ST2Twov4s_POST);
2770 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2771 return SelectPostStore(Node, 2, ARM64::ST2Twov2d_POST);
2772 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2773 return SelectPostStore(Node, 2, ARM64::ST1Twov1d_POST);
2776 case ARM64ISD::ST3post: {
2777 VT = Node->getOperand(1).getValueType();
2778 if (VT == MVT::v8i8)
2779 return SelectPostStore(Node, 3, ARM64::ST3Threev8b_POST);
2780 else if (VT == MVT::v16i8)
2781 return SelectPostStore(Node, 3, ARM64::ST3Threev16b_POST);
2782 else if (VT == MVT::v4i16)
2783 return SelectPostStore(Node, 3, ARM64::ST3Threev4h_POST);
2784 else if (VT == MVT::v8i16)
2785 return SelectPostStore(Node, 3, ARM64::ST3Threev8h_POST);
2786 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2787 return SelectPostStore(Node, 3, ARM64::ST3Threev2s_POST);
2788 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2789 return SelectPostStore(Node, 3, ARM64::ST3Threev4s_POST);
2790 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2791 return SelectPostStore(Node, 3, ARM64::ST3Threev2d_POST);
2792 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2793 return SelectPostStore(Node, 3, ARM64::ST1Threev1d_POST);
2796 case ARM64ISD::ST4post: {
2797 VT = Node->getOperand(1).getValueType();
2798 if (VT == MVT::v8i8)
2799 return SelectPostStore(Node, 4, ARM64::ST4Fourv8b_POST);
2800 else if (VT == MVT::v16i8)
2801 return SelectPostStore(Node, 4, ARM64::ST4Fourv16b_POST);
2802 else if (VT == MVT::v4i16)
2803 return SelectPostStore(Node, 4, ARM64::ST4Fourv4h_POST);
2804 else if (VT == MVT::v8i16)
2805 return SelectPostStore(Node, 4, ARM64::ST4Fourv8h_POST);
2806 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2807 return SelectPostStore(Node, 4, ARM64::ST4Fourv2s_POST);
2808 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2809 return SelectPostStore(Node, 4, ARM64::ST4Fourv4s_POST);
2810 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2811 return SelectPostStore(Node, 4, ARM64::ST4Fourv2d_POST);
2812 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2813 return SelectPostStore(Node, 4, ARM64::ST1Fourv1d_POST);
2816 case ARM64ISD::ST1x2post: {
2817 VT = Node->getOperand(1).getValueType();
2818 if (VT == MVT::v8i8)
2819 return SelectPostStore(Node, 2, ARM64::ST1Twov8b_POST);
2820 else if (VT == MVT::v16i8)
2821 return SelectPostStore(Node, 2, ARM64::ST1Twov16b_POST);
2822 else if (VT == MVT::v4i16)
2823 return SelectPostStore(Node, 2, ARM64::ST1Twov4h_POST);
2824 else if (VT == MVT::v8i16)
2825 return SelectPostStore(Node, 2, ARM64::ST1Twov8h_POST);
2826 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2827 return SelectPostStore(Node, 2, ARM64::ST1Twov2s_POST);
2828 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2829 return SelectPostStore(Node, 2, ARM64::ST1Twov4s_POST);
2830 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2831 return SelectPostStore(Node, 2, ARM64::ST1Twov1d_POST);
2832 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2833 return SelectPostStore(Node, 2, ARM64::ST1Twov2d_POST);
2836 case ARM64ISD::ST1x3post: {
2837 VT = Node->getOperand(1).getValueType();
2838 if (VT == MVT::v8i8)
2839 return SelectPostStore(Node, 3, ARM64::ST1Threev8b_POST);
2840 else if (VT == MVT::v16i8)
2841 return SelectPostStore(Node, 3, ARM64::ST1Threev16b_POST);
2842 else if (VT == MVT::v4i16)
2843 return SelectPostStore(Node, 3, ARM64::ST1Threev4h_POST);
2844 else if (VT == MVT::v8i16)
2845 return SelectPostStore(Node, 3, ARM64::ST1Threev8h_POST);
2846 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2847 return SelectPostStore(Node, 3, ARM64::ST1Threev2s_POST);
2848 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2849 return SelectPostStore(Node, 3, ARM64::ST1Threev4s_POST);
2850 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2851 return SelectPostStore(Node, 3, ARM64::ST1Threev1d_POST);
2852 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2853 return SelectPostStore(Node, 3, ARM64::ST1Threev2d_POST);
2856 case ARM64ISD::ST1x4post: {
2857 VT = Node->getOperand(1).getValueType();
2858 if (VT == MVT::v8i8)
2859 return SelectPostStore(Node, 4, ARM64::ST1Fourv8b_POST);
2860 else if (VT == MVT::v16i8)
2861 return SelectPostStore(Node, 4, ARM64::ST1Fourv16b_POST);
2862 else if (VT == MVT::v4i16)
2863 return SelectPostStore(Node, 4, ARM64::ST1Fourv4h_POST);
2864 else if (VT == MVT::v8i16)
2865 return SelectPostStore(Node, 4, ARM64::ST1Fourv8h_POST);
2866 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2867 return SelectPostStore(Node, 4, ARM64::ST1Fourv2s_POST);
2868 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2869 return SelectPostStore(Node, 4, ARM64::ST1Fourv4s_POST);
2870 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2871 return SelectPostStore(Node, 4, ARM64::ST1Fourv1d_POST);
2872 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2873 return SelectPostStore(Node, 4, ARM64::ST1Fourv2d_POST);
2876 case ARM64ISD::ST2LANEpost: {
2877 VT = Node->getOperand(1).getValueType();
2878 if (VT == MVT::v16i8 || VT == MVT::v8i8)
2879 return SelectPostStoreLane(Node, 2, ARM64::ST2i8_POST);
2880 else if (VT == MVT::v8i16 || VT == MVT::v4i16)
2881 return SelectPostStoreLane(Node, 2, ARM64::ST2i16_POST);
2882 else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
2884 return SelectPostStoreLane(Node, 2, ARM64::ST2i32_POST);
2885 else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
2887 return SelectPostStoreLane(Node, 2, ARM64::ST2i64_POST);
2890 case ARM64ISD::ST3LANEpost: {
2891 VT = Node->getOperand(1).getValueType();
2892 if (VT == MVT::v16i8 || VT == MVT::v8i8)
2893 return SelectPostStoreLane(Node, 3, ARM64::ST3i8_POST);
2894 else if (VT == MVT::v8i16 || VT == MVT::v4i16)
2895 return SelectPostStoreLane(Node, 3, ARM64::ST3i16_POST);
2896 else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
2898 return SelectPostStoreLane(Node, 3, ARM64::ST3i32_POST);
2899 else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
2901 return SelectPostStoreLane(Node, 3, ARM64::ST3i64_POST);
2904 case ARM64ISD::ST4LANEpost: {
2905 VT = Node->getOperand(1).getValueType();
2906 if (VT == MVT::v16i8 || VT == MVT::v8i8)
2907 return SelectPostStoreLane(Node, 4, ARM64::ST4i8_POST);
2908 else if (VT == MVT::v8i16 || VT == MVT::v4i16)
2909 return SelectPostStoreLane(Node, 4, ARM64::ST4i16_POST);
2910 else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
2912 return SelectPostStoreLane(Node, 4, ARM64::ST4i32_POST);
2913 else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
2915 return SelectPostStoreLane(Node, 4, ARM64::ST4i64_POST);
2923 if (SDNode *I = SelectLIBM(Node))
2928 // Select the default instruction
2929 ResNode = SelectCode(Node);
2931 DEBUG(errs() << "=> ");
2932 if (ResNode == nullptr || ResNode == Node)
2933 DEBUG(Node->dump(CurDAG));
2935 DEBUG(ResNode->dump(CurDAG));
2936 DEBUG(errs() << "\n");
2941 /// createARM64ISelDag - This pass converts a legalized DAG into a
2942 /// ARM64-specific DAG, ready for instruction scheduling.
2943 FunctionPass *llvm::createARM64ISelDag(ARM64TargetMachine &TM,
2944 CodeGenOpt::Level OptLevel) {
2945 return new ARM64DAGToDAGISel(TM, OptLevel);