1 //===- ThumbRegisterInfo.h - Thumb Register Information Impl ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef THUMBREGISTERINFO_H
15 #define THUMBREGISTERINFO_H
18 #include "ARMRegisterInfo.h"
19 #include "llvm/Target/TargetRegisterInfo.h"
23 class TargetInstrInfo;
26 struct ThumbRegisterInfo : public ARMBaseRegisterInfo {
28 ThumbRegisterInfo(const TargetInstrInfo &tii, const ARMSubtarget &STI);
30 /// emitLoadConstPool - Emits a load from constpool to materialize the
31 /// specified immediate.
32 void emitLoadConstPool(MachineBasicBlock &MBB,
33 MachineBasicBlock::iterator &MBBI,
34 unsigned DestReg, int Val,
35 unsigned Pred, unsigned PredReg,
36 const TargetInstrInfo *TII,
39 /// Code Generation virtual methods...
40 const TargetRegisterClass *
41 getPhysicalRegisterRegClass(unsigned Reg, MVT VT = MVT::Other) const;
43 bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;
45 bool requiresRegisterScavenging(const MachineFunction &MF) const;
47 bool hasReservedCallFrame(MachineFunction &MF) const;
49 void eliminateCallFramePseudoInstr(MachineFunction &MF,
50 MachineBasicBlock &MBB,
51 MachineBasicBlock::iterator I) const;
53 void eliminateFrameIndex(MachineBasicBlock::iterator II,
54 int SPAdj, RegScavenger *RS = NULL) const;
56 void emitPrologue(MachineFunction &MF) const;
57 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
59 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
60 int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg,
61 const TargetInstrInfo &TII, DebugLoc dl) const;
65 #endif // THUMBREGISTERINFO_H