1 //===- Thumb2InstrInfo.cpp - Thumb-2 Instruction Information --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb-2 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMInstrInfo.h"
16 #include "ARMGenInstrInfo.inc"
17 #include "ARMMachineFunctionInfo.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "Thumb2InstrInfo.h"
25 Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI)
26 : ARMBaseInstrInfo(STI), RI(*this, STI) {
29 unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const {
34 unsigned Thumb2InstrInfo::getOpcode(ARMII::Op Op) const {
36 case ARMII::ADDri: return ARM::t2ADDri;
37 case ARMII::ADDrs: return ARM::t2ADDrs;
38 case ARMII::ADDrr: return ARM::t2ADDrr;
39 case ARMII::LDRri: return ARM::t2LDRi12;
40 case ARMII::MOVr: return ARM::t2MOVr;
41 case ARMII::STRri: return ARM::t2STRi12;
42 case ARMII::SUBri: return ARM::t2SUBri;
43 case ARMII::SUBrs: return ARM::t2SUBrs;
44 case ARMII::SUBrr: return ARM::t2SUBrr;
53 Thumb2InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
54 if (MBB.empty()) return false;
56 switch (MBB.back().getOpcode()) {
58 case ARM::t2B: // Uncond branch.
59 case ARM::t2BR_JT: // Jumptable branch.
60 case ARM::tBR_JTr: // Jumptable branch (16-bit version).
62 case ARM::tBX_RET_vararg:
74 Thumb2InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
75 MachineBasicBlock::iterator I,
76 unsigned DestReg, unsigned SrcReg,
77 const TargetRegisterClass *DestRC,
78 const TargetRegisterClass *SrcRC) const {
79 DebugLoc DL = DebugLoc::getUnknownLoc();
80 if (I != MBB.end()) DL = I->getDebugLoc();
82 if (DestRC == ARM::GPRRegisterClass &&
83 SrcRC == ARM::GPRRegisterClass) {
84 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2MOVr),
85 DestReg).addReg(SrcReg)));
87 } else if (DestRC == ARM::GPRRegisterClass &&
88 SrcRC == ARM::tGPRRegisterClass) {
89 BuildMI(MBB, I, DL, get(ARM::tMOVtgpr2gpr), DestReg).addReg(SrcReg);
91 } else if (DestRC == ARM::tGPRRegisterClass &&
92 SrcRC == ARM::GPRRegisterClass) {
93 BuildMI(MBB, I, DL, get(ARM::tMOVgpr2tgpr), DestReg).addReg(SrcReg);
97 // Handle SPR, DPR, and QPR copies.
98 return ARMBaseInstrInfo::copyRegToReg(MBB, I, DestReg, SrcReg, DestRC, SrcRC);
101 void Thumb2InstrInfo::
102 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
103 unsigned SrcReg, bool isKill, int FI,
104 const TargetRegisterClass *RC) const {
105 DebugLoc DL = DebugLoc::getUnknownLoc();
106 if (I != MBB.end()) DL = I->getDebugLoc();
108 if (RC == ARM::GPRRegisterClass) {
109 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2STRi12))
110 .addReg(SrcReg, getKillRegState(isKill))
111 .addFrameIndex(FI).addImm(0));
115 ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC);
118 void Thumb2InstrInfo::
119 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
120 unsigned DestReg, int FI,
121 const TargetRegisterClass *RC) const {
122 DebugLoc DL = DebugLoc::getUnknownLoc();
123 if (I != MBB.end()) DL = I->getDebugLoc();
125 if (RC == ARM::GPRRegisterClass) {
126 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)
127 .addFrameIndex(FI).addImm(0));
131 ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC);