1 //===- Thumb2InstrInfo.cpp - Thumb-2 Instruction Information ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb-2 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "Thumb2InstrInfo.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMAddressingModes.h"
18 #include "ARMGenInstrInfo.inc"
19 #include "ARMMachineFunctionInfo.h"
20 #include "Thumb2HazardRecognizer.h"
21 #include "Thumb2InstrInfo.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineMemOperand.h"
25 #include "llvm/CodeGen/PseudoSourceValue.h"
26 #include "llvm/ADT/SmallVector.h"
30 Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI)
31 : ARMBaseInstrInfo(STI), RI(*this, STI) {
34 unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const {
40 Thumb2InstrInfo::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
41 MachineBasicBlock *NewDest) const {
42 MachineBasicBlock *MBB = Tail->getParent();
43 ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
44 if (!AFI->hasITBlocks()) {
45 TargetInstrInfoImpl::ReplaceTailWithBranchTo(Tail, NewDest);
49 // If the first instruction of Tail is predicated, we may have to update
50 // the IT instruction.
52 ARMCC::CondCodes CC = llvm::getInstrPredicate(Tail, PredReg);
53 MachineBasicBlock::iterator MBBI = Tail;
55 // Expecting at least the t2IT instruction before it.
58 // Actually replace the tail.
59 TargetInstrInfoImpl::ReplaceTailWithBranchTo(Tail, NewDest);
62 if (CC != ARMCC::AL) {
63 MachineBasicBlock::iterator E = MBB->begin();
64 unsigned Count = 4; // At most 4 instructions in an IT block.
65 while (Count && MBBI != E) {
66 if (MBBI->isDebugValue()) {
70 if (MBBI->getOpcode() == ARM::t2IT) {
71 unsigned Mask = MBBI->getOperand(1).getImm();
73 MBBI->eraseFromParent();
75 unsigned MaskOn = 1 << Count;
76 unsigned MaskOff = ~(MaskOn - 1);
77 MBBI->getOperand(1).setImm((Mask & MaskOff) | MaskOn);
85 // Ctrl flow can reach here if branch folding is run before IT block
91 Thumb2InstrInfo::isLegalToSplitMBBAt(MachineBasicBlock &MBB,
92 MachineBasicBlock::iterator MBBI) const {
94 return llvm::getITInstrPredicate(MBBI, PredReg) == ARMCC::AL;
99 Thumb2InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
100 MachineBasicBlock::iterator I,
101 unsigned DestReg, unsigned SrcReg,
102 const TargetRegisterClass *DestRC,
103 const TargetRegisterClass *SrcRC,
105 if (DestRC == ARM::GPRRegisterClass || DestRC == ARM::tcGPRRegisterClass) {
106 if (SrcRC == ARM::GPRRegisterClass || SrcRC == ARM::tcGPRRegisterClass) {
107 BuildMI(MBB, I, DL, get(ARM::tMOVgpr2gpr), DestReg).addReg(SrcReg);
109 } else if (SrcRC == ARM::tGPRRegisterClass) {
110 BuildMI(MBB, I, DL, get(ARM::tMOVtgpr2gpr), DestReg).addReg(SrcReg);
113 } else if (DestRC == ARM::tGPRRegisterClass) {
114 if (SrcRC == ARM::GPRRegisterClass || SrcRC == ARM::tcGPRRegisterClass) {
115 BuildMI(MBB, I, DL, get(ARM::tMOVgpr2tgpr), DestReg).addReg(SrcReg);
117 } else if (SrcRC == ARM::tGPRRegisterClass) {
118 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg).addReg(SrcReg);
123 // Handle SPR, DPR, and QPR copies.
124 return ARMBaseInstrInfo::copyRegToReg(MBB, I, DestReg, SrcReg, DestRC,
128 void Thumb2InstrInfo::
129 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
130 unsigned SrcReg, bool isKill, int FI,
131 const TargetRegisterClass *RC,
132 const TargetRegisterInfo *TRI) const {
133 if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass ||
134 RC == ARM::tcGPRRegisterClass) {
136 if (I != MBB.end()) DL = I->getDebugLoc();
138 MachineFunction &MF = *MBB.getParent();
139 MachineFrameInfo &MFI = *MF.getFrameInfo();
140 MachineMemOperand *MMO =
141 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
142 MachineMemOperand::MOStore, 0,
143 MFI.getObjectSize(FI),
144 MFI.getObjectAlignment(FI));
145 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2STRi12))
146 .addReg(SrcReg, getKillRegState(isKill))
147 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
151 ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC, TRI);
154 void Thumb2InstrInfo::
155 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
156 unsigned DestReg, int FI,
157 const TargetRegisterClass *RC,
158 const TargetRegisterInfo *TRI) const {
159 if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass ||
160 RC == ARM::tcGPRRegisterClass) {
162 if (I != MBB.end()) DL = I->getDebugLoc();
164 MachineFunction &MF = *MBB.getParent();
165 MachineFrameInfo &MFI = *MF.getFrameInfo();
166 MachineMemOperand *MMO =
167 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
168 MachineMemOperand::MOLoad, 0,
169 MFI.getObjectSize(FI),
170 MFI.getObjectAlignment(FI));
171 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)
172 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
176 ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC, TRI);
179 ScheduleHazardRecognizer *Thumb2InstrInfo::
180 CreateTargetPostRAHazardRecognizer(const InstrItineraryData &II) const {
181 return (ScheduleHazardRecognizer *)new Thumb2HazardRecognizer(II);
184 void llvm::emitT2RegPlusImmediate(MachineBasicBlock &MBB,
185 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
186 unsigned DestReg, unsigned BaseReg, int NumBytes,
187 ARMCC::CondCodes Pred, unsigned PredReg,
188 const ARMBaseInstrInfo &TII) {
189 bool isSub = NumBytes < 0;
190 if (isSub) NumBytes = -NumBytes;
192 // If profitable, use a movw or movt to materialize the offset.
193 // FIXME: Use the scavenger to grab a scratch register.
194 if (DestReg != ARM::SP && DestReg != BaseReg &&
196 ARM_AM::getT2SOImmVal(NumBytes) == -1) {
198 if (NumBytes < 65536) {
199 // Use a movw to materialize the 16-bit constant.
200 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg)
202 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
204 } else if ((NumBytes & 0xffff) == 0) {
205 // Use a movt to materialize the 32-bit constant.
206 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg)
208 .addImm(NumBytes >> 16)
209 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
215 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg)
216 .addReg(BaseReg, RegState::Kill)
217 .addReg(DestReg, RegState::Kill)
218 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
220 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg)
221 .addReg(DestReg, RegState::Kill)
222 .addReg(BaseReg, RegState::Kill)
223 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
230 unsigned ThisVal = NumBytes;
232 if (DestReg == ARM::SP && BaseReg != ARM::SP) {
233 // mov sp, rn. Note t2MOVr cannot be used.
234 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr),DestReg).addReg(BaseReg);
239 bool HasCCOut = true;
240 if (BaseReg == ARM::SP) {
242 if (DestReg == ARM::SP && (ThisVal < ((1 << 7)-1) * 4)) {
243 assert((ThisVal & 3) == 0 && "Stack update is not multiple of 4?");
244 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
245 // FIXME: Fix Thumb1 immediate encoding.
246 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
247 .addReg(BaseReg).addImm(ThisVal/4);
252 // sub rd, sp, so_imm
253 Opc = isSub ? ARM::t2SUBrSPi : ARM::t2ADDrSPi;
254 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
257 // FIXME: Move this to ARMAddressingModes.h?
258 unsigned RotAmt = CountLeadingZeros_32(ThisVal);
259 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
260 NumBytes &= ~ThisVal;
261 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
262 "Bit extraction didn't work?");
265 assert(DestReg != ARM::SP && BaseReg != ARM::SP);
266 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
267 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
269 } else if (ThisVal < 4096) {
270 Opc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
274 // FIXME: Move this to ARMAddressingModes.h?
275 unsigned RotAmt = CountLeadingZeros_32(ThisVal);
276 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
277 NumBytes &= ~ThisVal;
278 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
279 "Bit extraction didn't work?");
283 // Build the new ADD / SUB.
284 MachineInstrBuilder MIB =
285 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
286 .addReg(BaseReg, RegState::Kill)
296 negativeOffsetOpcode(unsigned opcode)
299 case ARM::t2LDRi12: return ARM::t2LDRi8;
300 case ARM::t2LDRHi12: return ARM::t2LDRHi8;
301 case ARM::t2LDRBi12: return ARM::t2LDRBi8;
302 case ARM::t2LDRSHi12: return ARM::t2LDRSHi8;
303 case ARM::t2LDRSBi12: return ARM::t2LDRSBi8;
304 case ARM::t2STRi12: return ARM::t2STRi8;
305 case ARM::t2STRBi12: return ARM::t2STRBi8;
306 case ARM::t2STRHi12: return ARM::t2STRHi8;
326 positiveOffsetOpcode(unsigned opcode)
329 case ARM::t2LDRi8: return ARM::t2LDRi12;
330 case ARM::t2LDRHi8: return ARM::t2LDRHi12;
331 case ARM::t2LDRBi8: return ARM::t2LDRBi12;
332 case ARM::t2LDRSHi8: return ARM::t2LDRSHi12;
333 case ARM::t2LDRSBi8: return ARM::t2LDRSBi12;
334 case ARM::t2STRi8: return ARM::t2STRi12;
335 case ARM::t2STRBi8: return ARM::t2STRBi12;
336 case ARM::t2STRHi8: return ARM::t2STRHi12;
341 case ARM::t2LDRSHi12:
342 case ARM::t2LDRSBi12:
356 immediateOffsetOpcode(unsigned opcode)
359 case ARM::t2LDRs: return ARM::t2LDRi12;
360 case ARM::t2LDRHs: return ARM::t2LDRHi12;
361 case ARM::t2LDRBs: return ARM::t2LDRBi12;
362 case ARM::t2LDRSHs: return ARM::t2LDRSHi12;
363 case ARM::t2LDRSBs: return ARM::t2LDRSBi12;
364 case ARM::t2STRs: return ARM::t2STRi12;
365 case ARM::t2STRBs: return ARM::t2STRBi12;
366 case ARM::t2STRHs: return ARM::t2STRHi12;
371 case ARM::t2LDRSHi12:
372 case ARM::t2LDRSBi12:
393 bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
394 unsigned FrameReg, int &Offset,
395 const ARMBaseInstrInfo &TII) {
396 unsigned Opcode = MI.getOpcode();
397 const TargetInstrDesc &Desc = MI.getDesc();
398 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
401 // Memory operands in inline assembly always use AddrModeT2_i12.
402 if (Opcode == ARM::INLINEASM)
403 AddrMode = ARMII::AddrModeT2_i12; // FIXME. mode for thumb2?
405 if (Opcode == ARM::t2ADDri || Opcode == ARM::t2ADDri12) {
406 Offset += MI.getOperand(FrameRegIdx+1).getImm();
409 if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
410 // Turn it into a move.
411 MI.setDesc(TII.get(ARM::tMOVgpr2gpr));
412 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
413 // Remove offset and remaining explicit predicate operands.
414 do MI.RemoveOperand(FrameRegIdx+1);
415 while (MI.getNumOperands() > FrameRegIdx+1 &&
416 (!MI.getOperand(FrameRegIdx+1).isReg() ||
417 !MI.getOperand(FrameRegIdx+1).isImm()));
421 bool isSP = FrameReg == ARM::SP;
422 bool HasCCOut = Opcode != ARM::t2ADDri12;
427 MI.setDesc(TII.get(isSP ? ARM::t2SUBrSPi : ARM::t2SUBri));
429 MI.setDesc(TII.get(isSP ? ARM::t2ADDrSPi : ARM::t2ADDri));
432 // Common case: small offset, fits into instruction.
433 if (ARM_AM::getT2SOImmVal(Offset) != -1) {
434 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
435 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
436 // Add cc_out operand if the original instruction did not have one.
438 MI.addOperand(MachineOperand::CreateReg(0, false));
442 // Another common case: imm12.
444 (!HasCCOut || MI.getOperand(MI.getNumOperands()-1).getReg() == 0)) {
445 unsigned NewOpc = isSP
446 ? (isSub ? ARM::t2SUBrSPi12 : ARM::t2ADDrSPi12)
447 : (isSub ? ARM::t2SUBri12 : ARM::t2ADDri12);
448 MI.setDesc(TII.get(NewOpc));
449 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
450 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
451 // Remove the cc_out operand.
453 MI.RemoveOperand(MI.getNumOperands()-1);
458 // Otherwise, extract 8 adjacent bits from the immediate into this
460 unsigned RotAmt = CountLeadingZeros_32(Offset);
461 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xff000000U, RotAmt);
463 // We will handle these bits from offset, clear them.
464 Offset &= ~ThisImmVal;
466 assert(ARM_AM::getT2SOImmVal(ThisImmVal) != -1 &&
467 "Bit extraction didn't work?");
468 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
469 // Add cc_out operand if the original instruction did not have one.
471 MI.addOperand(MachineOperand::CreateReg(0, false));
475 // AddrMode4 and AddrMode6 cannot handle any offset.
476 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
479 // AddrModeT2_so cannot handle any offset. If there is no offset
480 // register then we change to an immediate version.
481 unsigned NewOpc = Opcode;
482 if (AddrMode == ARMII::AddrModeT2_so) {
483 unsigned OffsetReg = MI.getOperand(FrameRegIdx+1).getReg();
484 if (OffsetReg != 0) {
485 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
489 MI.RemoveOperand(FrameRegIdx+1);
490 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(0);
491 NewOpc = immediateOffsetOpcode(Opcode);
492 AddrMode = ARMII::AddrModeT2_i12;
495 unsigned NumBits = 0;
497 if (AddrMode == ARMII::AddrModeT2_i8 || AddrMode == ARMII::AddrModeT2_i12) {
498 // i8 supports only negative, and i12 supports only positive, so
499 // based on Offset sign convert Opcode to the appropriate
501 Offset += MI.getOperand(FrameRegIdx+1).getImm();
503 NewOpc = negativeOffsetOpcode(Opcode);
508 NewOpc = positiveOffsetOpcode(Opcode);
511 } else if (AddrMode == ARMII::AddrMode5) {
513 const MachineOperand &OffOp = MI.getOperand(FrameRegIdx+1);
514 int InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
515 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
519 Offset += InstrOffs * 4;
520 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
526 llvm_unreachable("Unsupported addressing mode!");
529 if (NewOpc != Opcode)
530 MI.setDesc(TII.get(NewOpc));
532 MachineOperand &ImmOp = MI.getOperand(FrameRegIdx+1);
534 // Attempt to fold address computation
535 // Common case: small offset, fits into instruction.
536 int ImmedOffset = Offset / Scale;
537 unsigned Mask = (1 << NumBits) - 1;
538 if ((unsigned)Offset <= Mask * Scale) {
539 // Replace the FrameIndex with fp/sp
540 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
542 if (AddrMode == ARMII::AddrMode5)
543 // FIXME: Not consistent.
544 ImmedOffset |= 1 << NumBits;
546 ImmedOffset = -ImmedOffset;
548 ImmOp.ChangeToImmediate(ImmedOffset);
553 // Otherwise, offset doesn't fit. Pull in what we can to simplify
554 ImmedOffset = ImmedOffset & Mask;
556 if (AddrMode == ARMII::AddrMode5)
557 // FIXME: Not consistent.
558 ImmedOffset |= 1 << NumBits;
560 ImmedOffset = -ImmedOffset;
561 if (ImmedOffset == 0)
562 // Change the opcode back if the encoded offset is zero.
563 MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc)));
566 ImmOp.ChangeToImmediate(ImmedOffset);
567 Offset &= ~(Mask*Scale);
570 Offset = (isSub) ? -Offset : Offset;
574 /// scheduleTwoAddrSource - Schedule the copy / re-mat of the source of the
575 /// two-addrss instruction inserted by two-address pass.
577 Thumb2InstrInfo::scheduleTwoAddrSource(MachineInstr *SrcMI,
579 const TargetRegisterInfo &TRI) const {
580 if (SrcMI->getOpcode() != ARM::tMOVgpr2gpr ||
581 SrcMI->getOperand(1).isKill())
584 unsigned PredReg = 0;
585 ARMCC::CondCodes CC = llvm::getInstrPredicate(UseMI, PredReg);
586 if (CC == ARMCC::AL || PredReg != ARM::CPSR)
589 // Schedule the copy so it doesn't come between previous instructions
590 // and UseMI which can form an IT block.
591 unsigned SrcReg = SrcMI->getOperand(1).getReg();
592 ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC);
593 MachineBasicBlock *MBB = UseMI->getParent();
594 MachineBasicBlock::iterator MBBI = SrcMI;
595 unsigned NumInsts = 0;
596 while (--MBBI != MBB->begin()) {
597 if (MBBI->isDebugValue())
600 MachineInstr *NMI = &*MBBI;
601 ARMCC::CondCodes NCC = llvm::getInstrPredicate(NMI, PredReg);
602 if (!(NCC == CC || NCC == OCC) ||
603 NMI->modifiesRegister(SrcReg, &TRI) ||
604 NMI->definesRegister(ARM::CPSR))
607 // Too many in a row!
613 MBB->insert(++MBBI, SrcMI);
618 llvm::getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
619 unsigned Opc = MI->getOpcode();
620 if (Opc == ARM::tBcc || Opc == ARM::t2Bcc)
622 return llvm::getInstrPredicate(MI, PredReg);