1 //===- Thumb1RegisterInfo.cpp - Thumb-1 Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb-1 implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "ARMAddressingModes.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMMachineFunctionInfo.h"
18 #include "ARMSubtarget.h"
19 #include "Thumb1InstrInfo.h"
20 #include "Thumb1RegisterInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/Function.h"
24 #include "llvm/LLVMContext.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineLocation.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/Target/TargetFrameInfo.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/ADT/BitVector.h"
34 #include "llvm/ADT/SmallVector.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
41 ThumbRegScavenging("enable-thumb-reg-scavenging",
43 cl::desc("Enable register scavenging on Thumb"));
45 Thumb1RegisterInfo::Thumb1RegisterInfo(const ARMBaseInstrInfo &tii,
46 const ARMSubtarget &sti)
47 : ARMBaseRegisterInfo(tii, sti) {
50 /// emitLoadConstPool - Emits a load from constpool to materialize the
51 /// specified immediate.
52 void Thumb1RegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
53 MachineBasicBlock::iterator &MBBI,
55 unsigned DestReg, unsigned SubIdx,
57 ARMCC::CondCodes Pred,
58 unsigned PredReg) const {
59 MachineFunction &MF = *MBB.getParent();
60 MachineConstantPool *ConstantPool = MF.getConstantPool();
62 MF.getFunction()->getContext()->getConstantInt(Type::Int32Ty, Val);
63 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
65 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRcp))
66 .addReg(DestReg, getDefRegState(true), SubIdx)
67 .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg);
70 const TargetRegisterClass*
71 Thumb1RegisterInfo::getPhysicalRegisterRegClass(unsigned Reg, MVT VT) const {
72 if (isARMLowRegister(Reg))
73 return ARM::tGPRRegisterClass;
77 case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11:
78 case ARM::R12: case ARM::SP: case ARM::LR: case ARM::PC:
79 return ARM::GPRRegisterClass;
82 return TargetRegisterInfo::getPhysicalRegisterRegClass(Reg, VT);
86 Thumb1RegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
87 return ThumbRegScavenging;
90 bool Thumb1RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
91 const MachineFrameInfo *FFI = MF.getFrameInfo();
92 unsigned CFSize = FFI->getMaxCallFrameSize();
93 // It's not always a good idea to include the call frame as part of the
94 // stack frame. ARM (especially Thumb) has small immediate offset to
95 // address the stack frame. So a large call frame can cause poor codegen
96 // and may even makes it impossible to scavenge a register.
97 if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4
100 return !MF.getFrameInfo()->hasVarSizedObjects();
104 /// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize
105 /// a destreg = basereg + immediate in Thumb code. Materialize the immediate
106 /// in a register using mov / mvn sequences or load the immediate from a
109 void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
110 MachineBasicBlock::iterator &MBBI,
111 unsigned DestReg, unsigned BaseReg,
112 int NumBytes, bool CanChangeCC,
113 const TargetInstrInfo &TII,
114 const Thumb1RegisterInfo& MRI,
116 bool isHigh = !isARMLowRegister(DestReg) ||
117 (BaseReg != 0 && !isARMLowRegister(BaseReg));
119 // Subtract doesn't have high register version. Load the negative value
120 // if either base or dest register is a high register. Also, if do not
121 // issue sub as part of the sequence if condition register is to be
123 if (NumBytes < 0 && !isHigh && CanChangeCC) {
125 NumBytes = -NumBytes;
127 unsigned LdReg = DestReg;
128 if (DestReg == ARM::SP) {
129 assert(BaseReg == ARM::SP && "Unexpected!");
131 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVlor2hir), ARM::R12)
132 .addReg(ARM::R3, RegState::Kill);
135 if (NumBytes <= 255 && NumBytes >= 0)
136 AddDefaultCC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
138 else if (NumBytes < 0 && NumBytes >= -255) {
139 AddDefaultCC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
141 AddDefaultCC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tRSB), LdReg))
142 .addReg(LdReg, RegState::Kill);
144 MRI.emitLoadConstPool(MBB, MBBI, dl, LdReg, 0, NumBytes);
147 int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
148 MachineInstrBuilder MIB =
149 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
150 if (Opc != ARM::tADDhirr)
151 MIB = AddDefaultCC(MIB);
152 if (DestReg == ARM::SP || isSub)
153 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
155 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
158 if (DestReg == ARM::SP)
159 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVhir2lor), ARM::R3)
160 .addReg(ARM::R12, RegState::Kill);
163 /// calcNumMI - Returns the number of instructions required to materialize
164 /// the specific add / sub r, c instruction.
165 static unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes,
166 unsigned NumBits, unsigned Scale) {
168 unsigned Chunk = ((1 << NumBits) - 1) * Scale;
170 if (Opc == ARM::tADDrSPi) {
171 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
175 Scale = 1; // Followed by a number of tADDi8.
176 Chunk = ((1 << NumBits) - 1) * Scale;
179 NumMIs += Bytes / Chunk;
180 if ((Bytes % Chunk) != 0)
187 /// emitThumbRegPlusImmediate - Emits a series of instructions to materialize
188 /// a destreg = basereg + immediate in Thumb code.
190 void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
191 MachineBasicBlock::iterator &MBBI,
192 unsigned DestReg, unsigned BaseReg,
193 int NumBytes, const TargetInstrInfo &TII,
194 const Thumb1RegisterInfo& MRI,
196 bool isSub = NumBytes < 0;
197 unsigned Bytes = (unsigned)NumBytes;
198 if (isSub) Bytes = -NumBytes;
199 bool isMul4 = (Bytes & 3) == 0;
200 bool isTwoAddr = false;
201 bool DstNotEqBase = false;
202 unsigned NumBits = 1;
207 bool NeedPred = false;
209 if (DestReg == BaseReg && BaseReg == ARM::SP) {
210 assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
213 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
215 } else if (!isSub && BaseReg == ARM::SP) {
218 // r1 = add sp, 100 * 4
222 ExtraOpc = ARM::tADDi3;
231 if (DestReg != BaseReg)
234 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
235 NeedPred = NeedCC = true;
239 unsigned NumMIs = calcNumMI(Opc, ExtraOpc, Bytes, NumBits, Scale);
240 unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2;
241 if (NumMIs > Threshold) {
242 // This will expand into too many instructions. Load the immediate from a
244 emitThumbRegPlusImmInReg(MBB, MBBI, DestReg, BaseReg, NumBytes, true, TII,
250 if (isARMLowRegister(DestReg) && isARMLowRegister(BaseReg)) {
251 // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7)
252 unsigned Chunk = (1 << 3) - 1;
253 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
255 const TargetInstrDesc &TID = TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3);
256 const MachineInstrBuilder MIB =
257 AddDefaultCC(BuildMI(MBB, MBBI, dl, TID, DestReg));
258 AddDefaultPred(MIB.addReg(BaseReg, RegState::Kill).addImm(ThisVal));
260 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
261 .addReg(BaseReg, RegState::Kill);
266 unsigned Chunk = ((1 << NumBits) - 1) * Scale;
268 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
271 // Build the new tADD / tSUB.
273 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
275 MIB = AddDefaultCC(MIB);
276 MIB .addReg(DestReg).addImm(ThisVal);
278 MIB = AddDefaultPred(MIB);
281 bool isKill = BaseReg != ARM::SP;
282 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
284 MIB = AddDefaultCC(MIB);
285 MIB.addReg(BaseReg, getKillRegState(isKill)).addImm(ThisVal);
287 MIB = AddDefaultPred(MIB);
290 if (Opc == ARM::tADDrSPi) {
296 Chunk = ((1 << NumBits) - 1) * Scale;
297 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
298 NeedPred = NeedCC = isTwoAddr = true;
304 const TargetInstrDesc &TID = TII.get(ExtraOpc);
305 AddDefaultPred(AddDefaultCC(BuildMI(MBB, MBBI, dl, TID, DestReg))
306 .addReg(DestReg, RegState::Kill)
307 .addImm(((unsigned)NumBytes) & 3));
311 static void emitSPUpdate(MachineBasicBlock &MBB,
312 MachineBasicBlock::iterator &MBBI,
313 const TargetInstrInfo &TII, DebugLoc dl,
314 const Thumb1RegisterInfo &MRI,
316 emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII,
320 void Thumb1RegisterInfo::
321 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
322 MachineBasicBlock::iterator I) const {
323 if (!hasReservedCallFrame(MF)) {
324 // If we have alloca, convert as follows:
325 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
326 // ADJCALLSTACKUP -> add, sp, sp, amount
327 MachineInstr *Old = I;
328 DebugLoc dl = Old->getDebugLoc();
329 unsigned Amount = Old->getOperand(0).getImm();
331 // We need to keep the stack aligned properly. To do this, we round the
332 // amount of space needed for the outgoing arguments up to the next
333 // alignment boundary.
334 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
335 Amount = (Amount+Align-1)/Align*Align;
337 // Replace the pseudo instruction with a new instruction...
338 unsigned Opc = Old->getOpcode();
339 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
340 emitSPUpdate(MBB, I, TII, dl, *this, -Amount);
342 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
343 emitSPUpdate(MBB, I, TII, dl, *this, Amount);
350 /// emitThumbConstant - Emit a series of instructions to materialize a
352 static void emitThumbConstant(MachineBasicBlock &MBB,
353 MachineBasicBlock::iterator &MBBI,
354 unsigned DestReg, int Imm,
355 const TargetInstrInfo &TII,
356 const Thumb1RegisterInfo& MRI,
358 bool isSub = Imm < 0;
359 if (isSub) Imm = -Imm;
361 int Chunk = (1 << 8) - 1;
362 int ThisVal = (Imm > Chunk) ? Chunk : Imm;
364 AddDefaultPred(AddDefaultCC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8),
368 emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII, MRI, dl);
370 const TargetInstrDesc &TID = TII.get(ARM::tRSB);
371 AddDefaultPred(AddDefaultCC(BuildMI(MBB, MBBI, dl, TID, DestReg))
372 .addReg(DestReg, RegState::Kill));
376 static void removeOperands(MachineInstr &MI, unsigned i) {
378 for (unsigned e = MI.getNumOperands(); i != e; ++i)
379 MI.RemoveOperand(Op);
382 void Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
383 int SPAdj, RegScavenger *RS) const{
385 MachineInstr &MI = *II;
386 MachineBasicBlock &MBB = *MI.getParent();
387 MachineFunction &MF = *MBB.getParent();
388 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
389 DebugLoc dl = MI.getDebugLoc();
391 while (!MI.getOperand(i).isFI()) {
393 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
396 unsigned FrameReg = ARM::SP;
397 int FrameIndex = MI.getOperand(i).getIndex();
398 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
399 MF.getFrameInfo()->getStackSize() + SPAdj;
401 if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex))
402 Offset -= AFI->getGPRCalleeSavedArea1Offset();
403 else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex))
404 Offset -= AFI->getGPRCalleeSavedArea2Offset();
405 else if (hasFP(MF)) {
406 assert(SPAdj == 0 && "Unexpected");
407 // There is alloca()'s in this function, must reference off the frame
409 FrameReg = getFrameRegister(MF);
410 Offset -= AFI->getFramePtrSpillOffset();
413 unsigned Opcode = MI.getOpcode();
414 const TargetInstrDesc &Desc = MI.getDesc();
415 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
417 if (Opcode == ARM::tADDrSPi) {
418 Offset += MI.getOperand(i+1).getImm();
420 // Can't use tADDrSPi if it's based off the frame pointer.
421 unsigned NumBits = 0;
423 if (FrameReg != ARM::SP) {
424 Opcode = ARM::tADDi3;
425 MI.setDesc(TII.get(Opcode));
430 assert((Offset & 3) == 0 &&
431 "Thumb add/sub sp, #imm immediate must be multiple of 4!");
435 // Turn it into a move.
436 MI.setDesc(TII.get(ARM::tMOVhir2lor));
437 MI.getOperand(i).ChangeToRegister(FrameReg, false);
438 MI.RemoveOperand(i+1);
442 // Common case: small offset, fits into instruction.
443 unsigned Mask = (1 << NumBits) - 1;
444 if (((Offset / Scale) & ~Mask) == 0) {
445 // Replace the FrameIndex with sp / fp
446 if (Opcode == ARM::tADDi3) {
447 removeOperands(MI, i);
448 MachineInstrBuilder MIB(&MI);
449 AddDefaultPred(AddDefaultCC(MIB).addReg(FrameReg).addImm(Offset/Scale));
451 MI.getOperand(i).ChangeToRegister(FrameReg, false);
452 MI.getOperand(i+1).ChangeToImmediate(Offset / Scale);
457 unsigned DestReg = MI.getOperand(0).getReg();
458 unsigned Bytes = (Offset > 0) ? Offset : -Offset;
459 unsigned NumMIs = calcNumMI(Opcode, 0, Bytes, NumBits, Scale);
460 // MI would expand into a large number of instructions. Don't try to
461 // simplify the immediate.
463 emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII,
470 // Translate r0 = add sp, imm to
471 // r0 = add sp, 255*4
472 // r0 = add r0, (imm - 255*4)
473 if (Opcode == ARM::tADDi3) {
474 removeOperands(MI, i);
475 MachineInstrBuilder MIB(&MI);
476 AddDefaultPred(AddDefaultCC(MIB).addReg(FrameReg).addImm(Mask));
478 MI.getOperand(i).ChangeToRegister(FrameReg, false);
479 MI.getOperand(i+1).ChangeToImmediate(Mask);
481 Offset = (Offset - Mask * Scale);
482 MachineBasicBlock::iterator NII = next(II);
483 emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII,
486 // Translate r0 = add sp, -imm to
487 // r0 = -imm (this is then translated into a series of instructons)
489 emitThumbConstant(MBB, II, DestReg, Offset, TII, *this, dl);
490 MI.setDesc(TII.get(ARM::tADDhirr));
491 MI.getOperand(i).ChangeToRegister(DestReg, false, false, true);
492 MI.getOperand(i+1).ChangeToRegister(FrameReg, false);
498 unsigned NumBits = 0;
501 case ARMII::AddrModeT1_s: {
503 InstrOffs = MI.getOperand(ImmIdx).getImm();
504 NumBits = (FrameReg == ARM::SP) ? 8 : 5;
509 llvm_unreachable("Unsupported addressing mode!");
513 Offset += InstrOffs * Scale;
514 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
516 // Common case: small offset, fits into instruction.
517 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
518 int ImmedOffset = Offset / Scale;
519 unsigned Mask = (1 << NumBits) - 1;
520 if ((unsigned)Offset <= Mask * Scale) {
521 // Replace the FrameIndex with sp
522 MI.getOperand(i).ChangeToRegister(FrameReg, false);
523 ImmOp.ChangeToImmediate(ImmedOffset);
527 bool isThumSpillRestore = Opcode == ARM::tRestore || Opcode == ARM::tSpill;
528 if (AddrMode == ARMII::AddrModeT1_s) {
529 // Thumb tLDRspi, tSTRspi. These will change to instructions that use
530 // a different base register.
532 Mask = (1 << NumBits) - 1;
534 // If this is a thumb spill / restore, we will be using a constpool load to
535 // materialize the offset.
536 if (AddrMode == ARMII::AddrModeT1_s && isThumSpillRestore)
537 ImmOp.ChangeToImmediate(0);
539 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
540 ImmedOffset = ImmedOffset & Mask;
541 ImmOp.ChangeToImmediate(ImmedOffset);
542 Offset &= ~(Mask*Scale);
546 // If we get here, the immediate doesn't fit into the instruction. We folded
547 // as much as possible above, handle the rest, providing a register that is
549 assert(Offset && "This code isn't needed if offset already handled!");
551 // Remove predicate first.
552 int PIdx = MI.findFirstPredOperandIdx();
554 removeOperands(MI, PIdx);
556 if (Desc.mayLoad()) {
557 // Use the destination register to materialize sp + offset.
558 unsigned TmpReg = MI.getOperand(0).getReg();
560 if (Opcode == ARM::tRestore) {
561 if (FrameReg == ARM::SP)
562 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
563 Offset, false, TII, *this, dl);
565 emitLoadConstPool(MBB, II, dl, TmpReg, 0, Offset);
569 emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII,
573 MI.setDesc(TII.get(ARM::tLDR));
574 MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
576 // Use [reg, reg] addrmode.
577 MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
578 else // tLDR has an extra register operand.
579 MI.addOperand(MachineOperand::CreateReg(0, false));
580 } else if (Desc.mayStore()) {
581 // FIXME! This is horrific!!! We need register scavenging.
582 // Our temporary workaround has marked r3 unavailable. Of course, r3 is
583 // also a ABI register so it's possible that is is the register that is
584 // being storing here. If that's the case, we do the following:
586 // Use r2 to materialize sp + offset
589 unsigned ValReg = MI.getOperand(0).getReg();
590 unsigned TmpReg = ARM::R3;
592 if (ValReg == ARM::R3) {
593 BuildMI(MBB, II, dl, TII.get(ARM::tMOVlor2hir), ARM::R12)
594 .addReg(ARM::R2, RegState::Kill);
597 if (TmpReg == ARM::R3 && AFI->isR3LiveIn())
598 BuildMI(MBB, II, dl, TII.get(ARM::tMOVlor2hir), ARM::R12)
599 .addReg(ARM::R3, RegState::Kill);
600 if (Opcode == ARM::tSpill) {
601 if (FrameReg == ARM::SP)
602 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
603 Offset, false, TII, *this, dl);
605 emitLoadConstPool(MBB, II, dl, TmpReg, 0, Offset);
609 emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII,
611 MI.setDesc(TII.get(ARM::tSTR));
612 MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
613 if (UseRR) // Use [reg, reg] addrmode.
614 MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
615 else // tSTR has an extra register operand.
616 MI.addOperand(MachineOperand::CreateReg(0, false));
618 MachineBasicBlock::iterator NII = next(II);
619 if (ValReg == ARM::R3)
620 BuildMI(MBB, NII, dl, TII.get(ARM::tMOVhir2lor), ARM::R2)
621 .addReg(ARM::R12, RegState::Kill);
622 if (TmpReg == ARM::R3 && AFI->isR3LiveIn())
623 BuildMI(MBB, NII, dl, TII.get(ARM::tMOVhir2lor), ARM::R3)
624 .addReg(ARM::R12, RegState::Kill);
626 assert(false && "Unexpected opcode!");
628 // Add predicate back if it's needed.
629 if (MI.getDesc().isPredicable()) {
630 MachineInstrBuilder MIB(&MI);
635 void Thumb1RegisterInfo::emitPrologue(MachineFunction &MF) const {
636 MachineBasicBlock &MBB = MF.front();
637 MachineBasicBlock::iterator MBBI = MBB.begin();
638 MachineFrameInfo *MFI = MF.getFrameInfo();
639 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
640 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
641 unsigned NumBytes = MFI->getStackSize();
642 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
643 DebugLoc dl = (MBBI != MBB.end() ?
644 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
646 // Check if R3 is live in. It might have to be used as a scratch register.
647 for (MachineRegisterInfo::livein_iterator I =MF.getRegInfo().livein_begin(),
648 E = MF.getRegInfo().livein_end(); I != E; ++I) {
649 if (I->first == ARM::R3) {
650 AFI->setR3IsLiveIn(true);
655 // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
656 NumBytes = (NumBytes + 3) & ~3;
657 MFI->setStackSize(NumBytes);
659 // Determine the sizes of each callee-save spill areas and record which frame
660 // belongs to which callee-save spill areas.
661 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
662 int FramePtrSpillFI = 0;
665 emitSPUpdate(MBB, MBBI, TII, dl, *this, -VARegSaveSize);
667 if (!AFI->hasStackFrame()) {
669 emitSPUpdate(MBB, MBBI, TII, dl, *this, -NumBytes);
673 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
674 unsigned Reg = CSI[i].getReg();
675 int FI = CSI[i].getFrameIdx();
683 FramePtrSpillFI = FI;
684 AFI->addGPRCalleeSavedArea1Frame(FI);
692 FramePtrSpillFI = FI;
693 if (STI.isTargetDarwin()) {
694 AFI->addGPRCalleeSavedArea2Frame(FI);
697 AFI->addGPRCalleeSavedArea1Frame(FI);
702 AFI->addDPRCalleeSavedAreaFrame(FI);
707 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
709 if (MBBI != MBB.end())
710 dl = MBBI->getDebugLoc();
713 // Darwin ABI requires FP to point to the stack slot that contains the
715 if (STI.isTargetDarwin() || hasFP(MF)) {
716 MachineInstrBuilder MIB =
717 BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
718 .addFrameIndex(FramePtrSpillFI).addImm(0);
721 // Determine starting offsets of spill areas.
722 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
723 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
724 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
725 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
726 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
727 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
728 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
730 NumBytes = DPRCSOffset;
732 // Insert it after all the callee-save spills.
733 emitSPUpdate(MBB, MBBI, TII, dl, *this, -NumBytes);
736 if (STI.isTargetELF() && hasFP(MF)) {
737 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
738 AFI->getFramePtrSpillOffset());
741 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
742 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
743 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
746 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
747 for (unsigned i = 0; CSRegs[i]; ++i)
748 if (Reg == CSRegs[i])
753 static bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) {
754 return (MI->getOpcode() == ARM::tRestore &&
755 MI->getOperand(1).isFI() &&
756 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
759 void Thumb1RegisterInfo::emitEpilogue(MachineFunction &MF,
760 MachineBasicBlock &MBB) const {
761 MachineBasicBlock::iterator MBBI = prior(MBB.end());
762 assert((MBBI->getOpcode() == ARM::tBX_RET ||
763 MBBI->getOpcode() == ARM::tPOP_RET) &&
764 "Can only insert epilog into returning blocks");
765 DebugLoc dl = MBBI->getDebugLoc();
766 MachineFrameInfo *MFI = MF.getFrameInfo();
767 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
768 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
769 int NumBytes = (int)MFI->getStackSize();
771 if (!AFI->hasStackFrame()) {
773 emitSPUpdate(MBB, MBBI, TII, dl, *this, NumBytes);
775 // Unwind MBBI to point to first LDR / FLDD.
776 const unsigned *CSRegs = getCalleeSavedRegs();
777 if (MBBI != MBB.begin()) {
780 while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));
781 if (!isCSRestore(MBBI, CSRegs))
785 // Move SP to start of FP callee save spill area.
786 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
787 AFI->getGPRCalleeSavedArea2Size() +
788 AFI->getDPRCalleeSavedAreaSize());
791 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
792 // Reset SP based on frame pointer only if the stack frame extends beyond
793 // frame pointer stack slot or target is ELF and the function has FP.
795 emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, FramePtr, -NumBytes,
798 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVlor2hir), ARM::SP)
801 if (MBBI->getOpcode() == ARM::tBX_RET &&
802 &MBB.front() != MBBI &&
803 prior(MBBI)->getOpcode() == ARM::tPOP) {
804 MachineBasicBlock::iterator PMBBI = prior(MBBI);
805 emitSPUpdate(MBB, PMBBI, TII, dl, *this, NumBytes);
807 emitSPUpdate(MBB, MBBI, TII, dl, *this, NumBytes);
812 // Epilogue for vararg functions: pop LR to R3 and branch off it.
813 // FIXME: Verify this is still ok when R3 is no longer being reserved.
814 BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)).addReg(ARM::R3);
816 emitSPUpdate(MBB, MBBI, TII, dl, *this, VARegSaveSize);
818 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg)).addReg(ARM::R3);