1 //===- Thumb1RegisterInfo.cpp - Thumb-1 Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb-1 implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "ARMAddressingModes.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMMachineFunctionInfo.h"
18 #include "ARMSubtarget.h"
19 #include "Thumb1InstrInfo.h"
20 #include "Thumb1RegisterInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/Function.h"
24 #include "llvm/LLVMContext.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineLocation.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/Target/TargetFrameInfo.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/ADT/BitVector.h"
34 #include "llvm/ADT/SmallVector.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
40 Thumb1RegisterInfo::Thumb1RegisterInfo(const ARMBaseInstrInfo &tii,
41 const ARMSubtarget &sti)
42 : ARMBaseRegisterInfo(tii, sti) {
45 /// emitLoadConstPool - Emits a load from constpool to materialize the
46 /// specified immediate.
47 void Thumb1RegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
48 MachineBasicBlock::iterator &MBBI,
50 unsigned DestReg, unsigned SubIdx,
52 ARMCC::CondCodes Pred,
53 unsigned PredReg) const {
54 MachineFunction &MF = *MBB.getParent();
55 MachineConstantPool *ConstantPool = MF.getConstantPool();
56 Constant *C = ConstantInt::get(
57 Type::getInt32Ty(MBB.getParent()->getFunction()->getContext()), Val);
58 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
60 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRcp))
61 .addReg(DestReg, getDefRegState(true), SubIdx)
62 .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg);
65 const TargetRegisterClass*
66 Thumb1RegisterInfo::getPhysicalRegisterRegClass(unsigned Reg, EVT VT) const {
67 if (isARMLowRegister(Reg))
68 return ARM::tGPRRegisterClass;
72 case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11:
73 case ARM::R12: case ARM::SP: case ARM::LR: case ARM::PC:
74 return ARM::GPRRegisterClass;
77 return TargetRegisterInfo::getPhysicalRegisterRegClass(Reg, VT);
81 Thumb1RegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
86 Thumb1RegisterInfo::requiresFrameIndexScavenging(const MachineFunction &MF)
92 bool Thumb1RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
93 const MachineFrameInfo *FFI = MF.getFrameInfo();
94 unsigned CFSize = FFI->getMaxCallFrameSize();
95 // It's not always a good idea to include the call frame as part of the
96 // stack frame. ARM (especially Thumb) has small immediate offset to
97 // address the stack frame. So a large call frame can cause poor codegen
98 // and may even makes it impossible to scavenge a register.
99 if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4
102 return !MF.getFrameInfo()->hasVarSizedObjects();
106 /// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize
107 /// a destreg = basereg + immediate in Thumb code. Materialize the immediate
108 /// in a register using mov / mvn sequences or load the immediate from a
111 void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
112 MachineBasicBlock::iterator &MBBI,
113 unsigned DestReg, unsigned BaseReg,
114 int NumBytes, bool CanChangeCC,
115 const TargetInstrInfo &TII,
116 const Thumb1RegisterInfo& MRI,
118 MachineFunction &MF = *MBB.getParent();
119 bool isHigh = !isARMLowRegister(DestReg) ||
120 (BaseReg != 0 && !isARMLowRegister(BaseReg));
122 // Subtract doesn't have high register version. Load the negative value
123 // if either base or dest register is a high register. Also, if do not
124 // issue sub as part of the sequence if condition register is to be
126 if (NumBytes < 0 && !isHigh && CanChangeCC) {
128 NumBytes = -NumBytes;
130 unsigned LdReg = DestReg;
131 if (DestReg == ARM::SP) {
132 assert(BaseReg == ARM::SP && "Unexpected!");
133 LdReg = MF.getRegInfo().createVirtualRegister(ARM::tGPRRegisterClass);
136 if (NumBytes <= 255 && NumBytes >= 0)
137 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
139 else if (NumBytes < 0 && NumBytes >= -255) {
140 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
142 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tRSB), LdReg))
143 .addReg(LdReg, RegState::Kill);
145 MRI.emitLoadConstPool(MBB, MBBI, dl, LdReg, 0, NumBytes);
148 int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
149 MachineInstrBuilder MIB =
150 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
151 if (Opc != ARM::tADDhirr)
152 MIB = AddDefaultT1CC(MIB);
153 if (DestReg == ARM::SP || isSub)
154 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
156 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
160 /// calcNumMI - Returns the number of instructions required to materialize
161 /// the specific add / sub r, c instruction.
162 static unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes,
163 unsigned NumBits, unsigned Scale) {
165 unsigned Chunk = ((1 << NumBits) - 1) * Scale;
167 if (Opc == ARM::tADDrSPi) {
168 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
172 Scale = 1; // Followed by a number of tADDi8.
173 Chunk = ((1 << NumBits) - 1) * Scale;
176 NumMIs += Bytes / Chunk;
177 if ((Bytes % Chunk) != 0)
184 /// emitThumbRegPlusImmediate - Emits a series of instructions to materialize
185 /// a destreg = basereg + immediate in Thumb code.
187 void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
188 MachineBasicBlock::iterator &MBBI,
189 unsigned DestReg, unsigned BaseReg,
190 int NumBytes, const TargetInstrInfo &TII,
191 const Thumb1RegisterInfo& MRI,
193 bool isSub = NumBytes < 0;
194 unsigned Bytes = (unsigned)NumBytes;
195 if (isSub) Bytes = -NumBytes;
196 bool isMul4 = (Bytes & 3) == 0;
197 bool isTwoAddr = false;
198 bool DstNotEqBase = false;
199 unsigned NumBits = 1;
204 bool NeedPred = false;
206 if (DestReg == BaseReg && BaseReg == ARM::SP) {
207 assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
210 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
212 } else if (!isSub && BaseReg == ARM::SP) {
215 // r1 = add sp, 100 * 4
219 ExtraOpc = ARM::tADDi3;
228 if (DestReg != BaseReg)
231 if (DestReg == ARM::SP) {
232 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
233 assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
237 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
239 NeedPred = NeedCC = true;
244 unsigned NumMIs = calcNumMI(Opc, ExtraOpc, Bytes, NumBits, Scale);
245 unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2;
246 if (NumMIs > Threshold) {
247 // This will expand into too many instructions. Load the immediate from a
249 emitThumbRegPlusImmInReg(MBB, MBBI, DestReg, BaseReg, NumBytes, true, TII,
255 if (isARMLowRegister(DestReg) && isARMLowRegister(BaseReg)) {
256 // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7)
257 unsigned Chunk = (1 << 3) - 1;
258 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
260 const TargetInstrDesc &TID = TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3);
261 const MachineInstrBuilder MIB =
262 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TID, DestReg));
263 AddDefaultPred(MIB.addReg(BaseReg, RegState::Kill).addImm(ThisVal));
265 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
266 .addReg(BaseReg, RegState::Kill);
271 unsigned Chunk = ((1 << NumBits) - 1) * Scale;
273 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
276 // Build the new tADD / tSUB.
278 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
280 MIB = AddDefaultT1CC(MIB);
281 MIB .addReg(DestReg).addImm(ThisVal);
283 MIB = AddDefaultPred(MIB);
286 bool isKill = BaseReg != ARM::SP;
287 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
289 MIB = AddDefaultT1CC(MIB);
290 MIB.addReg(BaseReg, getKillRegState(isKill)).addImm(ThisVal);
292 MIB = AddDefaultPred(MIB);
295 if (Opc == ARM::tADDrSPi) {
301 Chunk = ((1 << NumBits) - 1) * Scale;
302 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
303 NeedPred = NeedCC = isTwoAddr = true;
309 const TargetInstrDesc &TID = TII.get(ExtraOpc);
310 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TID, DestReg))
311 .addReg(DestReg, RegState::Kill)
312 .addImm(((unsigned)NumBytes) & 3));
316 static void emitSPUpdate(MachineBasicBlock &MBB,
317 MachineBasicBlock::iterator &MBBI,
318 const TargetInstrInfo &TII, DebugLoc dl,
319 const Thumb1RegisterInfo &MRI,
321 emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII,
325 void Thumb1RegisterInfo::
326 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
327 MachineBasicBlock::iterator I) const {
328 if (!hasReservedCallFrame(MF)) {
329 // If we have alloca, convert as follows:
330 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
331 // ADJCALLSTACKUP -> add, sp, sp, amount
332 MachineInstr *Old = I;
333 DebugLoc dl = Old->getDebugLoc();
334 unsigned Amount = Old->getOperand(0).getImm();
336 // We need to keep the stack aligned properly. To do this, we round the
337 // amount of space needed for the outgoing arguments up to the next
338 // alignment boundary.
339 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
340 Amount = (Amount+Align-1)/Align*Align;
342 // Replace the pseudo instruction with a new instruction...
343 unsigned Opc = Old->getOpcode();
344 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
345 emitSPUpdate(MBB, I, TII, dl, *this, -Amount);
347 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
348 emitSPUpdate(MBB, I, TII, dl, *this, Amount);
355 /// emitThumbConstant - Emit a series of instructions to materialize a
357 static void emitThumbConstant(MachineBasicBlock &MBB,
358 MachineBasicBlock::iterator &MBBI,
359 unsigned DestReg, int Imm,
360 const TargetInstrInfo &TII,
361 const Thumb1RegisterInfo& MRI,
363 bool isSub = Imm < 0;
364 if (isSub) Imm = -Imm;
366 int Chunk = (1 << 8) - 1;
367 int ThisVal = (Imm > Chunk) ? Chunk : Imm;
369 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8),
373 emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII, MRI, dl);
375 const TargetInstrDesc &TID = TII.get(ARM::tRSB);
376 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TID, DestReg))
377 .addReg(DestReg, RegState::Kill));
381 static void removeOperands(MachineInstr &MI, unsigned i) {
383 for (unsigned e = MI.getNumOperands(); i != e; ++i)
384 MI.RemoveOperand(Op);
387 int Thumb1RegisterInfo::
388 rewriteFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
389 unsigned FrameReg, int Offset,
390 unsigned MOVOpc, unsigned ADDriOpc, unsigned SUBriOpc) const
392 // if/when eliminateFrameIndex() conforms with ARMBaseRegisterInfo
393 // version then can pull out Thumb1 specific parts here
397 /// saveScavengerRegister - Spill the register so it can be used by the
398 /// register scavenger. Return true.
400 Thumb1RegisterInfo::saveScavengerRegister(MachineBasicBlock &MBB,
401 MachineBasicBlock::iterator I,
402 MachineBasicBlock::iterator &UseMI,
403 const TargetRegisterClass *RC,
404 unsigned Reg) const {
405 // Thumb1 can't use the emergency spill slot on the stack because
406 // ldr/str immediate offsets must be positive, and if we're referencing
407 // off the frame pointer (if, for example, there are alloca() calls in
408 // the function, the offset will be negative. Use R12 instead since that's
409 // a call clobbered register that we know won't be used in Thumb1 mode.
410 DebugLoc DL = DebugLoc::getUnknownLoc();
411 BuildMI(MBB, I, DL, TII.get(ARM::tMOVtgpr2gpr)).
412 addReg(ARM::R12, RegState::Define).addReg(Reg, RegState::Kill);
414 // The UseMI is where we would like to restore the register. If there's
415 // interference with R12 before then, however, we'll need to restore it
416 // before that instead and adjust the UseMI.
418 for (MachineBasicBlock::iterator II = I; !done && II != UseMI ; ++II) {
419 // If this instruction affects R12, adjust our restore point.
420 for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) {
421 const MachineOperand &MO = II->getOperand(i);
422 if (!MO.isReg() || MO.isUndef() || !MO.getReg() ||
423 TargetRegisterInfo::isVirtualRegister(MO.getReg()))
425 if (MO.getReg() == ARM::R12) {
432 // Restore the register from R12
433 BuildMI(MBB, UseMI, DL, TII.get(ARM::tMOVgpr2tgpr)).
434 addReg(Reg, RegState::Define).addReg(ARM::R12, RegState::Kill);
440 Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
441 int SPAdj, int *Value,
442 RegScavenger *RS) const{
445 MachineInstr &MI = *II;
446 MachineBasicBlock &MBB = *MI.getParent();
447 MachineFunction &MF = *MBB.getParent();
448 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
449 DebugLoc dl = MI.getDebugLoc();
451 while (!MI.getOperand(i).isFI()) {
453 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
456 unsigned FrameReg = ARM::SP;
457 int FrameIndex = MI.getOperand(i).getIndex();
458 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
459 MF.getFrameInfo()->getStackSize() + SPAdj;
461 if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex))
462 Offset -= AFI->getGPRCalleeSavedArea1Offset();
463 else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex))
464 Offset -= AFI->getGPRCalleeSavedArea2Offset();
465 else if (hasFP(MF)) {
466 assert(SPAdj == 0 && "Unexpected");
467 // There is alloca()'s in this function, must reference off the frame
469 FrameReg = getFrameRegister(MF);
470 Offset -= AFI->getFramePtrSpillOffset();
473 unsigned Opcode = MI.getOpcode();
474 const TargetInstrDesc &Desc = MI.getDesc();
475 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
477 if (Opcode == ARM::tADDrSPi) {
478 Offset += MI.getOperand(i+1).getImm();
480 // Can't use tADDrSPi if it's based off the frame pointer.
481 unsigned NumBits = 0;
483 if (FrameReg != ARM::SP) {
484 Opcode = ARM::tADDi3;
485 MI.setDesc(TII.get(Opcode));
490 assert((Offset & 3) == 0 &&
491 "Thumb add/sub sp, #imm immediate must be multiple of 4!");
495 // Turn it into a move.
496 MI.setDesc(TII.get(ARM::tMOVgpr2tgpr));
497 MI.getOperand(i).ChangeToRegister(FrameReg, false);
498 MI.RemoveOperand(i+1);
502 // Common case: small offset, fits into instruction.
503 unsigned Mask = (1 << NumBits) - 1;
504 if (((Offset / Scale) & ~Mask) == 0) {
505 // Replace the FrameIndex with sp / fp
506 if (Opcode == ARM::tADDi3) {
507 removeOperands(MI, i);
508 MachineInstrBuilder MIB(&MI);
509 AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg)
510 .addImm(Offset / Scale));
512 MI.getOperand(i).ChangeToRegister(FrameReg, false);
513 MI.getOperand(i+1).ChangeToImmediate(Offset / Scale);
518 unsigned DestReg = MI.getOperand(0).getReg();
519 unsigned Bytes = (Offset > 0) ? Offset : -Offset;
520 unsigned NumMIs = calcNumMI(Opcode, 0, Bytes, NumBits, Scale);
521 // MI would expand into a large number of instructions. Don't try to
522 // simplify the immediate.
524 emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII,
531 // Translate r0 = add sp, imm to
532 // r0 = add sp, 255*4
533 // r0 = add r0, (imm - 255*4)
534 if (Opcode == ARM::tADDi3) {
535 removeOperands(MI, i);
536 MachineInstrBuilder MIB(&MI);
537 AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg).addImm(Mask));
539 MI.getOperand(i).ChangeToRegister(FrameReg, false);
540 MI.getOperand(i+1).ChangeToImmediate(Mask);
542 Offset = (Offset - Mask * Scale);
543 MachineBasicBlock::iterator NII = next(II);
544 emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII,
547 // Translate r0 = add sp, -imm to
548 // r0 = -imm (this is then translated into a series of instructons)
550 emitThumbConstant(MBB, II, DestReg, Offset, TII, *this, dl);
552 MI.setDesc(TII.get(ARM::tADDhirr));
553 MI.getOperand(i).ChangeToRegister(DestReg, false, false, true);
554 MI.getOperand(i+1).ChangeToRegister(FrameReg, false);
555 if (Opcode == ARM::tADDi3) {
556 MachineInstrBuilder MIB(&MI);
564 unsigned NumBits = 0;
567 case ARMII::AddrModeT1_s: {
569 InstrOffs = MI.getOperand(ImmIdx).getImm();
570 NumBits = (FrameReg == ARM::SP) ? 8 : 5;
575 llvm_unreachable("Unsupported addressing mode!");
579 Offset += InstrOffs * Scale;
580 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
582 // Common case: small offset, fits into instruction.
583 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
584 int ImmedOffset = Offset / Scale;
585 unsigned Mask = (1 << NumBits) - 1;
586 if ((unsigned)Offset <= Mask * Scale) {
587 // Replace the FrameIndex with sp
588 MI.getOperand(i).ChangeToRegister(FrameReg, false);
589 ImmOp.ChangeToImmediate(ImmedOffset);
593 bool isThumSpillRestore = Opcode == ARM::tRestore || Opcode == ARM::tSpill;
594 if (AddrMode == ARMII::AddrModeT1_s) {
595 // Thumb tLDRspi, tSTRspi. These will change to instructions that use
596 // a different base register.
598 Mask = (1 << NumBits) - 1;
600 // If this is a thumb spill / restore, we will be using a constpool load to
601 // materialize the offset.
602 if (AddrMode == ARMII::AddrModeT1_s && isThumSpillRestore)
603 ImmOp.ChangeToImmediate(0);
605 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
606 ImmedOffset = ImmedOffset & Mask;
607 ImmOp.ChangeToImmediate(ImmedOffset);
608 Offset &= ~(Mask*Scale);
612 // If we get here, the immediate doesn't fit into the instruction. We folded
613 // as much as possible above, handle the rest, providing a register that is
615 assert(Offset && "This code isn't needed if offset already handled!");
617 // Remove predicate first.
618 int PIdx = MI.findFirstPredOperandIdx();
620 removeOperands(MI, PIdx);
622 if (Desc.mayLoad()) {
623 // Use the destination register to materialize sp + offset.
624 unsigned TmpReg = MI.getOperand(0).getReg();
626 if (Opcode == ARM::tRestore) {
627 if (FrameReg == ARM::SP)
628 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
629 Offset, false, TII, *this, dl);
631 emitLoadConstPool(MBB, II, dl, TmpReg, 0, Offset);
635 emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII,
639 MI.setDesc(TII.get(ARM::tLDR));
640 MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
642 // Use [reg, reg] addrmode.
643 MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
644 else // tLDR has an extra register operand.
645 MI.addOperand(MachineOperand::CreateReg(0, false));
646 } else if (Desc.mayStore()) {
647 VReg = MF.getRegInfo().createVirtualRegister(ARM::tGPRRegisterClass);
648 assert (Value && "Frame index virtual allocated, but Value arg is NULL!");
652 if (Opcode == ARM::tSpill) {
653 if (FrameReg == ARM::SP)
654 emitThumbRegPlusImmInReg(MBB, II, VReg, FrameReg,
655 Offset, false, TII, *this, dl);
657 emitLoadConstPool(MBB, II, dl, VReg, 0, Offset);
661 emitThumbRegPlusImmediate(MBB, II, VReg, FrameReg, Offset, TII,
663 MI.setDesc(TII.get(ARM::tSTR));
664 MI.getOperand(i).ChangeToRegister(VReg, false, false, true);
665 if (UseRR) // Use [reg, reg] addrmode.
666 MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
667 else // tSTR has an extra register operand.
668 MI.addOperand(MachineOperand::CreateReg(0, false));
670 assert(false && "Unexpected opcode!");
672 // Add predicate back if it's needed.
673 if (MI.getDesc().isPredicable()) {
674 MachineInstrBuilder MIB(&MI);
680 void Thumb1RegisterInfo::emitPrologue(MachineFunction &MF) const {
681 MachineBasicBlock &MBB = MF.front();
682 MachineBasicBlock::iterator MBBI = MBB.begin();
683 MachineFrameInfo *MFI = MF.getFrameInfo();
684 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
685 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
686 unsigned NumBytes = MFI->getStackSize();
687 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
688 DebugLoc dl = (MBBI != MBB.end() ?
689 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
691 // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
692 NumBytes = (NumBytes + 3) & ~3;
693 MFI->setStackSize(NumBytes);
695 // Determine the sizes of each callee-save spill areas and record which frame
696 // belongs to which callee-save spill areas.
697 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
698 int FramePtrSpillFI = 0;
701 emitSPUpdate(MBB, MBBI, TII, dl, *this, -VARegSaveSize);
703 if (!AFI->hasStackFrame()) {
705 emitSPUpdate(MBB, MBBI, TII, dl, *this, -NumBytes);
709 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
710 unsigned Reg = CSI[i].getReg();
711 int FI = CSI[i].getFrameIdx();
719 FramePtrSpillFI = FI;
720 AFI->addGPRCalleeSavedArea1Frame(FI);
728 FramePtrSpillFI = FI;
729 if (STI.isTargetDarwin()) {
730 AFI->addGPRCalleeSavedArea2Frame(FI);
733 AFI->addGPRCalleeSavedArea1Frame(FI);
738 AFI->addDPRCalleeSavedAreaFrame(FI);
743 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
745 if (MBBI != MBB.end())
746 dl = MBBI->getDebugLoc();
749 // Darwin ABI requires FP to point to the stack slot that contains the
751 if (STI.isTargetDarwin() || hasFP(MF)) {
752 BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
753 .addFrameIndex(FramePtrSpillFI).addImm(0);
756 // Determine starting offsets of spill areas.
757 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
758 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
759 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
760 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
761 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
762 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
763 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
765 NumBytes = DPRCSOffset;
767 // Insert it after all the callee-save spills.
768 emitSPUpdate(MBB, MBBI, TII, dl, *this, -NumBytes);
771 if (STI.isTargetELF() && hasFP(MF)) {
772 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
773 AFI->getFramePtrSpillOffset());
776 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
777 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
778 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
781 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
782 for (unsigned i = 0; CSRegs[i]; ++i)
783 if (Reg == CSRegs[i])
788 static bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) {
789 return (MI->getOpcode() == ARM::tRestore &&
790 MI->getOperand(1).isFI() &&
791 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
794 void Thumb1RegisterInfo::emitEpilogue(MachineFunction &MF,
795 MachineBasicBlock &MBB) const {
796 MachineBasicBlock::iterator MBBI = prior(MBB.end());
797 assert((MBBI->getOpcode() == ARM::tBX_RET ||
798 MBBI->getOpcode() == ARM::tPOP_RET) &&
799 "Can only insert epilog into returning blocks");
800 DebugLoc dl = MBBI->getDebugLoc();
801 MachineFrameInfo *MFI = MF.getFrameInfo();
802 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
803 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
804 int NumBytes = (int)MFI->getStackSize();
806 if (!AFI->hasStackFrame()) {
808 emitSPUpdate(MBB, MBBI, TII, dl, *this, NumBytes);
810 // Unwind MBBI to point to first LDR / FLDD.
811 const unsigned *CSRegs = getCalleeSavedRegs();
812 if (MBBI != MBB.begin()) {
815 while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));
816 if (!isCSRestore(MBBI, CSRegs))
820 // Move SP to start of FP callee save spill area.
821 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
822 AFI->getGPRCalleeSavedArea2Size() +
823 AFI->getDPRCalleeSavedAreaSize());
826 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
827 // Reset SP based on frame pointer only if the stack frame extends beyond
828 // frame pointer stack slot or target is ELF and the function has FP.
830 emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, FramePtr, -NumBytes,
833 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
836 if (MBBI->getOpcode() == ARM::tBX_RET &&
837 &MBB.front() != MBBI &&
838 prior(MBBI)->getOpcode() == ARM::tPOP) {
839 MachineBasicBlock::iterator PMBBI = prior(MBBI);
840 emitSPUpdate(MBB, PMBBI, TII, dl, *this, NumBytes);
842 emitSPUpdate(MBB, MBBI, TII, dl, *this, NumBytes);
847 // Epilogue for vararg functions: pop LR to R3 and branch off it.
848 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)))
849 .addReg(0) // No write back.
850 .addReg(ARM::R3, RegState::Define);
852 emitSPUpdate(MBB, MBBI, TII, dl, *this, VARegSaveSize);
854 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg))
855 .addReg(ARM::R3, RegState::Kill);