1 //===- Thumb1InstrInfo.h - Thumb-1 Instruction Information ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb-1 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef THUMB1INSTRUCTIONINFO_H
15 #define THUMB1INSTRUCTIONINFO_H
17 #include "llvm/Target/TargetInstrInfo.h"
19 #include "ARMInstrInfo.h"
20 #include "Thumb1RegisterInfo.h"
25 class Thumb1InstrInfo : public ARMBaseInstrInfo {
26 Thumb1RegisterInfo RI;
28 explicit Thumb1InstrInfo(const ARMSubtarget &STI);
30 // Return the non-pre/post incrementing version of 'Opc'. Return 0
31 // if there is not such an opcode.
32 unsigned getUnindexedOpcode(unsigned Opc) const;
34 // Return the opcode that implements 'Op', or 0 if no opcode
35 unsigned getOpcode(ARMII::Op Op) const;
37 // Return true if the block does not fall through.
38 bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
40 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
41 /// such, whenever a client has an instance of instruction info, it should
42 /// always be able to get register info as well (through this method).
44 const Thumb1RegisterInfo &getRegisterInfo() const { return RI; }
46 bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
47 MachineBasicBlock::iterator MI,
48 const std::vector<CalleeSavedInfo> &CSI) const;
49 bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
50 MachineBasicBlock::iterator MI,
51 const std::vector<CalleeSavedInfo> &CSI) const;
53 bool isMoveInstr(const MachineInstr &MI,
54 unsigned &SrcReg, unsigned &DstReg,
55 unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
56 unsigned isLoadFromStackSlot(const MachineInstr *MI,
57 int &FrameIndex) const;
58 unsigned isStoreToStackSlot(const MachineInstr *MI,
59 int &FrameIndex) const;
61 bool copyRegToReg(MachineBasicBlock &MBB,
62 MachineBasicBlock::iterator I,
63 unsigned DestReg, unsigned SrcReg,
64 const TargetRegisterClass *DestRC,
65 const TargetRegisterClass *SrcRC) const;
66 void storeRegToStackSlot(MachineBasicBlock &MBB,
67 MachineBasicBlock::iterator MBBI,
68 unsigned SrcReg, bool isKill, int FrameIndex,
69 const TargetRegisterClass *RC) const;
71 void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
72 SmallVectorImpl<MachineOperand> &Addr,
73 const TargetRegisterClass *RC,
74 SmallVectorImpl<MachineInstr*> &NewMIs) const;
76 void loadRegFromStackSlot(MachineBasicBlock &MBB,
77 MachineBasicBlock::iterator MBBI,
78 unsigned DestReg, int FrameIndex,
79 const TargetRegisterClass *RC) const;
81 void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
82 SmallVectorImpl<MachineOperand> &Addr,
83 const TargetRegisterClass *RC,
84 SmallVectorImpl<MachineInstr*> &NewMIs) const;
86 bool canFoldMemoryOperand(const MachineInstr *MI,
87 const SmallVectorImpl<unsigned> &Ops) const;
89 MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
91 const SmallVectorImpl<unsigned> &Ops,
92 int FrameIndex) const;
94 MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
96 const SmallVectorImpl<unsigned> &Ops,
97 MachineInstr* LoadMI) const {
103 #endif // THUMB1INSTRUCTIONINFO_H