1 //===-- Thumb1FrameLowering.cpp - Thumb1 Frame Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb1 implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "Thumb1FrameLowering.h"
15 #include "ARMMachineFunctionInfo.h"
16 #include "llvm/CodeGen/LivePhysRegs.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineModuleInfo.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 Thumb1FrameLowering::Thumb1FrameLowering(const ARMSubtarget &sti)
26 : ARMFrameLowering(sti) {}
28 bool Thumb1FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const{
29 const MachineFrameInfo *FFI = MF.getFrameInfo();
30 unsigned CFSize = FFI->getMaxCallFrameSize();
31 // It's not always a good idea to include the call frame as part of the
32 // stack frame. ARM (especially Thumb) has small immediate offset to
33 // address the stack frame. So a large call frame can cause poor codegen
34 // and may even makes it impossible to scavenge a register.
35 if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4
38 return !MF.getFrameInfo()->hasVarSizedObjects();
42 emitSPUpdate(MachineBasicBlock &MBB,
43 MachineBasicBlock::iterator &MBBI,
44 const TargetInstrInfo &TII, DebugLoc dl,
45 const ThumbRegisterInfo &MRI,
46 int NumBytes, unsigned MIFlags = MachineInstr::NoFlags) {
47 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII,
52 void Thumb1FrameLowering::
53 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
54 MachineBasicBlock::iterator I) const {
55 const Thumb1InstrInfo &TII =
56 *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
57 const ThumbRegisterInfo *RegInfo =
58 static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
59 if (!hasReservedCallFrame(MF)) {
60 // If we have alloca, convert as follows:
61 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
62 // ADJCALLSTACKUP -> add, sp, sp, amount
63 MachineInstr *Old = I;
64 DebugLoc dl = Old->getDebugLoc();
65 unsigned Amount = Old->getOperand(0).getImm();
67 // We need to keep the stack aligned properly. To do this, we round the
68 // amount of space needed for the outgoing arguments up to the next
69 // alignment boundary.
70 unsigned Align = getStackAlignment();
71 Amount = (Amount+Align-1)/Align*Align;
73 // Replace the pseudo instruction with a new instruction...
74 unsigned Opc = Old->getOpcode();
75 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
76 emitSPUpdate(MBB, I, TII, dl, *RegInfo, -Amount);
78 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
79 emitSPUpdate(MBB, I, TII, dl, *RegInfo, Amount);
86 void Thumb1FrameLowering::emitPrologue(MachineFunction &MF,
87 MachineBasicBlock &MBB) const {
88 MachineBasicBlock::iterator MBBI = MBB.begin();
89 MachineFrameInfo *MFI = MF.getFrameInfo();
90 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
91 MachineModuleInfo &MMI = MF.getMMI();
92 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
93 const ThumbRegisterInfo *RegInfo =
94 static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
95 const Thumb1InstrInfo &TII =
96 *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
98 unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
99 unsigned NumBytes = MFI->getStackSize();
100 assert(NumBytes >= ArgRegsSaveSize &&
101 "ArgRegsSaveSize is included in NumBytes");
102 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
103 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
104 unsigned FramePtr = RegInfo->getFrameRegister(MF);
105 unsigned BasePtr = RegInfo->getBaseRegister();
108 // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
109 NumBytes = (NumBytes + 3) & ~3;
110 MFI->setStackSize(NumBytes);
112 // Determine the sizes of each callee-save spill areas and record which frame
113 // belongs to which callee-save spill areas.
114 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
115 int FramePtrSpillFI = 0;
117 if (ArgRegsSaveSize) {
118 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -ArgRegsSaveSize,
119 MachineInstr::FrameSetup);
120 CFAOffset -= ArgRegsSaveSize;
121 unsigned CFIIndex = MMI.addFrameInst(
122 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
123 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
124 .addCFIIndex(CFIIndex)
125 .setMIFlags(MachineInstr::FrameSetup);
128 if (!AFI->hasStackFrame()) {
129 if (NumBytes - ArgRegsSaveSize != 0) {
130 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -(NumBytes - ArgRegsSaveSize),
131 MachineInstr::FrameSetup);
132 CFAOffset -= NumBytes - ArgRegsSaveSize;
133 unsigned CFIIndex = MMI.addFrameInst(
134 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
135 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
136 .addCFIIndex(CFIIndex)
137 .setMIFlags(MachineInstr::FrameSetup);
142 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
143 unsigned Reg = CSI[i].getReg();
144 int FI = CSI[i].getFrameIdx();
150 if (STI.isTargetMachO()) {
161 FramePtrSpillFI = FI;
169 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
171 if (MBBI != MBB.end())
172 dl = MBBI->getDebugLoc();
175 // Determine starting offsets of spill areas.
176 unsigned DPRCSOffset = NumBytes - ArgRegsSaveSize - (GPRCS1Size + GPRCS2Size + DPRCSSize);
177 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
178 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
179 bool HasFP = hasFP(MF);
181 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) +
183 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
184 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
185 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
186 NumBytes = DPRCSOffset;
188 int FramePtrOffsetInBlock = 0;
189 unsigned adjustedGPRCS1Size = GPRCS1Size;
190 if (tryFoldSPUpdateIntoPushPop(STI, MF, std::prev(MBBI), NumBytes)) {
191 FramePtrOffsetInBlock = NumBytes;
192 adjustedGPRCS1Size += NumBytes;
196 if (adjustedGPRCS1Size) {
197 CFAOffset -= adjustedGPRCS1Size;
198 unsigned CFIIndex = MMI.addFrameInst(
199 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
200 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
201 .addCFIIndex(CFIIndex)
202 .setMIFlags(MachineInstr::FrameSetup);
204 for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(),
205 E = CSI.end(); I != E; ++I) {
206 unsigned Reg = I->getReg();
207 int FI = I->getFrameIdx();
214 if (STI.isTargetMachO())
226 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
227 nullptr, MRI->getDwarfRegNum(Reg, true), MFI->getObjectOffset(FI)));
228 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
229 .addCFIIndex(CFIIndex)
230 .setMIFlags(MachineInstr::FrameSetup);
235 // Adjust FP so it point to the stack slot that contains the previous FP.
237 FramePtrOffsetInBlock +=
238 MFI->getObjectOffset(FramePtrSpillFI) + GPRCS1Size + ArgRegsSaveSize;
239 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
240 .addReg(ARM::SP).addImm(FramePtrOffsetInBlock / 4)
241 .setMIFlags(MachineInstr::FrameSetup));
242 if(FramePtrOffsetInBlock) {
243 CFAOffset += FramePtrOffsetInBlock;
244 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createDefCfa(
245 nullptr, MRI->getDwarfRegNum(FramePtr, true), CFAOffset));
246 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
247 .addCFIIndex(CFIIndex)
248 .setMIFlags(MachineInstr::FrameSetup);
251 MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister(
252 nullptr, MRI->getDwarfRegNum(FramePtr, true)));
253 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
254 .addCFIIndex(CFIIndex)
255 .setMIFlags(MachineInstr::FrameSetup);
258 // If offset is > 508 then sp cannot be adjusted in a single instruction,
259 // try restoring from fp instead.
260 AFI->setShouldRestoreSPFromFP(true);
264 // Insert it after all the callee-save spills.
265 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes,
266 MachineInstr::FrameSetup);
268 CFAOffset -= NumBytes;
269 unsigned CFIIndex = MMI.addFrameInst(
270 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
271 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
272 .addCFIIndex(CFIIndex)
273 .setMIFlags(MachineInstr::FrameSetup);
277 if (STI.isTargetELF() && HasFP)
278 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
279 AFI->getFramePtrSpillOffset());
281 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
282 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
283 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
285 // Thumb1 does not currently support dynamic stack realignment. Report a
286 // fatal error rather then silently generate bad code.
287 if (RegInfo->needsStackRealignment(MF))
288 report_fatal_error("Dynamic stack realignment not supported for thumb1.");
290 // If we need a base pointer, set it up here. It's whatever the value
291 // of the stack pointer is at this point. Any variable size objects
292 // will be allocated after this, so we can still use the base pointer
293 // to reference locals.
294 if (RegInfo->hasBasePointer(MF))
295 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), BasePtr)
298 // If the frame has variable sized objects then the epilogue must restore
299 // the sp from fp. We can assume there's an FP here since hasFP already
300 // checks for hasVarSizedObjects.
301 if (MFI->hasVarSizedObjects())
302 AFI->setShouldRestoreSPFromFP(true);
305 static bool isCSRestore(MachineInstr *MI, const MCPhysReg *CSRegs) {
306 if (MI->getOpcode() == ARM::tLDRspi &&
307 MI->getOperand(1).isFI() &&
308 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs))
310 else if (MI->getOpcode() == ARM::tPOP) {
311 // The first two operands are predicates. The last two are
312 // imp-def and imp-use of SP. Check everything in between.
313 for (int i = 2, e = MI->getNumOperands() - 2; i != e; ++i)
314 if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs))
321 void Thumb1FrameLowering::emitEpilogue(MachineFunction &MF,
322 MachineBasicBlock &MBB) const {
323 MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator();
324 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
325 MachineFrameInfo *MFI = MF.getFrameInfo();
326 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
327 const ThumbRegisterInfo *RegInfo =
328 static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
329 const Thumb1InstrInfo &TII =
330 *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
332 unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
333 int NumBytes = (int)MFI->getStackSize();
334 assert((unsigned)NumBytes >= ArgRegsSaveSize &&
335 "ArgRegsSaveSize is included in NumBytes");
336 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
337 unsigned FramePtr = RegInfo->getFrameRegister(MF);
339 if (!AFI->hasStackFrame()) {
340 if (NumBytes - ArgRegsSaveSize != 0)
341 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes - ArgRegsSaveSize);
343 // Unwind MBBI to point to first LDR / VLDRD.
344 if (MBBI != MBB.begin()) {
347 while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));
348 if (!isCSRestore(MBBI, CSRegs))
352 // Move SP to start of FP callee save spill area.
353 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
354 AFI->getGPRCalleeSavedArea2Size() +
355 AFI->getDPRCalleeSavedAreaSize() +
358 if (AFI->shouldRestoreSPFromFP()) {
359 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
360 // Reset SP based on frame pointer only if the stack frame extends beyond
361 // frame pointer stack slot, the target is ELF and the function has FP, or
362 // the target uses var sized objects.
364 assert(!MFI->getPristineRegs(MF).test(ARM::R4) &&
365 "No scratch register to restore SP from FP!");
366 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
368 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
372 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
376 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tBX_RET &&
377 &MBB.front() != MBBI && std::prev(MBBI)->getOpcode() == ARM::tPOP) {
378 MachineBasicBlock::iterator PMBBI = std::prev(MBBI);
379 if (!tryFoldSPUpdateIntoPushPop(STI, MF, PMBBI, NumBytes))
380 emitSPUpdate(MBB, PMBBI, TII, dl, *RegInfo, NumBytes);
381 } else if (!tryFoldSPUpdateIntoPushPop(STI, MF, MBBI, NumBytes))
382 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes);
386 if (needPopSpecialFixUp(MF)) {
387 bool Done = emitPopSpecialFixUp(MBB, /* DoIt */ true);
389 assert(Done && "Emission of the special fixup failed!?");
393 bool Thumb1FrameLowering::canUseAsEpilogue(const MachineBasicBlock &MBB) const {
394 if (!needPopSpecialFixUp(*MBB.getParent()))
397 MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB);
398 return emitPopSpecialFixUp(*TmpMBB, /* DoIt */ false);
401 bool Thumb1FrameLowering::needPopSpecialFixUp(const MachineFunction &MF) const {
402 ARMFunctionInfo *AFI =
403 const_cast<MachineFunction *>(&MF)->getInfo<ARMFunctionInfo>();
404 if (AFI->getArgRegsSaveSize())
407 bool IsV4PopReturn = false;
408 for (const CalleeSavedInfo &CSI : MF.getFrameInfo()->getCalleeSavedInfo())
409 if (CSI.getReg() == ARM::LR)
410 IsV4PopReturn = true;
411 return IsV4PopReturn && STI.hasV4TOps() && !STI.hasV5TOps();
414 bool Thumb1FrameLowering::emitPopSpecialFixUp(MachineBasicBlock &MBB,
416 MachineFunction &MF = *MBB.getParent();
417 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
418 unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
419 const TargetInstrInfo &TII = *STI.getInstrInfo();
420 const ThumbRegisterInfo *RegInfo =
421 static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
423 // If MBBI is a return instruction, we may be able to directly restore
425 // This is possible if we do not need to emit any SP update.
426 // Otherwise, we need a temporary register to pop the value
427 // and copy that value into LR.
428 auto MBBI = MBB.getFirstTerminator();
429 if (!ArgRegsSaveSize && MBBI != MBB.end() &&
430 MBBI->getOpcode() == ARM::tBX_RET) {
433 MachineInstrBuilder MIB =
435 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII.get(ARM::tPOP_RET)))
436 .addReg(ARM::PC, RegState::Define);
437 MIB.copyImplicitOps(&*MBBI);
438 // erase the old tBX_RET instruction
443 // Look for a temporary register to use.
444 // First, compute the liveness information.
445 LivePhysRegs UsedRegs(STI.getRegisterInfo());
446 UsedRegs.addLiveOuts(&MBB, /*AddPristines*/ true);
447 // The semantic of pristines changed recently and now,
448 // the callee-saved registers that are touched in the function
449 // are not part of the pristines set anymore.
450 // Add those callee-saved now.
451 const TargetRegisterInfo *TRI = STI.getRegisterInfo();
452 const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF);
453 for (unsigned i = 0; CSRegs[i]; ++i)
454 UsedRegs.addReg(CSRegs[i]);
456 DebugLoc dl = DebugLoc();
457 if (MBBI != MBB.end()) {
458 dl = MBBI->getDebugLoc();
459 auto InstUpToMBBI = MBB.end();
460 // The post-decrement is on purpose here.
461 // We want to have the liveness right before MBBI.
462 while (InstUpToMBBI-- != MBBI)
463 UsedRegs.stepBackward(*InstUpToMBBI);
466 // Look for a register that can be directly use in the POP.
468 // And some temporary register, just in case.
469 unsigned TemporaryReg = 0;
470 BitVector PopFriendly =
471 TRI->getAllocatableSet(MF, TRI->getRegClass(ARM::tGPRRegClassID));
472 assert(PopFriendly.any() && "No allocatable pop-friendly register?!");
473 // Rebuild the GPRs from the high registers because they are removed
474 // form the GPR reg class for thumb1.
475 BitVector GPRsNoLRSP =
476 TRI->getAllocatableSet(MF, TRI->getRegClass(ARM::hGPRRegClassID));
477 GPRsNoLRSP |= PopFriendly;
478 GPRsNoLRSP.reset(ARM::LR);
479 GPRsNoLRSP.reset(ARM::SP);
480 GPRsNoLRSP.reset(ARM::PC);
481 for (int Register = GPRsNoLRSP.find_first(); Register != -1;
482 Register = GPRsNoLRSP.find_next(Register)) {
483 if (!UsedRegs.contains(Register)) {
484 // Remember the first pop-friendly register and exit.
485 if (PopFriendly.test(Register)) {
490 // Otherwise, remember that the register will be available to
491 // save a pop-friendly register.
492 TemporaryReg = Register;
496 if (!DoIt && !PopReg && !TemporaryReg)
499 assert((PopReg || TemporaryReg) && "Cannot get LR");
502 assert(!PopReg && "Unnecessary MOV is about to be inserted");
503 PopReg = PopFriendly.find_first();
504 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
505 .addReg(TemporaryReg, RegState::Define)
506 .addReg(PopReg, RegState::Kill));
509 assert(PopReg && "Do not know how to get LR");
510 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)))
511 .addReg(PopReg, RegState::Define);
513 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, ArgRegsSaveSize);
515 if (!TemporaryReg && MBBI != MBB.end() && MBBI->getOpcode() == ARM::tBX_RET) {
516 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX))
517 .addReg(PopReg, RegState::Kill);
519 MIB.copyImplicitOps(&*MBBI);
520 // erase the old tBX_RET instruction
525 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
526 .addReg(ARM::LR, RegState::Define)
527 .addReg(PopReg, RegState::Kill));
530 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
531 .addReg(PopReg, RegState::Define)
532 .addReg(TemporaryReg, RegState::Kill));
538 bool Thumb1FrameLowering::
539 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
540 MachineBasicBlock::iterator MI,
541 const std::vector<CalleeSavedInfo> &CSI,
542 const TargetRegisterInfo *TRI) const {
547 const TargetInstrInfo &TII = *STI.getInstrInfo();
549 if (MI != MBB.end()) DL = MI->getDebugLoc();
551 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH));
553 for (unsigned i = CSI.size(); i != 0; --i) {
554 unsigned Reg = CSI[i-1].getReg();
557 // Add the callee-saved register as live-in unless it's LR and
558 // @llvm.returnaddress is called. If LR is returned for @llvm.returnaddress
559 // then it's already added to the function and entry block live-in sets.
560 if (Reg == ARM::LR) {
561 MachineFunction &MF = *MBB.getParent();
562 if (MF.getFrameInfo()->isReturnAddressTaken() &&
563 MF.getRegInfo().isLiveIn(Reg))
570 MIB.addReg(Reg, getKillRegState(isKill));
572 MIB.setMIFlags(MachineInstr::FrameSetup);
576 bool Thumb1FrameLowering::
577 restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
578 MachineBasicBlock::iterator MI,
579 const std::vector<CalleeSavedInfo> &CSI,
580 const TargetRegisterInfo *TRI) const {
584 MachineFunction &MF = *MBB.getParent();
585 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
586 const TargetInstrInfo &TII = *STI.getInstrInfo();
588 bool isVarArg = AFI->getArgRegsSaveSize() > 0;
589 DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc();
590 MachineInstrBuilder MIB = BuildMI(MF, DL, TII.get(ARM::tPOP));
593 bool NumRegs = false;
594 for (unsigned i = CSI.size(); i != 0; --i) {
595 unsigned Reg = CSI[i-1].getReg();
596 if (Reg == ARM::LR && MBB.succ_empty()) {
597 // Special epilogue for vararg functions. See emitEpilogue
600 // ARMv4T requires BX, see emitEpilogue
601 if (STI.hasV4TOps() && !STI.hasV5TOps())
604 (*MIB).setDesc(TII.get(ARM::tPOP_RET));
606 MIB.copyImplicitOps(&*MI);
609 MIB.addReg(Reg, getDefRegState(true));
613 // It's illegal to emit pop instruction without operands.
615 MBB.insert(MI, &*MIB);
617 MF.DeleteMachineInstr(MIB);