1 //===-- NEONPreAllocPass.cpp - Allocate adjacent NEON registers--*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "neon-prealloc"
12 #include "ARMInstrInfo.h"
13 #include "llvm/CodeGen/MachineInstr.h"
14 #include "llvm/CodeGen/MachineInstrBuilder.h"
15 #include "llvm/CodeGen/MachineFunctionPass.h"
19 class VISIBILITY_HIDDEN NEONPreAllocPass : public MachineFunctionPass {
20 const TargetInstrInfo *TII;
24 NEONPreAllocPass() : MachineFunctionPass(&ID) {}
26 virtual bool runOnMachineFunction(MachineFunction &MF);
28 virtual const char *getPassName() const {
29 return "NEON register pre-allocation pass";
33 bool PreAllocNEONRegisters(MachineBasicBlock &MBB);
36 char NEONPreAllocPass::ID = 0;
39 static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd, unsigned &NumRegs,
40 unsigned &Offset, unsigned &Stride) {
41 // Default to unit stride with no offset.
231 bool NEONPreAllocPass::PreAllocNEONRegisters(MachineBasicBlock &MBB) {
232 bool Modified = false;
234 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
235 for (; MBBI != E; ++MBBI) {
236 MachineInstr *MI = &*MBBI;
237 unsigned FirstOpnd, NumRegs, Offset, Stride;
238 if (!isNEONMultiRegOp(MI->getOpcode(), FirstOpnd, NumRegs, Offset, Stride))
241 MachineBasicBlock::iterator NextI = next(MBBI);
242 for (unsigned R = 0; R < NumRegs; ++R) {
243 MachineOperand &MO = MI->getOperand(FirstOpnd + R);
244 assert(MO.isReg() && MO.getSubReg() == 0 && "unexpected operand");
245 unsigned VirtReg = MO.getReg();
246 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
247 "expected a virtual register");
249 // For now, just assign a fixed set of adjacent registers.
250 // This leaves plenty of room for future improvements.
251 static const unsigned NEONDRegs[] = {
252 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
253 ARM::D4, ARM::D5, ARM::D6, ARM::D7
255 MO.setReg(NEONDRegs[Offset + R * Stride]);
258 // Insert a copy from VirtReg.
259 TII->copyRegToReg(MBB, MBBI, MO.getReg(), VirtReg,
260 ARM::DPRRegisterClass, ARM::DPRRegisterClass);
262 MachineInstr *CopyMI = prior(MBBI);
263 CopyMI->findRegisterUseOperand(VirtReg)->setIsKill();
266 } else if (MO.isDef() && !MO.isDead()) {
267 // Add a copy to VirtReg.
268 TII->copyRegToReg(MBB, NextI, VirtReg, MO.getReg(),
269 ARM::DPRRegisterClass, ARM::DPRRegisterClass);
277 bool NEONPreAllocPass::runOnMachineFunction(MachineFunction &MF) {
278 TII = MF.getTarget().getInstrInfo();
280 bool Modified = false;
281 for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E;
283 MachineBasicBlock &MBB = *MFI;
284 Modified |= PreAllocNEONRegisters(MBB);
290 /// createNEONPreAllocPass - returns an instance of the NEON register
291 /// pre-allocation pass.
292 FunctionPass *llvm::createNEONPreAllocPass() {
293 return new NEONPreAllocPass();