1 //===-- NEONPreAllocPass.cpp - Allocate adjacent NEON registers--*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "neon-prealloc"
12 #include "ARMInstrInfo.h"
13 #include "llvm/CodeGen/MachineInstr.h"
14 #include "llvm/CodeGen/MachineInstrBuilder.h"
15 #include "llvm/CodeGen/MachineRegisterInfo.h"
16 #include "llvm/CodeGen/MachineFunctionPass.h"
20 class NEONPreAllocPass : public MachineFunctionPass {
21 const TargetInstrInfo *TII;
22 MachineRegisterInfo *MRI;
26 NEONPreAllocPass() : MachineFunctionPass(ID) {}
28 virtual bool runOnMachineFunction(MachineFunction &MF);
30 virtual const char *getPassName() const {
31 return "NEON register pre-allocation pass";
35 bool FormsRegSequence(MachineInstr *MI,
36 unsigned FirstOpnd, unsigned NumRegs,
37 unsigned Offset, unsigned Stride) const;
38 bool PreAllocNEONRegisters(MachineBasicBlock &MBB);
41 char NEONPreAllocPass::ID = 0;
44 static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd, unsigned &NumRegs,
45 unsigned &Offset, unsigned &Stride) {
46 // Default to unit stride with no offset.
83 case ARM::VLD2LNq16odd:
84 case ARM::VLD2LNq32odd:
102 case ARM::VLD3q8_UPD:
103 case ARM::VLD3q16_UPD:
104 case ARM::VLD3q32_UPD:
111 case ARM::VLD3q8odd_UPD:
112 case ARM::VLD3q16odd_UPD:
113 case ARM::VLD3q32odd_UPD:
128 case ARM::VLD3LNq16odd:
129 case ARM::VLD3LNq32odd:
147 case ARM::VLD4q8_UPD:
148 case ARM::VLD4q16_UPD:
149 case ARM::VLD4q32_UPD:
156 case ARM::VLD4q8odd_UPD:
157 case ARM::VLD4q16odd_UPD:
158 case ARM::VLD4q32odd_UPD:
173 case ARM::VLD4LNq16odd:
174 case ARM::VLD4LNq32odd:
210 case ARM::VST2LNq16odd:
211 case ARM::VST2LNq32odd:
233 case ARM::VST3LNq16odd:
234 case ARM::VST3LNq32odd:
256 case ARM::VST4LNq16odd:
257 case ARM::VST4LNq32odd:
299 NEONPreAllocPass::FormsRegSequence(MachineInstr *MI,
300 unsigned FirstOpnd, unsigned NumRegs,
301 unsigned Offset, unsigned Stride) const {
302 MachineOperand &FMO = MI->getOperand(FirstOpnd);
303 assert(FMO.isReg() && FMO.getSubReg() == 0 && "unexpected operand");
304 unsigned VirtReg = FMO.getReg();
306 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
307 "expected a virtual register");
309 unsigned LastSubIdx = 0;
311 MachineInstr *RegSeq = 0;
312 for (unsigned R = 0; R < NumRegs; ++R) {
313 const MachineOperand &MO = MI->getOperand(FirstOpnd + R);
314 assert(MO.isReg() && MO.getSubReg() == 0 && "unexpected operand");
315 unsigned VirtReg = MO.getReg();
316 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
317 "expected a virtual register");
318 // Feeding into a REG_SEQUENCE.
319 if (!MRI->hasOneNonDBGUse(VirtReg))
321 MachineInstr *UseMI = &*MRI->use_nodbg_begin(VirtReg);
322 if (!UseMI->isRegSequence())
324 if (RegSeq && RegSeq != UseMI)
326 unsigned OpIdx = 1 + (Offset + R * Stride) * 2;
327 if (UseMI->getOperand(OpIdx).getReg() != VirtReg)
328 llvm_unreachable("Malformed REG_SEQUENCE instruction!");
329 unsigned SubIdx = UseMI->getOperand(OpIdx + 1).getImm();
331 if (LastSubIdx != SubIdx-Stride)
334 // Must start from dsub_0 or qsub_0.
335 if (SubIdx != (ARM::dsub_0+Offset) &&
336 SubIdx != (ARM::qsub_0+Offset))
343 // In the case of vld3, etc., make sure the trailing operand of
344 // REG_SEQUENCE is an undef.
346 unsigned OpIdx = 1 + (Offset + 3 * Stride) * 2;
347 const MachineOperand &MO = RegSeq->getOperand(OpIdx);
348 unsigned VirtReg = MO.getReg();
349 MachineInstr *DefMI = MRI->getVRegDef(VirtReg);
350 if (!DefMI || !DefMI->isImplicitDef())
356 unsigned LastSrcReg = 0;
357 SmallVector<unsigned, 4> SubIds;
358 for (unsigned R = 0; R < NumRegs; ++R) {
359 const MachineOperand &MO = MI->getOperand(FirstOpnd + R);
360 assert(MO.isReg() && MO.getSubReg() == 0 && "unexpected operand");
361 unsigned VirtReg = MO.getReg();
362 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
363 "expected a virtual register");
364 // Extracting from a Q or QQ register.
365 MachineInstr *DefMI = MRI->getVRegDef(VirtReg);
366 if (!DefMI || !DefMI->isCopy() || !DefMI->getOperand(1).getSubReg())
368 VirtReg = DefMI->getOperand(1).getReg();
369 if (LastSrcReg && LastSrcReg != VirtReg)
371 LastSrcReg = VirtReg;
372 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
373 if (RC != ARM::QPRRegisterClass &&
374 RC != ARM::QQPRRegisterClass &&
375 RC != ARM::QQQQPRRegisterClass)
377 unsigned SubIdx = DefMI->getOperand(1).getSubReg();
379 if (LastSubIdx != SubIdx-Stride)
382 // Must start from dsub_0 or qsub_0.
383 if (SubIdx != (ARM::dsub_0+Offset) &&
384 SubIdx != (ARM::qsub_0+Offset))
387 SubIds.push_back(SubIdx);
391 // FIXME: Update the uses of EXTRACT_SUBREG from REG_SEQUENCE is
392 // currently required for correctness. e.g.
393 // %reg1041<def> = REG_SEQUENCE %reg1040<kill>, 5, %reg1035<kill>, 6
394 // %reg1042<def> = EXTRACT_SUBREG %reg1041, 6
395 // %reg1043<def> = EXTRACT_SUBREG %reg1041, 5
396 // VST1q16 %reg1025<kill>, 0, %reg1043<kill>, %reg1042<kill>,
397 // reg1042 and reg1043 should be replaced with reg1041:6 and reg1041:5
399 // We need to change how we model uses of REG_SEQUENCE.
400 for (unsigned R = 0; R < NumRegs; ++R) {
401 MachineOperand &MO = MI->getOperand(FirstOpnd + R);
402 unsigned OldReg = MO.getReg();
403 MachineInstr *DefMI = MRI->getVRegDef(OldReg);
404 assert(DefMI->isCopy());
405 MO.setReg(LastSrcReg);
406 MO.setSubReg(SubIds[R]);
408 // Delete the EXTRACT_SUBREG if its result is now dead.
409 if (MRI->use_empty(OldReg))
410 DefMI->eraseFromParent();
416 bool NEONPreAllocPass::PreAllocNEONRegisters(MachineBasicBlock &MBB) {
417 bool Modified = false;
419 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
420 for (; MBBI != E; ++MBBI) {
421 MachineInstr *MI = &*MBBI;
422 unsigned FirstOpnd, NumRegs, Offset, Stride;
423 if (!isNEONMultiRegOp(MI->getOpcode(), FirstOpnd, NumRegs, Offset, Stride))
425 if (FormsRegSequence(MI, FirstOpnd, NumRegs, Offset, Stride))
428 MachineBasicBlock::iterator NextI = llvm::next(MBBI);
429 for (unsigned R = 0; R < NumRegs; ++R) {
430 MachineOperand &MO = MI->getOperand(FirstOpnd + R);
431 assert(MO.isReg() && MO.getSubReg() == 0 && "unexpected operand");
432 unsigned VirtReg = MO.getReg();
433 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
434 "expected a virtual register");
436 // For now, just assign a fixed set of adjacent registers.
437 // This leaves plenty of room for future improvements.
438 static const unsigned NEONDRegs[] = {
439 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
440 ARM::D4, ARM::D5, ARM::D6, ARM::D7
442 MO.setReg(NEONDRegs[Offset + R * Stride]);
445 // Insert a copy from VirtReg.
446 BuildMI(MBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY),MO.getReg())
447 .addReg(VirtReg, getKillRegState(MO.isKill()));
449 } else if (MO.isDef() && !MO.isDead()) {
450 // Add a copy to VirtReg.
451 BuildMI(MBB, NextI, DebugLoc(), TII->get(TargetOpcode::COPY), VirtReg)
452 .addReg(MO.getReg());
460 bool NEONPreAllocPass::runOnMachineFunction(MachineFunction &MF) {
461 TII = MF.getTarget().getInstrInfo();
462 MRI = &MF.getRegInfo();
464 bool Modified = false;
465 for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E;
467 MachineBasicBlock &MBB = *MFI;
468 Modified |= PreAllocNEONRegisters(MBB);
474 /// createNEONPreAllocPass - returns an instance of the NEON register
475 /// pre-allocation pass.
476 FunctionPass *llvm::createNEONPreAllocPass() {
477 return new NEONPreAllocPass();