1 //===-- ARMMCTargetDesc.h - ARM Target Descriptions -------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides ARM specific target descriptions.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMMCTARGETDESC_H
15 #define LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMMCTARGETDESC_H
17 #include "llvm/Support/DataTypes.h"
21 class formatted_raw_ostream;
29 class MCSubtargetInfo;
31 class MCRelocationInfo;
32 class MCTargetStreamer;
38 extern Target TheARMLETarget, TheThumbLETarget;
39 extern Target TheARMBETarget, TheThumbBETarget;
42 std::string ParseARMTriple(StringRef TT, StringRef CPU);
44 /// createARMMCSubtargetInfo - Create a ARM MCSubtargetInfo instance.
45 /// This is exposed so Asm parser, etc. do not need to go through
47 MCSubtargetInfo *createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
51 MCTargetStreamer *createARMNullTargetStreamer(MCStreamer &S);
52 MCTargetStreamer *createARMTargetAsmStreamer(MCStreamer &S,
53 formatted_raw_ostream &OS,
54 MCInstPrinter *InstPrint,
56 MCTargetStreamer *createARMObjectTargetStreamer(MCStreamer &S,
57 const MCSubtargetInfo &STI);
59 MCCodeEmitter *createARMLEMCCodeEmitter(const MCInstrInfo &MCII,
60 const MCRegisterInfo &MRI,
63 MCCodeEmitter *createARMBEMCCodeEmitter(const MCInstrInfo &MCII,
64 const MCRegisterInfo &MRI,
67 MCAsmBackend *createARMAsmBackend(const Target &T, const MCRegisterInfo &MRI,
68 StringRef TT, StringRef CPU,
71 MCAsmBackend *createARMLEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
72 StringRef TT, StringRef CPU);
74 MCAsmBackend *createARMBEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
75 StringRef TT, StringRef CPU);
77 MCAsmBackend *createThumbLEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
78 StringRef TT, StringRef CPU);
80 MCAsmBackend *createThumbBEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
81 StringRef TT, StringRef CPU);
83 // Construct a PE/COFF machine code streamer which will generate a PE/COFF
85 MCStreamer *createARMWinCOFFStreamer(MCContext &Context, MCAsmBackend &MAB,
86 raw_ostream &OS, MCCodeEmitter *Emitter,
89 /// createARMELFObjectWriter - Construct an ELF Mach-O object writer.
90 MCObjectWriter *createARMELFObjectWriter(raw_ostream &OS,
94 /// createARMMachObjectWriter - Construct an ARM Mach-O object writer.
95 MCObjectWriter *createARMMachObjectWriter(raw_ostream &OS,
100 /// createARMWinCOFFObjectWriter - Construct an ARM PE/COFF object writer.
101 MCObjectWriter *createARMWinCOFFObjectWriter(raw_ostream &OS, bool Is64Bit);
103 /// createARMMachORelocationInfo - Construct ARM Mach-O relocation info.
104 MCRelocationInfo *createARMMachORelocationInfo(MCContext &Ctx);
105 } // End llvm namespace
107 // Defines symbolic names for ARM registers. This defines a mapping from
108 // register name to register number.
110 #define GET_REGINFO_ENUM
111 #include "ARMGenRegisterInfo.inc"
113 // Defines symbolic names for the ARM instructions.
115 #define GET_INSTRINFO_ENUM
116 #include "ARMGenInstrInfo.inc"
118 #define GET_SUBTARGETINFO_ENUM
119 #include "ARMGenSubtargetInfo.inc"