lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp

   1 //===-- ARMMCTargetDesc.cpp - ARM Target Descriptions -----------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file provides ARM specific target descriptions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "ARMMCTargetDesc.h"
  15 #include "ARMMCAsmInfo.h"
  16 #include "ARMBaseInfo.h"
  17 #include "InstPrinter/ARMInstPrinter.h"
  18 #include "llvm/MC/MCInstrInfo.h"
  19 #include "llvm/MC/MCRegisterInfo.h"
  20 #include "llvm/MC/MCStreamer.h"
  21 #include "llvm/MC/MCSubtargetInfo.h"
  22 #include "llvm/Target/TargetRegistry.h"
  23 #include "llvm/Support/ErrorHandling.h"
  24
  25 #define GET_REGINFO_MC_DESC
  26 #include "ARMGenRegisterInfo.inc"
  27
  28 #define GET_INSTRINFO_MC_DESC
  29 #include "ARMGenInstrInfo.inc"
  30
  31 #define GET_SUBTARGETINFO_MC_DESC
  32 #include "ARMGenSubtargetInfo.inc"
  33
  34 using namespace llvm;
  35
  36 std::string ARM_MC::ParseARMTriple(StringRef TT) {
  37   // Set the boolean corresponding to the current target triple, or the default
  38   // if one cannot be determined, to true.
  39   unsigned Len = TT.size();
  40   unsigned Idx = 0;
  41
  42   // FIXME: Enahnce Triple helper class to extract ARM version.
  43   bool isThumb = false;
  44   if (Len >= 5 && TT.substr(0, 4) == "armv")
  45     Idx = 4;
  46   else if (Len >= 6 && TT.substr(0, 5) == "thumb") {
  47     isThumb = true;
  48     if (Len >= 7 && TT[5] == 'v')
  49       Idx = 6;
  50   }
  51
  52   std::string ARMArchFeature;
  53   if (Idx) {
  54     unsigned SubVer = TT[Idx];
  55     if (SubVer >= '7' && SubVer <= '9') {
  56       if (Len >= Idx+2 && TT[Idx+1] == 'm') {
  57         // v7m: FeatureNoARM, FeatureDB, FeatureHWDiv
  58         ARMArchFeature = "+v7,+noarm,+db,+hwdiv";
  59       } else if (Len >= Idx+3 && TT[Idx+1] == 'e'&& TT[Idx+2] == 'm') {
  60         // v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSPThumb2,
  61         //       FeatureT2XtPk
  62         ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+t2dsp,t2xtpk";
  63       } else
  64         // v7a: FeatureNEON, FeatureDB, FeatureDSPThumb2
  65         ARMArchFeature = "+v7,+neon,+db,+t2dsp";
  66     } else if (SubVer == '6') {
  67       if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2')
  68         ARMArchFeature = "+v6t2";
  69       else
  70         ARMArchFeature = "+v6";
  71     } else if (SubVer == '5') {
  72       if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e')
  73         ARMArchFeature = "+v5te";
  74       else
  75         ARMArchFeature = "+v5t";
  76     } else if (SubVer == '4' && Len >= Idx+2 && TT[Idx+1] == 't')
  77       ARMArchFeature = "+v4t";
  78   }
  79
  80   if (isThumb) {
  81     if (ARMArchFeature.empty())
  82       ARMArchFeature = "+thumb-mode";
  83     else
  84       ARMArchFeature += ",+thumb-mode";
  85   }
  86
  87   return ARMArchFeature;
  88 }
  89
  90 MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
  91                                                   StringRef FS) {
  92   std::string ArchFS = ARM_MC::ParseARMTriple(TT);
  93   if (!FS.empty()) {
  94     if (!ArchFS.empty())
  95       ArchFS = ArchFS + "," + FS.str();
  96     else
  97       ArchFS = FS;
  98   }
  99
 100   MCSubtargetInfo *X = new MCSubtargetInfo();
 101   InitARMMCSubtargetInfo(X, TT, CPU, ArchFS);
 102   return X;
 103 }
 104
 105 static MCInstrInfo *createARMMCInstrInfo() {
 106   MCInstrInfo *X = new MCInstrInfo();
 107   InitARMMCInstrInfo(X);
 108   return X;
 109 }
 110
 111 static MCRegisterInfo *createARMMCRegisterInfo(StringRef Triple) {
 112   MCRegisterInfo *X = new MCRegisterInfo();
 113   InitARMMCRegisterInfo(X, ARM::LR);
 114   return X;
 115 }
 116
 117 static MCAsmInfo *createARMMCAsmInfo(const Target &T, StringRef TT) {
 118   Triple TheTriple(TT);
 119
 120   if (TheTriple.isOSDarwin())
 121     return new ARMMCAsmInfoDarwin();
 122
 123   return new ARMELFMCAsmInfo();
 124 }
 125
 126 static MCCodeGenInfo *createARMMCCodeGenInfo(StringRef TT, Reloc::Model RM,
 127                                              CodeModel::Model CM) {
 128   MCCodeGenInfo *X = new MCCodeGenInfo();
 129   if (RM == Reloc::Default)
 130     RM = Reloc::DynamicNoPIC;
 131   X->InitMCCodeGenInfo(RM, CM);
 132   return X;
 133 }
 134
 135 // This is duplicated code. Refactor this.
 136 static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
 137                                     MCContext &Ctx, MCAsmBackend &MAB,
 138                                     raw_ostream &OS,
 139                                     MCCodeEmitter *Emitter,
 140                                     bool RelaxAll,
 141                                     bool NoExecStack) {
 142   Triple TheTriple(TT);
 143
 144   if (TheTriple.isOSDarwin())
 145     return createMachOStreamer(Ctx, MAB, OS, Emitter, RelaxAll);
 146
 147   if (TheTriple.isOSWindows()) {
 148     llvm_unreachable("ARM does not support Windows COFF format");
 149     return NULL;
 150   }
 151
 152   return createELFStreamer(Ctx, MAB, OS, Emitter, RelaxAll, NoExecStack);
 153 }
 154
 155 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
 156                                              unsigned SyntaxVariant,
 157                                              const MCAsmInfo &MAI) {
 158   if (SyntaxVariant == 0)
 159     return new ARMInstPrinter(MAI);
 160   return 0;
 161 }
 162
 163 namespace {
 164
 165 class ARMMCInstrAnalysis : public MCInstrAnalysis {
 166 public:
 167   ARMMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
 168
 169   virtual bool isUnconditionalBranch(const MCInst &Inst) const {
 170     // BCCs with the "always" predicate are unconditional branches.
 171     if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
 172       return true;
 173     return MCInstrAnalysis::isUnconditionalBranch(Inst);
 174   }
 175
 176   virtual bool isConditionalBranch(const MCInst &Inst) const {
 177     // BCCs with the "always" predicate are unconditional branches.
 178     if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
 179       return false;
 180     return MCInstrAnalysis::isConditionalBranch(Inst);
 181   }
 182
 183   uint64_t evaluateBranch(const MCInst &Inst, uint64_t Addr,
 184                           uint64_t Size) const {
 185     // We only handle PCRel branches for now.
 186     if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL)
 187       return -1ULL;
 188
 189     int64_t Imm = Inst.getOperand(0).getImm();
 190     // FIXME: This is not right for thumb.
 191     return Addr+Imm+8; // In ARM mode the PC is always off by 8 bytes.
 192   }
 193 };
 194
 195 }
 196
 197 static MCInstrAnalysis *createARMMCInstrAnalysis(const MCInstrInfo *Info) {
 198   return new ARMMCInstrAnalysis(Info);
 199 }
 200
 201 // Force static initialization.
 202 extern "C" void LLVMInitializeARMTargetMC() {
 203   // Register the MC asm info.
 204   RegisterMCAsmInfoFn A(TheARMTarget, createARMMCAsmInfo);
 205   RegisterMCAsmInfoFn B(TheThumbTarget, createARMMCAsmInfo);
 206
 207   // Register the MC codegen info.
 208   TargetRegistry::RegisterMCCodeGenInfo(TheARMTarget, createARMMCCodeGenInfo);
 209   TargetRegistry::RegisterMCCodeGenInfo(TheThumbTarget, createARMMCCodeGenInfo);
 210
 211   // Register the MC instruction info.
 212   TargetRegistry::RegisterMCInstrInfo(TheARMTarget, createARMMCInstrInfo);
 213   TargetRegistry::RegisterMCInstrInfo(TheThumbTarget, createARMMCInstrInfo);
 214
 215   // Register the MC register info.
 216   TargetRegistry::RegisterMCRegInfo(TheARMTarget, createARMMCRegisterInfo);
 217   TargetRegistry::RegisterMCRegInfo(TheThumbTarget, createARMMCRegisterInfo);
 218
 219   TargetRegistry::RegisterMCInstrAnalysis(TheARMTarget,
 220                                           createARMMCInstrAnalysis);
 221   TargetRegistry::RegisterMCInstrAnalysis(TheThumbTarget,
 222                                           createARMMCInstrAnalysis);
 223
 224   // Register the MC subtarget info.
 225   TargetRegistry::RegisterMCSubtargetInfo(TheARMTarget,
 226                                           ARM_MC::createARMMCSubtargetInfo);
 227   TargetRegistry::RegisterMCSubtargetInfo(TheThumbTarget,
 228                                           ARM_MC::createARMMCSubtargetInfo);
 229
 230   // Register the MC Code Emitter
 231   TargetRegistry::RegisterMCCodeEmitter(TheARMTarget, createARMMCCodeEmitter);
 232   TargetRegistry::RegisterMCCodeEmitter(TheThumbTarget, createARMMCCodeEmitter);
 233
 234   // Register the asm backend.
 235   TargetRegistry::RegisterMCAsmBackend(TheARMTarget, createARMAsmBackend);
 236   TargetRegistry::RegisterMCAsmBackend(TheThumbTarget, createARMAsmBackend);
 237
 238   // Register the object streamer.
 239   TargetRegistry::RegisterMCObjectStreamer(TheARMTarget, createMCStreamer);
 240   TargetRegistry::RegisterMCObjectStreamer(TheThumbTarget, createMCStreamer);
 241
 242   // Register the MCInstPrinter.
 243   TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
 244   TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);
 245 }