1 //===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARMMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mccodeemitter"
15 #include "MCTargetDesc/ARMMCTargetDesc.h"
16 #include "MCTargetDesc/ARMAddressingModes.h"
17 #include "MCTargetDesc/ARMBaseInfo.h"
18 #include "MCTargetDesc/ARMFixupKinds.h"
19 #include "MCTargetDesc/ARMMCExpr.h"
20 #include "llvm/ADT/APFloat.h"
21 #include "llvm/ADT/Statistic.h"
22 #include "llvm/MC/MCCodeEmitter.h"
23 #include "llvm/MC/MCContext.h"
24 #include "llvm/MC/MCExpr.h"
25 #include "llvm/MC/MCInst.h"
26 #include "llvm/MC/MCInstrInfo.h"
27 #include "llvm/MC/MCRegisterInfo.h"
28 #include "llvm/MC/MCSubtargetInfo.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/raw_ostream.h"
34 STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
35 STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");
38 class ARMMCCodeEmitter : public MCCodeEmitter {
39 ARMMCCodeEmitter(const ARMMCCodeEmitter &) LLVM_DELETED_FUNCTION;
40 void operator=(const ARMMCCodeEmitter &) LLVM_DELETED_FUNCTION;
41 const MCInstrInfo &MCII;
45 ARMMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx)
46 : MCII(mcii), CTX(ctx) {
49 ~ARMMCCodeEmitter() {}
51 bool isThumb(const MCSubtargetInfo &STI) const {
52 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
54 bool isThumb2(const MCSubtargetInfo &STI) const {
55 return isThumb(STI) && (STI.getFeatureBits() & ARM::FeatureThumb2) != 0;
57 bool isTargetMachO(const MCSubtargetInfo &STI) const {
58 Triple TT(STI.getTargetTriple());
59 return TT.isOSBinFormatMachO();
62 unsigned getMachineSoImmOpValue(unsigned SoImm) const;
64 // getBinaryCodeForInstr - TableGen'erated function for getting the
65 // binary encoding for an instruction.
66 uint64_t getBinaryCodeForInstr(const MCInst &MI,
67 SmallVectorImpl<MCFixup> &Fixups,
68 const MCSubtargetInfo &STI) const;
70 /// getMachineOpValue - Return binary encoding of operand. If the machine
71 /// operand requires relocation, record the relocation and return zero.
72 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
73 SmallVectorImpl<MCFixup> &Fixups,
74 const MCSubtargetInfo &STI) const;
76 /// getHiLo16ImmOpValue - Return the encoding for the hi / low 16-bit of
77 /// the specified operand. This is used for operands with :lower16: and
78 /// :upper16: prefixes.
79 uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
80 SmallVectorImpl<MCFixup> &Fixups,
81 const MCSubtargetInfo &STI) const;
83 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
84 unsigned &Reg, unsigned &Imm,
85 SmallVectorImpl<MCFixup> &Fixups,
86 const MCSubtargetInfo &STI) const;
88 /// getThumbBLTargetOpValue - Return encoding info for Thumb immediate
90 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
91 SmallVectorImpl<MCFixup> &Fixups,
92 const MCSubtargetInfo &STI) const;
94 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
95 /// BLX branch target.
96 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
97 SmallVectorImpl<MCFixup> &Fixups,
98 const MCSubtargetInfo &STI) const;
100 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
101 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
102 SmallVectorImpl<MCFixup> &Fixups,
103 const MCSubtargetInfo &STI) const;
105 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
106 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
107 SmallVectorImpl<MCFixup> &Fixups,
108 const MCSubtargetInfo &STI) const;
110 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
111 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
112 SmallVectorImpl<MCFixup> &Fixups,
113 const MCSubtargetInfo &STI) const;
115 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
117 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
118 SmallVectorImpl<MCFixup> &Fixups,
119 const MCSubtargetInfo &STI) const;
121 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
122 /// immediate Thumb2 direct branch target.
123 uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
124 SmallVectorImpl<MCFixup> &Fixups,
125 const MCSubtargetInfo &STI) const;
127 /// getARMBranchTargetOpValue - Return encoding info for 24-bit immediate
129 uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
130 SmallVectorImpl<MCFixup> &Fixups,
131 const MCSubtargetInfo &STI) const;
132 uint32_t getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
133 SmallVectorImpl<MCFixup> &Fixups,
134 const MCSubtargetInfo &STI) const;
135 uint32_t getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
136 SmallVectorImpl<MCFixup> &Fixups,
137 const MCSubtargetInfo &STI) const;
139 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate
140 /// ADR label target.
141 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
142 SmallVectorImpl<MCFixup> &Fixups,
143 const MCSubtargetInfo &STI) const;
144 uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
145 SmallVectorImpl<MCFixup> &Fixups,
146 const MCSubtargetInfo &STI) const;
147 uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
148 SmallVectorImpl<MCFixup> &Fixups,
149 const MCSubtargetInfo &STI) const;
152 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
154 uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
155 SmallVectorImpl<MCFixup> &Fixups,
156 const MCSubtargetInfo &STI) const;
158 /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand.
159 uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
160 SmallVectorImpl<MCFixup> &Fixups,
161 const MCSubtargetInfo &STI) const;
163 /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2'
165 uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
166 SmallVectorImpl<MCFixup> &Fixups,
167 const MCSubtargetInfo &STI) const;
169 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 'reg + imm8<<2'
171 uint32_t getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
172 SmallVectorImpl<MCFixup> &Fixups,
173 const MCSubtargetInfo &STI) const;
175 /// getT2Imm8s4OpValue - Return encoding info for '+/- imm8<<2'
177 uint32_t getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx,
178 SmallVectorImpl<MCFixup> &Fixups,
179 const MCSubtargetInfo &STI) const;
182 /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
183 /// operand as needed by load/store instructions.
184 uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
185 SmallVectorImpl<MCFixup> &Fixups,
186 const MCSubtargetInfo &STI) const;
188 /// getLdStmModeOpValue - Return encoding for load/store multiple mode.
189 uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
190 SmallVectorImpl<MCFixup> &Fixups,
191 const MCSubtargetInfo &STI) const {
192 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
194 default: llvm_unreachable("Unknown addressing sub-mode!");
195 case ARM_AM::da: return 0;
196 case ARM_AM::ia: return 1;
197 case ARM_AM::db: return 2;
198 case ARM_AM::ib: return 3;
201 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
203 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
205 case ARM_AM::no_shift:
206 case ARM_AM::lsl: return 0;
207 case ARM_AM::lsr: return 1;
208 case ARM_AM::asr: return 2;
210 case ARM_AM::rrx: return 3;
212 llvm_unreachable("Invalid ShiftOpc!");
215 /// getAddrMode2OpValue - Return encoding for addrmode2 operands.
216 uint32_t getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
217 SmallVectorImpl<MCFixup> &Fixups,
218 const MCSubtargetInfo &STI) const;
220 /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands.
221 uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
222 SmallVectorImpl<MCFixup> &Fixups,
223 const MCSubtargetInfo &STI) const;
225 /// getPostIdxRegOpValue - Return encoding for postidx_reg operands.
226 uint32_t getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
227 SmallVectorImpl<MCFixup> &Fixups,
228 const MCSubtargetInfo &STI) const;
230 /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands.
231 uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
232 SmallVectorImpl<MCFixup> &Fixups,
233 const MCSubtargetInfo &STI) const;
235 /// getAddrMode3OpValue - Return encoding for addrmode3 operands.
236 uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
237 SmallVectorImpl<MCFixup> &Fixups,
238 const MCSubtargetInfo &STI) const;
240 /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12'
242 uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
243 SmallVectorImpl<MCFixup> &Fixups,
244 const MCSubtargetInfo &STI) const;
246 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
247 uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
248 SmallVectorImpl<MCFixup> &Fixups,
249 const MCSubtargetInfo &STI) const;
251 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
252 uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
253 SmallVectorImpl<MCFixup> &Fixups,
254 const MCSubtargetInfo &STI) const;
256 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand.
257 uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
258 SmallVectorImpl<MCFixup> &Fixups,
259 const MCSubtargetInfo &STI) const;
261 /// getCCOutOpValue - Return encoding of the 's' bit.
262 unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
263 SmallVectorImpl<MCFixup> &Fixups,
264 const MCSubtargetInfo &STI) const {
265 // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
267 return MI.getOperand(Op).getReg() == ARM::CPSR;
270 /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value.
271 unsigned getSOImmOpValue(const MCInst &MI, unsigned Op,
272 SmallVectorImpl<MCFixup> &Fixups,
273 const MCSubtargetInfo &STI) const {
275 const MCOperand &MO = MI.getOperand(Op);
277 // We expect MO to be an immediate or an expression,
278 // if it is an immediate - that's fine, just encode the value.
279 // Otherwise - create a Fixup.
281 const MCExpr *Expr = MO.getExpr();
282 // In instruction code this value always encoded as lowest 12 bits,
283 // so we don't have to perform any specific adjustments and
284 // can use just 2-bytes fixup.
285 MCFixupKind Kind = MCFixupKind(FK_Data_2);
286 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
290 unsigned SoImm = MO.getImm();
291 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
292 assert(SoImmVal != -1 && "Not a valid so_imm value!");
294 // Encode rotate_imm.
295 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
296 << ARMII::SoRotImmShift;
299 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
303 /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
304 unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
305 SmallVectorImpl<MCFixup> &Fixups,
306 const MCSubtargetInfo &STI) const {
307 unsigned SoImm = MI.getOperand(Op).getImm();
308 unsigned Encoded = ARM_AM::getT2SOImmVal(SoImm);
309 assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
313 unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
314 SmallVectorImpl<MCFixup> &Fixups,
315 const MCSubtargetInfo &STI) const;
316 unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
317 SmallVectorImpl<MCFixup> &Fixups,
318 const MCSubtargetInfo &STI) const;
319 unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
320 SmallVectorImpl<MCFixup> &Fixups,
321 const MCSubtargetInfo &STI) const;
322 unsigned getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
323 SmallVectorImpl<MCFixup> &Fixups,
324 const MCSubtargetInfo &STI) const;
326 /// getSORegOpValue - Return an encoded so_reg shifted register value.
327 unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op,
328 SmallVectorImpl<MCFixup> &Fixups,
329 const MCSubtargetInfo &STI) const;
330 unsigned getSORegImmOpValue(const MCInst &MI, unsigned Op,
331 SmallVectorImpl<MCFixup> &Fixups,
332 const MCSubtargetInfo &STI) const;
333 unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
334 SmallVectorImpl<MCFixup> &Fixups,
335 const MCSubtargetInfo &STI) const;
337 unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
338 SmallVectorImpl<MCFixup> &Fixups,
339 const MCSubtargetInfo &STI) const {
340 return 64 - MI.getOperand(Op).getImm();
343 unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
344 SmallVectorImpl<MCFixup> &Fixups,
345 const MCSubtargetInfo &STI) const;
347 unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
348 SmallVectorImpl<MCFixup> &Fixups,
349 const MCSubtargetInfo &STI) const;
350 unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
351 SmallVectorImpl<MCFixup> &Fixups,
352 const MCSubtargetInfo &STI) const;
353 unsigned getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
354 SmallVectorImpl<MCFixup> &Fixups,
355 const MCSubtargetInfo &STI) const;
356 unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
357 SmallVectorImpl<MCFixup> &Fixups,
358 const MCSubtargetInfo &STI) const;
359 unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
360 SmallVectorImpl<MCFixup> &Fixups,
361 const MCSubtargetInfo &STI) const;
363 unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op,
364 SmallVectorImpl<MCFixup> &Fixups,
365 const MCSubtargetInfo &STI) const;
366 unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op,
367 SmallVectorImpl<MCFixup> &Fixups,
368 const MCSubtargetInfo &STI) const;
369 unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op,
370 SmallVectorImpl<MCFixup> &Fixups,
371 const MCSubtargetInfo &STI) const;
372 unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op,
373 SmallVectorImpl<MCFixup> &Fixups,
374 const MCSubtargetInfo &STI) const;
376 unsigned getThumbSRImmOpValue(const MCInst &MI, unsigned Op,
377 SmallVectorImpl<MCFixup> &Fixups,
378 const MCSubtargetInfo &STI) const;
380 unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
381 unsigned EncodedValue,
382 const MCSubtargetInfo &STI) const;
383 unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI,
384 unsigned EncodedValue,
385 const MCSubtargetInfo &STI) const;
386 unsigned NEONThumb2DupPostEncoder(const MCInst &MI,
387 unsigned EncodedValue,
388 const MCSubtargetInfo &STI) const;
389 unsigned NEONThumb2V8PostEncoder(const MCInst &MI,
390 unsigned EncodedValue,
391 const MCSubtargetInfo &STI) const;
393 unsigned VFPThumb2PostEncoder(const MCInst &MI,
394 unsigned EncodedValue,
395 const MCSubtargetInfo &STI) const;
397 void EmitByte(unsigned char C, raw_ostream &OS) const {
401 void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
402 // Output the constant in little endian byte order.
403 for (unsigned i = 0; i != Size; ++i) {
404 EmitByte(Val & 255, OS);
409 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
410 SmallVectorImpl<MCFixup> &Fixups,
411 const MCSubtargetInfo &STI) const override;
414 } // end anonymous namespace
416 MCCodeEmitter *llvm::createARMMCCodeEmitter(const MCInstrInfo &MCII,
417 const MCRegisterInfo &MRI,
418 const MCSubtargetInfo &STI,
420 return new ARMMCCodeEmitter(MCII, Ctx);
423 /// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
424 /// instructions, and rewrite them to their Thumb2 form if we are currently in
426 unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
427 unsigned EncodedValue,
428 const MCSubtargetInfo &STI) const {
430 // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved
431 // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are
433 unsigned Bit24 = EncodedValue & 0x01000000;
434 unsigned Bit28 = Bit24 << 4;
435 EncodedValue &= 0xEFFFFFFF;
436 EncodedValue |= Bit28;
437 EncodedValue |= 0x0F000000;
443 /// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store
444 /// instructions, and rewrite them to their Thumb2 form if we are currently in
446 unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI,
447 unsigned EncodedValue,
448 const MCSubtargetInfo &STI) const {
450 EncodedValue &= 0xF0FFFFFF;
451 EncodedValue |= 0x09000000;
457 /// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup
458 /// instructions, and rewrite them to their Thumb2 form if we are currently in
460 unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI,
461 unsigned EncodedValue,
462 const MCSubtargetInfo &STI) const {
464 EncodedValue &= 0x00FFFFFF;
465 EncodedValue |= 0xEE000000;
471 /// Post-process encoded NEON v8 instructions, and rewrite them to Thumb2 form
472 /// if we are in Thumb2.
473 unsigned ARMMCCodeEmitter::NEONThumb2V8PostEncoder(const MCInst &MI,
474 unsigned EncodedValue,
475 const MCSubtargetInfo &STI) const {
477 EncodedValue |= 0xC000000; // Set bits 27-26
483 /// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite
484 /// them to their Thumb2 form if we are currently in Thumb2 mode.
485 unsigned ARMMCCodeEmitter::
486 VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue,
487 const MCSubtargetInfo &STI) const {
489 EncodedValue &= 0x0FFFFFFF;
490 EncodedValue |= 0xE0000000;
495 /// getMachineOpValue - Return binary encoding of operand. If the machine
496 /// operand requires relocation, record the relocation and return zero.
497 unsigned ARMMCCodeEmitter::
498 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
499 SmallVectorImpl<MCFixup> &Fixups,
500 const MCSubtargetInfo &STI) const {
502 unsigned Reg = MO.getReg();
503 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
505 // Q registers are encoded as 2x their register number.
509 case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3:
510 case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7:
511 case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11:
512 case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
515 } else if (MO.isImm()) {
516 return static_cast<unsigned>(MO.getImm());
517 } else if (MO.isFPImm()) {
518 return static_cast<unsigned>(APFloat(MO.getFPImm())
519 .bitcastToAPInt().getHiBits(32).getLimitedValue());
522 llvm_unreachable("Unable to encode MCOperand!");
525 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
526 bool ARMMCCodeEmitter::
527 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
528 unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups,
529 const MCSubtargetInfo &STI) const {
530 const MCOperand &MO = MI.getOperand(OpIdx);
531 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
533 Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
535 int32_t SImm = MO1.getImm();
538 // Special value for #-0
539 if (SImm == INT32_MIN) {
544 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
554 /// getBranchTargetOpValue - Helper function to get the branch target operand,
555 /// which is either an immediate or requires a fixup.
556 static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
558 SmallVectorImpl<MCFixup> &Fixups,
559 const MCSubtargetInfo &STI) {
560 const MCOperand &MO = MI.getOperand(OpIdx);
562 // If the destination is an immediate, we have nothing to do.
563 if (MO.isImm()) return MO.getImm();
564 assert(MO.isExpr() && "Unexpected branch target type!");
565 const MCExpr *Expr = MO.getExpr();
566 MCFixupKind Kind = MCFixupKind(FixupKind);
567 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
569 // All of the information is in the fixup.
573 // Thumb BL and BLX use a strange offset encoding where bits 22 and 21 are
574 // determined by negating them and XOR'ing them with bit 23.
575 static int32_t encodeThumbBLOffset(int32_t offset) {
577 uint32_t S = (offset & 0x800000) >> 23;
578 uint32_t J1 = (offset & 0x400000) >> 22;
579 uint32_t J2 = (offset & 0x200000) >> 21;
592 /// getThumbBLTargetOpValue - Return encoding info for immediate branch target.
593 uint32_t ARMMCCodeEmitter::
594 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
595 SmallVectorImpl<MCFixup> &Fixups,
596 const MCSubtargetInfo &STI) const {
597 const MCOperand MO = MI.getOperand(OpIdx);
599 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl,
601 return encodeThumbBLOffset(MO.getImm());
604 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
605 /// BLX branch target.
606 uint32_t ARMMCCodeEmitter::
607 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
608 SmallVectorImpl<MCFixup> &Fixups,
609 const MCSubtargetInfo &STI) const {
610 const MCOperand MO = MI.getOperand(OpIdx);
612 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx,
614 return encodeThumbBLOffset(MO.getImm());
617 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
618 uint32_t ARMMCCodeEmitter::
619 getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
620 SmallVectorImpl<MCFixup> &Fixups,
621 const MCSubtargetInfo &STI) const {
622 const MCOperand MO = MI.getOperand(OpIdx);
624 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br,
626 return (MO.getImm() >> 1);
629 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
630 uint32_t ARMMCCodeEmitter::
631 getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
632 SmallVectorImpl<MCFixup> &Fixups,
633 const MCSubtargetInfo &STI) const {
634 const MCOperand MO = MI.getOperand(OpIdx);
636 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc,
638 return (MO.getImm() >> 1);
641 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
642 uint32_t ARMMCCodeEmitter::
643 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
644 SmallVectorImpl<MCFixup> &Fixups,
645 const MCSubtargetInfo &STI) const {
646 const MCOperand MO = MI.getOperand(OpIdx);
648 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups, STI);
649 return (MO.getImm() >> 1);
652 /// Return true if this branch has a non-always predication
653 static bool HasConditionalBranch(const MCInst &MI) {
654 int NumOp = MI.getNumOperands();
656 for (int i = 0; i < NumOp-1; ++i) {
657 const MCOperand &MCOp1 = MI.getOperand(i);
658 const MCOperand &MCOp2 = MI.getOperand(i + 1);
659 if (MCOp1.isImm() && MCOp2.isReg() &&
660 (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) {
661 if (ARMCC::CondCodes(MCOp1.getImm()) != ARMCC::AL)
669 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
671 uint32_t ARMMCCodeEmitter::
672 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
673 SmallVectorImpl<MCFixup> &Fixups,
674 const MCSubtargetInfo &STI) const {
675 // FIXME: This really, really shouldn't use TargetMachine. We don't want
676 // coupling between MC and TM anywhere we can help it.
679 ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups, STI);
680 return getARMBranchTargetOpValue(MI, OpIdx, Fixups, STI);
683 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
685 uint32_t ARMMCCodeEmitter::
686 getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
687 SmallVectorImpl<MCFixup> &Fixups,
688 const MCSubtargetInfo &STI) const {
689 const MCOperand MO = MI.getOperand(OpIdx);
691 if (HasConditionalBranch(MI))
692 return ::getBranchTargetOpValue(MI, OpIdx,
693 ARM::fixup_arm_condbranch, Fixups, STI);
694 return ::getBranchTargetOpValue(MI, OpIdx,
695 ARM::fixup_arm_uncondbranch, Fixups, STI);
698 return MO.getImm() >> 2;
701 uint32_t ARMMCCodeEmitter::
702 getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
703 SmallVectorImpl<MCFixup> &Fixups,
704 const MCSubtargetInfo &STI) const {
705 const MCOperand MO = MI.getOperand(OpIdx);
707 if (HasConditionalBranch(MI))
708 return ::getBranchTargetOpValue(MI, OpIdx,
709 ARM::fixup_arm_condbl, Fixups, STI);
710 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_uncondbl, Fixups, STI);
713 return MO.getImm() >> 2;
716 uint32_t ARMMCCodeEmitter::
717 getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
718 SmallVectorImpl<MCFixup> &Fixups,
719 const MCSubtargetInfo &STI) const {
720 const MCOperand MO = MI.getOperand(OpIdx);
722 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_blx, Fixups, STI);
724 return MO.getImm() >> 1;
727 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
728 /// immediate branch target.
729 uint32_t ARMMCCodeEmitter::
730 getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
731 SmallVectorImpl<MCFixup> &Fixups,
732 const MCSubtargetInfo &STI) const {
734 const MCOperand MO = MI.getOperand(OpIdx);
737 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_uncondbranch, Fixups, STI);
739 Val = MO.getImm() >> 1;
741 bool I = (Val & 0x800000);
742 bool J1 = (Val & 0x400000);
743 bool J2 = (Val & 0x200000);
757 /// getAdrLabelOpValue - Return encoding info for 12-bit shifted-immediate
758 /// ADR label target.
759 uint32_t ARMMCCodeEmitter::
760 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
761 SmallVectorImpl<MCFixup> &Fixups,
762 const MCSubtargetInfo &STI) const {
763 const MCOperand MO = MI.getOperand(OpIdx);
765 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12,
767 int64_t offset = MO.getImm();
768 uint32_t Val = 0x2000;
771 if (offset == INT32_MIN) {
774 } else if (offset < 0) {
777 SoImmVal = ARM_AM::getSOImmVal(offset);
781 SoImmVal = ARM_AM::getSOImmVal(offset);
784 SoImmVal = ARM_AM::getSOImmVal(offset);
788 SoImmVal = ARM_AM::getSOImmVal(offset);
792 assert(SoImmVal != -1 && "Not a valid so_imm value!");
798 /// getT2AdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
800 uint32_t ARMMCCodeEmitter::
801 getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
802 SmallVectorImpl<MCFixup> &Fixups,
803 const MCSubtargetInfo &STI) const {
804 const MCOperand MO = MI.getOperand(OpIdx);
806 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12,
808 int32_t Val = MO.getImm();
809 if (Val == INT32_MIN)
818 /// getThumbAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label
820 uint32_t ARMMCCodeEmitter::
821 getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
822 SmallVectorImpl<MCFixup> &Fixups,
823 const MCSubtargetInfo &STI) const {
824 const MCOperand MO = MI.getOperand(OpIdx);
826 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10,
831 /// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg'
833 uint32_t ARMMCCodeEmitter::
834 getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
835 SmallVectorImpl<MCFixup> &,
836 const MCSubtargetInfo &STI) const {
840 const MCOperand &MO1 = MI.getOperand(OpIdx);
841 const MCOperand &MO2 = MI.getOperand(OpIdx + 1);
842 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
843 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO2.getReg());
844 return (Rm << 3) | Rn;
847 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
848 uint32_t ARMMCCodeEmitter::
849 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
850 SmallVectorImpl<MCFixup> &Fixups,
851 const MCSubtargetInfo &STI) const {
853 // {12} = (U)nsigned (add == '1', sub == '0')
857 // If The first operand isn't a register, we have a label reference.
858 const MCOperand &MO = MI.getOperand(OpIdx);
860 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
864 const MCExpr *Expr = MO.getExpr();
865 isAdd = false ; // 'U' bit is set as part of the fixup.
869 Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12);
871 Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12);
872 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
874 ++MCNumCPRelocations;
877 int32_t Offset = MO.getImm();
878 if (Offset == INT32_MIN) {
881 } else if (Offset < 0) {
888 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups, STI);
890 uint32_t Binary = Imm12 & 0xfff;
891 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
894 Binary |= (Reg << 13);
898 /// getT2Imm8s4OpValue - Return encoding info for
899 /// '+/- imm8<<2' operand.
900 uint32_t ARMMCCodeEmitter::
901 getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx,
902 SmallVectorImpl<MCFixup> &Fixups,
903 const MCSubtargetInfo &STI) const {
904 // FIXME: The immediate operand should have already been encoded like this
905 // before ever getting here. The encoder method should just need to combine
906 // the MI operands for the register and the offset into a single
907 // representation for the complex operand in the .td file. This isn't just
908 // style, unfortunately. As-is, we can't represent the distinct encoding
911 // {8} = (U)nsigned (add == '1', sub == '0')
913 int32_t Imm8 = MI.getOperand(OpIdx).getImm();
914 bool isAdd = Imm8 >= 0;
916 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
918 Imm8 = -(uint32_t)Imm8;
923 uint32_t Binary = Imm8 & 0xff;
924 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
930 /// getT2AddrModeImm8s4OpValue - Return encoding info for
931 /// 'reg +/- imm8<<2' operand.
932 uint32_t ARMMCCodeEmitter::
933 getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
934 SmallVectorImpl<MCFixup> &Fixups,
935 const MCSubtargetInfo &STI) const {
937 // {8} = (U)nsigned (add == '1', sub == '0')
941 // If The first operand isn't a register, we have a label reference.
942 const MCOperand &MO = MI.getOperand(OpIdx);
944 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
946 isAdd = false ; // 'U' bit is set as part of the fixup.
948 assert(MO.isExpr() && "Unexpected machine operand type!");
949 const MCExpr *Expr = MO.getExpr();
950 MCFixupKind Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
951 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
953 ++MCNumCPRelocations;
955 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
957 // FIXME: The immediate operand should have already been encoded like this
958 // before ever getting here. The encoder method should just need to combine
959 // the MI operands for the register and the offset into a single
960 // representation for the complex operand in the .td file. This isn't just
961 // style, unfortunately. As-is, we can't represent the distinct encoding
963 uint32_t Binary = (Imm8 >> 2) & 0xff;
964 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
967 Binary |= (Reg << 9);
971 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for
972 /// 'reg + imm8<<2' operand.
973 uint32_t ARMMCCodeEmitter::
974 getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
975 SmallVectorImpl<MCFixup> &Fixups,
976 const MCSubtargetInfo &STI) const {
979 const MCOperand &MO = MI.getOperand(OpIdx);
980 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
981 unsigned Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
982 unsigned Imm8 = MO1.getImm();
983 return (Reg << 8) | Imm8;
986 // FIXME: This routine assumes that a binary
987 // expression will always result in a PCRel expression
988 // In reality, its only true if one or more subexpressions
989 // is itself a PCRel (i.e. "." in asm or some other pcrel construct)
990 // but this is good enough for now.
991 static bool EvaluateAsPCRel(const MCExpr *Expr) {
992 switch (Expr->getKind()) {
993 default: llvm_unreachable("Unexpected expression type");
994 case MCExpr::SymbolRef: return false;
995 case MCExpr::Binary: return true;
1000 ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
1001 SmallVectorImpl<MCFixup> &Fixups,
1002 const MCSubtargetInfo &STI) const {
1003 // {20-16} = imm{15-12}
1004 // {11-0} = imm{11-0}
1005 const MCOperand &MO = MI.getOperand(OpIdx);
1007 // Hi / lo 16 bits already extracted during earlier passes.
1008 return static_cast<unsigned>(MO.getImm());
1010 // Handle :upper16: and :lower16: assembly prefixes.
1011 const MCExpr *E = MO.getExpr();
1013 if (E->getKind() == MCExpr::Target) {
1014 const ARMMCExpr *ARM16Expr = cast<ARMMCExpr>(E);
1015 E = ARM16Expr->getSubExpr();
1017 if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(E)) {
1018 const int64_t Value = MCE->getValue();
1019 if (Value > UINT32_MAX)
1020 report_fatal_error("constant value truncated (limited to 32-bit)");
1022 switch (ARM16Expr->getKind()) {
1023 case ARMMCExpr::VK_ARM_HI16:
1024 return (int32_t(Value) & 0xffff0000) >> 16;
1025 case ARMMCExpr::VK_ARM_LO16:
1026 return (int32_t(Value) & 0x0000ffff);
1027 default: llvm_unreachable("Unsupported ARMFixup");
1031 switch (ARM16Expr->getKind()) {
1032 default: llvm_unreachable("Unsupported ARMFixup");
1033 case ARMMCExpr::VK_ARM_HI16:
1034 if (!isTargetMachO(STI) && EvaluateAsPCRel(E))
1035 Kind = MCFixupKind(isThumb2(STI)
1036 ? ARM::fixup_t2_movt_hi16_pcrel
1037 : ARM::fixup_arm_movt_hi16_pcrel);
1039 Kind = MCFixupKind(isThumb2(STI)
1040 ? ARM::fixup_t2_movt_hi16
1041 : ARM::fixup_arm_movt_hi16);
1043 case ARMMCExpr::VK_ARM_LO16:
1044 if (!isTargetMachO(STI) && EvaluateAsPCRel(E))
1045 Kind = MCFixupKind(isThumb2(STI)
1046 ? ARM::fixup_t2_movw_lo16_pcrel
1047 : ARM::fixup_arm_movw_lo16_pcrel);
1049 Kind = MCFixupKind(isThumb2(STI)
1050 ? ARM::fixup_t2_movw_lo16
1051 : ARM::fixup_arm_movw_lo16);
1054 Fixups.push_back(MCFixup::Create(0, E, Kind, MI.getLoc()));
1057 // If the expression doesn't have :upper16: or :lower16: on it,
1058 // it's just a plain immediate expression, and those evaluate to
1059 // the lower 16 bits of the expression regardless of whether
1060 // we have a movt or a movw.
1061 if (!isTargetMachO(STI) && EvaluateAsPCRel(E))
1062 Kind = MCFixupKind(isThumb2(STI)
1063 ? ARM::fixup_t2_movw_lo16_pcrel
1064 : ARM::fixup_arm_movw_lo16_pcrel);
1066 Kind = MCFixupKind(isThumb2(STI)
1067 ? ARM::fixup_t2_movw_lo16
1068 : ARM::fixup_arm_movw_lo16);
1069 Fixups.push_back(MCFixup::Create(0, E, Kind, MI.getLoc()));
1073 uint32_t ARMMCCodeEmitter::
1074 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
1075 SmallVectorImpl<MCFixup> &Fixups,
1076 const MCSubtargetInfo &STI) const {
1077 const MCOperand &MO = MI.getOperand(OpIdx);
1078 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1079 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
1080 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1081 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1082 unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
1083 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
1084 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
1085 unsigned SBits = getShiftOp(ShOp);
1087 // While "lsr #32" and "asr #32" exist, they are encoded with a 0 in the shift
1088 // amount. However, it would be an easy mistake to make so check here.
1089 assert((ShImm & ~0x1f) == 0 && "Out of range shift amount");
1098 uint32_t Binary = Rm;
1100 Binary |= SBits << 5;
1101 Binary |= ShImm << 7;
1107 uint32_t ARMMCCodeEmitter::
1108 getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
1109 SmallVectorImpl<MCFixup> &Fixups,
1110 const MCSubtargetInfo &STI) const {
1112 // {13} 1 == imm12, 0 == Rm
1115 const MCOperand &MO = MI.getOperand(OpIdx);
1116 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1117 uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups, STI);
1122 uint32_t ARMMCCodeEmitter::
1123 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
1124 SmallVectorImpl<MCFixup> &Fixups,
1125 const MCSubtargetInfo &STI) const {
1126 // {13} 1 == imm12, 0 == Rm
1129 const MCOperand &MO = MI.getOperand(OpIdx);
1130 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1131 unsigned Imm = MO1.getImm();
1132 bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add;
1133 bool isReg = MO.getReg() != 0;
1134 uint32_t Binary = ARM_AM::getAM2Offset(Imm);
1135 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12
1137 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm);
1138 Binary <<= 7; // Shift amount is bits [11:7]
1139 Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
1140 Binary |= CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); // Rm is bits [3:0]
1142 return Binary | (isAdd << 12) | (isReg << 13);
1145 uint32_t ARMMCCodeEmitter::
1146 getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
1147 SmallVectorImpl<MCFixup> &Fixups,
1148 const MCSubtargetInfo &STI) const {
1151 const MCOperand &MO = MI.getOperand(OpIdx);
1152 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1153 bool isAdd = MO1.getImm() != 0;
1154 return CTX.getRegisterInfo()->getEncodingValue(MO.getReg()) | (isAdd << 4);
1157 uint32_t ARMMCCodeEmitter::
1158 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
1159 SmallVectorImpl<MCFixup> &Fixups,
1160 const MCSubtargetInfo &STI) const {
1161 // {9} 1 == imm8, 0 == Rm
1163 // {7-4} imm7_4/zero
1165 const MCOperand &MO = MI.getOperand(OpIdx);
1166 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1167 unsigned Imm = MO1.getImm();
1168 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
1169 bool isImm = MO.getReg() == 0;
1170 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
1171 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
1173 Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1174 return Imm8 | (isAdd << 8) | (isImm << 9);
1177 uint32_t ARMMCCodeEmitter::
1178 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
1179 SmallVectorImpl<MCFixup> &Fixups,
1180 const MCSubtargetInfo &STI) const {
1181 // {13} 1 == imm8, 0 == Rm
1184 // {7-4} imm7_4/zero
1186 const MCOperand &MO = MI.getOperand(OpIdx);
1187 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1188 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
1190 // If The first operand isn't a register, we have a label reference.
1192 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
1194 assert(MO.isExpr() && "Unexpected machine operand type!");
1195 const MCExpr *Expr = MO.getExpr();
1196 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10_unscaled);
1197 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
1199 ++MCNumCPRelocations;
1200 return (Rn << 9) | (1 << 13);
1202 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1203 unsigned Imm = MO2.getImm();
1204 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
1205 bool isImm = MO1.getReg() == 0;
1206 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
1207 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
1209 Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1210 return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
1213 /// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands.
1214 uint32_t ARMMCCodeEmitter::
1215 getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
1216 SmallVectorImpl<MCFixup> &Fixups,
1217 const MCSubtargetInfo &STI) const {
1220 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1221 assert(MI.getOperand(OpIdx).getReg() == ARM::SP &&
1222 "Unexpected base register!");
1224 // The immediate is already shifted for the implicit zeroes, so no change
1226 return MO1.getImm() & 0xff;
1229 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
1230 uint32_t ARMMCCodeEmitter::
1231 getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
1232 SmallVectorImpl<MCFixup> &Fixups,
1233 const MCSubtargetInfo &STI) const {
1237 const MCOperand &MO = MI.getOperand(OpIdx);
1238 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1239 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1240 unsigned Imm5 = MO1.getImm();
1241 return ((Imm5 & 0x1f) << 3) | Rn;
1244 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
1245 uint32_t ARMMCCodeEmitter::
1246 getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
1247 SmallVectorImpl<MCFixup> &Fixups,
1248 const MCSubtargetInfo &STI) const {
1249 const MCOperand MO = MI.getOperand(OpIdx);
1251 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups, STI);
1252 return (MO.getImm() >> 2);
1255 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm10' operand.
1256 uint32_t ARMMCCodeEmitter::
1257 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
1258 SmallVectorImpl<MCFixup> &Fixups,
1259 const MCSubtargetInfo &STI) const {
1261 // {8} = (U)nsigned (add == '1', sub == '0')
1265 // If The first operand isn't a register, we have a label reference.
1266 const MCOperand &MO = MI.getOperand(OpIdx);
1268 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
1270 isAdd = false; // 'U' bit is handled as part of the fixup.
1272 assert(MO.isExpr() && "Unexpected machine operand type!");
1273 const MCExpr *Expr = MO.getExpr();
1276 Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
1278 Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
1279 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
1281 ++MCNumCPRelocations;
1283 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
1284 isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
1287 uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
1288 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1291 Binary |= (Reg << 9);
1295 unsigned ARMMCCodeEmitter::
1296 getSORegRegOpValue(const MCInst &MI, unsigned OpIdx,
1297 SmallVectorImpl<MCFixup> &Fixups,
1298 const MCSubtargetInfo &STI) const {
1299 // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
1300 // shifted. The second is Rs, the amount to shift by, and the third specifies
1301 // the type of the shift.
1309 const MCOperand &MO = MI.getOperand(OpIdx);
1310 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1311 const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
1312 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
1315 unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1317 // Encode the shift opcode.
1319 unsigned Rs = MO1.getReg();
1321 // Set shift operand (bit[7:4]).
1327 default: llvm_unreachable("Unknown shift opc!");
1328 case ARM_AM::lsl: SBits = 0x1; break;
1329 case ARM_AM::lsr: SBits = 0x3; break;
1330 case ARM_AM::asr: SBits = 0x5; break;
1331 case ARM_AM::ror: SBits = 0x7; break;
1335 Binary |= SBits << 4;
1337 // Encode the shift operation Rs.
1338 // Encode Rs bit[11:8].
1339 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
1340 return Binary | (CTX.getRegisterInfo()->getEncodingValue(Rs) << ARMII::RegRsShift);
1343 unsigned ARMMCCodeEmitter::
1344 getSORegImmOpValue(const MCInst &MI, unsigned OpIdx,
1345 SmallVectorImpl<MCFixup> &Fixups,
1346 const MCSubtargetInfo &STI) const {
1347 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1348 // shifted. The second is the amount to shift by.
1355 const MCOperand &MO = MI.getOperand(OpIdx);
1356 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1357 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1360 unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1362 // Encode the shift opcode.
1365 // Set shift operand (bit[6:4]).
1370 // RRX - 110 and bit[11:8] clear.
1372 default: llvm_unreachable("Unknown shift opc!");
1373 case ARM_AM::lsl: SBits = 0x0; break;
1374 case ARM_AM::lsr: SBits = 0x2; break;
1375 case ARM_AM::asr: SBits = 0x4; break;
1376 case ARM_AM::ror: SBits = 0x6; break;
1382 // Encode shift_imm bit[11:7].
1383 Binary |= SBits << 4;
1384 unsigned Offset = ARM_AM::getSORegOffset(MO1.getImm());
1385 assert(Offset < 32 && "Offset must be in range 0-31!");
1386 return Binary | (Offset << 7);
1390 unsigned ARMMCCodeEmitter::
1391 getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
1392 SmallVectorImpl<MCFixup> &Fixups,
1393 const MCSubtargetInfo &STI) const {
1394 const MCOperand &MO1 = MI.getOperand(OpNum);
1395 const MCOperand &MO2 = MI.getOperand(OpNum+1);
1396 const MCOperand &MO3 = MI.getOperand(OpNum+2);
1398 // Encoded as [Rn, Rm, imm].
1399 // FIXME: Needs fixup support.
1400 unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1402 Value |= CTX.getRegisterInfo()->getEncodingValue(MO2.getReg());
1404 Value |= MO3.getImm();
1409 unsigned ARMMCCodeEmitter::
1410 getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
1411 SmallVectorImpl<MCFixup> &Fixups,
1412 const MCSubtargetInfo &STI) const {
1413 const MCOperand &MO1 = MI.getOperand(OpNum);
1414 const MCOperand &MO2 = MI.getOperand(OpNum+1);
1416 // FIXME: Needs fixup support.
1417 unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1419 // Even though the immediate is 8 bits long, we need 9 bits in order
1420 // to represent the (inverse of the) sign bit.
1422 int32_t tmp = (int32_t)MO2.getImm();
1426 Value |= 256; // Set the ADD bit
1431 unsigned ARMMCCodeEmitter::
1432 getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
1433 SmallVectorImpl<MCFixup> &Fixups,
1434 const MCSubtargetInfo &STI) const {
1435 const MCOperand &MO1 = MI.getOperand(OpNum);
1437 // FIXME: Needs fixup support.
1439 int32_t tmp = (int32_t)MO1.getImm();
1443 Value |= 256; // Set the ADD bit
1448 unsigned ARMMCCodeEmitter::
1449 getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
1450 SmallVectorImpl<MCFixup> &Fixups,
1451 const MCSubtargetInfo &STI) const {
1452 const MCOperand &MO1 = MI.getOperand(OpNum);
1454 // FIXME: Needs fixup support.
1456 int32_t tmp = (int32_t)MO1.getImm();
1460 Value |= 4096; // Set the ADD bit
1461 Value |= tmp & 4095;
1465 unsigned ARMMCCodeEmitter::
1466 getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
1467 SmallVectorImpl<MCFixup> &Fixups,
1468 const MCSubtargetInfo &STI) const {
1469 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1470 // shifted. The second is the amount to shift by.
1477 const MCOperand &MO = MI.getOperand(OpIdx);
1478 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1479 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1482 unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1484 // Encode the shift opcode.
1486 // Set shift operand (bit[6:4]).
1492 default: llvm_unreachable("Unknown shift opc!");
1493 case ARM_AM::lsl: SBits = 0x0; break;
1494 case ARM_AM::lsr: SBits = 0x2; break;
1495 case ARM_AM::asr: SBits = 0x4; break;
1496 case ARM_AM::rrx: // FALLTHROUGH
1497 case ARM_AM::ror: SBits = 0x6; break;
1500 Binary |= SBits << 4;
1501 if (SOpc == ARM_AM::rrx)
1504 // Encode shift_imm bit[11:7].
1505 return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7;
1508 unsigned ARMMCCodeEmitter::
1509 getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
1510 SmallVectorImpl<MCFixup> &Fixups,
1511 const MCSubtargetInfo &STI) const {
1512 // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the
1514 const MCOperand &MO = MI.getOperand(Op);
1515 uint32_t v = ~MO.getImm();
1516 uint32_t lsb = countTrailingZeros(v);
1517 uint32_t msb = (32 - countLeadingZeros (v)) - 1;
1518 assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
1519 return lsb | (msb << 5);
1522 unsigned ARMMCCodeEmitter::
1523 getRegisterListOpValue(const MCInst &MI, unsigned Op,
1524 SmallVectorImpl<MCFixup> &Fixups,
1525 const MCSubtargetInfo &STI) const {
1528 // {7-0} = Number of registers
1531 // {15-0} = Bitfield of GPRs.
1532 unsigned Reg = MI.getOperand(Op).getReg();
1533 bool SPRRegs = ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg);
1534 bool DPRRegs = ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg);
1536 unsigned Binary = 0;
1538 if (SPRRegs || DPRRegs) {
1540 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
1541 unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
1542 Binary |= (RegNo & 0x1f) << 8;
1546 Binary |= NumRegs * 2;
1548 for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
1549 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(MI.getOperand(I).getReg());
1550 Binary |= 1 << RegNo;
1557 /// getAddrMode6AddressOpValue - Encode an addrmode6 register number along
1558 /// with the alignment operand.
1559 unsigned ARMMCCodeEmitter::
1560 getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
1561 SmallVectorImpl<MCFixup> &Fixups,
1562 const MCSubtargetInfo &STI) const {
1563 const MCOperand &Reg = MI.getOperand(Op);
1564 const MCOperand &Imm = MI.getOperand(Op + 1);
1566 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1569 switch (Imm.getImm()) {
1573 case 8: Align = 0x01; break;
1574 case 16: Align = 0x02; break;
1575 case 32: Align = 0x03; break;
1578 return RegNo | (Align << 4);
1581 /// getAddrMode6OneLane32AddressOpValue - Encode an addrmode6 register number
1582 /// along with the alignment operand for use in VST1 and VLD1 with size 32.
1583 unsigned ARMMCCodeEmitter::
1584 getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
1585 SmallVectorImpl<MCFixup> &Fixups,
1586 const MCSubtargetInfo &STI) const {
1587 const MCOperand &Reg = MI.getOperand(Op);
1588 const MCOperand &Imm = MI.getOperand(Op + 1);
1590 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1593 switch (Imm.getImm()) {
1597 case 32: // Default '0' value for invalid alignments of 8, 16, 32 bytes.
1598 case 2: Align = 0x00; break;
1599 case 4: Align = 0x03; break;
1602 return RegNo | (Align << 4);
1606 /// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and
1607 /// alignment operand for use in VLD-dup instructions. This is the same as
1608 /// getAddrMode6AddressOpValue except for the alignment encoding, which is
1609 /// different for VLD4-dup.
1610 unsigned ARMMCCodeEmitter::
1611 getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
1612 SmallVectorImpl<MCFixup> &Fixups,
1613 const MCSubtargetInfo &STI) const {
1614 const MCOperand &Reg = MI.getOperand(Op);
1615 const MCOperand &Imm = MI.getOperand(Op + 1);
1617 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1620 switch (Imm.getImm()) {
1624 case 8: Align = 0x01; break;
1625 case 16: Align = 0x03; break;
1628 return RegNo | (Align << 4);
1631 unsigned ARMMCCodeEmitter::
1632 getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
1633 SmallVectorImpl<MCFixup> &Fixups,
1634 const MCSubtargetInfo &STI) const {
1635 const MCOperand &MO = MI.getOperand(Op);
1636 if (MO.getReg() == 0) return 0x0D;
1637 return CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1640 unsigned ARMMCCodeEmitter::
1641 getShiftRight8Imm(const MCInst &MI, unsigned Op,
1642 SmallVectorImpl<MCFixup> &Fixups,
1643 const MCSubtargetInfo &STI) const {
1644 return 8 - MI.getOperand(Op).getImm();
1647 unsigned ARMMCCodeEmitter::
1648 getShiftRight16Imm(const MCInst &MI, unsigned Op,
1649 SmallVectorImpl<MCFixup> &Fixups,
1650 const MCSubtargetInfo &STI) const {
1651 return 16 - MI.getOperand(Op).getImm();
1654 unsigned ARMMCCodeEmitter::
1655 getShiftRight32Imm(const MCInst &MI, unsigned Op,
1656 SmallVectorImpl<MCFixup> &Fixups,
1657 const MCSubtargetInfo &STI) const {
1658 return 32 - MI.getOperand(Op).getImm();
1661 unsigned ARMMCCodeEmitter::
1662 getShiftRight64Imm(const MCInst &MI, unsigned Op,
1663 SmallVectorImpl<MCFixup> &Fixups,
1664 const MCSubtargetInfo &STI) const {
1665 return 64 - MI.getOperand(Op).getImm();
1668 void ARMMCCodeEmitter::
1669 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
1670 SmallVectorImpl<MCFixup> &Fixups,
1671 const MCSubtargetInfo &STI) const {
1672 // Pseudo instructions don't get encoded.
1673 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
1674 uint64_t TSFlags = Desc.TSFlags;
1675 if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo)
1679 if (Desc.getSize() == 2 || Desc.getSize() == 4)
1680 Size = Desc.getSize();
1682 llvm_unreachable("Unexpected instruction size!");
1684 uint32_t Binary = getBinaryCodeForInstr(MI, Fixups, STI);
1685 // Thumb 32-bit wide instructions need to emit the high order halfword
1687 if (isThumb(STI) && Size == 4) {
1688 EmitConstant(Binary >> 16, 2, OS);
1689 EmitConstant(Binary & 0xffff, 2, OS);
1691 EmitConstant(Binary, Size, OS);
1692 ++MCNumEmitted; // Keep track of the # of mi's emitted.
1695 #include "ARMGenMCCodeEmitter.inc"