1 //===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/ARMMCTargetDesc.h"
11 #include "MCTargetDesc/ARMAddressingModes.h"
12 #include "MCTargetDesc/ARMBaseInfo.h"
13 #include "MCTargetDesc/ARMFixupKinds.h"
14 #include "llvm/ADT/StringSwitch.h"
15 #include "llvm/MC/MCAsmBackend.h"
16 #include "llvm/MC/MCAssembler.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCDirectives.h"
19 #include "llvm/MC/MCELFObjectWriter.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCFixupKindInfo.h"
22 #include "llvm/MC/MCMachObjectWriter.h"
23 #include "llvm/MC/MCObjectWriter.h"
24 #include "llvm/MC/MCSectionELF.h"
25 #include "llvm/MC/MCSectionMachO.h"
26 #include "llvm/MC/MCSubtargetInfo.h"
27 #include "llvm/MC/MCValue.h"
28 #include "llvm/Object/MachOFormat.h"
29 #include "llvm/Support/ELF.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include "llvm/Support/raw_ostream.h"
35 class ARMELFObjectWriter : public MCELFObjectTargetWriter {
37 ARMELFObjectWriter(uint8_t OSABI)
38 : MCELFObjectTargetWriter(/*Is64Bit*/ false, OSABI, ELF::EM_ARM,
39 /*HasRelocationAddend*/ false) {}
42 class ARMAsmBackend : public MCAsmBackend {
43 const MCSubtargetInfo* STI;
44 bool isThumbMode; // Currently emitting Thumb code.
46 ARMAsmBackend(const Target &T, const StringRef TT)
47 : MCAsmBackend(), STI(ARM_MC::createARMMCSubtargetInfo(TT, "", "")),
48 isThumbMode(TT.startswith("thumb")) {}
54 unsigned getNumFixupKinds() const { return ARM::NumTargetFixupKinds; }
57 return (STI->getFeatureBits() & ARM::HasV6T2Ops) != 0;
60 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
61 const static MCFixupKindInfo Infos[ARM::NumTargetFixupKinds] = {
62 // This table *must* be in the order that the fixup_* kinds are defined in
65 // Name Offset (bits) Size (bits) Flags
66 { "fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
67 { "fixup_t2_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
68 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
69 { "fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
70 { "fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
71 { "fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
72 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
73 { "fixup_thumb_adr_pcrel_10",0, 8, MCFixupKindInfo::FKF_IsPCRel |
74 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
75 { "fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
76 { "fixup_t2_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
77 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
78 { "fixup_arm_condbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
79 { "fixup_arm_uncondbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
80 { "fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
81 { "fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
82 { "fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
83 { "fixup_arm_uncondbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
84 { "fixup_arm_condbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
85 { "fixup_arm_blx", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
86 { "fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
87 { "fixup_arm_thumb_blx", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
88 { "fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
89 { "fixup_arm_thumb_cp", 0, 8, MCFixupKindInfo::FKF_IsPCRel |
90 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
91 { "fixup_arm_thumb_bcc", 0, 8, MCFixupKindInfo::FKF_IsPCRel },
92 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16 - 19.
93 { "fixup_arm_movt_hi16", 0, 20, 0 },
94 { "fixup_arm_movw_lo16", 0, 20, 0 },
95 { "fixup_t2_movt_hi16", 0, 20, 0 },
96 { "fixup_t2_movw_lo16", 0, 20, 0 },
97 { "fixup_arm_movt_hi16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
98 { "fixup_arm_movw_lo16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
99 { "fixup_t2_movt_hi16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
100 { "fixup_t2_movw_lo16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
103 if (Kind < FirstTargetFixupKind)
104 return MCAsmBackend::getFixupKindInfo(Kind);
106 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
108 return Infos[Kind - FirstTargetFixupKind];
111 /// processFixupValue - Target hook to process the literal value of a fixup
113 void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout,
114 const MCFixup &Fixup, const MCFragment *DF,
115 MCValue &Target, uint64_t &Value,
119 void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
120 uint64_t Value) const;
122 bool mayNeedRelaxation(const MCInst &Inst) const;
124 bool fixupNeedsRelaxation(const MCFixup &Fixup,
126 const MCRelaxableFragment *DF,
127 const MCAsmLayout &Layout) const;
129 void relaxInstruction(const MCInst &Inst, MCInst &Res) const;
131 bool writeNopData(uint64_t Count, MCObjectWriter *OW) const;
133 void handleAssemblerFlag(MCAssemblerFlag Flag) {
145 unsigned getPointerSize() const { return 4; }
146 bool isThumb() const { return isThumbMode; }
147 void setIsThumb(bool it) { isThumbMode = it; }
149 } // end anonymous namespace
151 static unsigned getRelaxedOpcode(unsigned Op) {
154 case ARM::tBcc: return ARM::t2Bcc;
155 case ARM::tLDRpci: return ARM::t2LDRpci;
156 case ARM::tADR: return ARM::t2ADR;
157 case ARM::tB: return ARM::t2B;
161 bool ARMAsmBackend::mayNeedRelaxation(const MCInst &Inst) const {
162 if (getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode())
167 bool ARMAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
169 const MCRelaxableFragment *DF,
170 const MCAsmLayout &Layout) const {
171 switch ((unsigned)Fixup.getKind()) {
172 case ARM::fixup_arm_thumb_br: {
173 // Relaxing tB to t2B. tB has a signed 12-bit displacement with the
174 // low bit being an implied zero. There's an implied +4 offset for the
175 // branch, so we adjust the other way here to determine what's
178 // Relax if the value is too big for a (signed) i8.
179 int64_t Offset = int64_t(Value) - 4;
180 return Offset > 2046 || Offset < -2048;
182 case ARM::fixup_arm_thumb_bcc: {
183 // Relaxing tBcc to t2Bcc. tBcc has a signed 9-bit displacement with the
184 // low bit being an implied zero. There's an implied +4 offset for the
185 // branch, so we adjust the other way here to determine what's
188 // Relax if the value is too big for a (signed) i8.
189 int64_t Offset = int64_t(Value) - 4;
190 return Offset > 254 || Offset < -256;
192 case ARM::fixup_thumb_adr_pcrel_10:
193 case ARM::fixup_arm_thumb_cp: {
194 // If the immediate is negative, greater than 1020, or not a multiple
195 // of four, the wide version of the instruction must be used.
196 int64_t Offset = int64_t(Value) - 4;
197 return Offset > 1020 || Offset < 0 || Offset & 3;
200 llvm_unreachable("Unexpected fixup kind in fixupNeedsRelaxation()!");
203 void ARMAsmBackend::relaxInstruction(const MCInst &Inst, MCInst &Res) const {
204 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode());
206 // Sanity check w/ diagnostic if we get here w/ a bogus instruction.
207 if (RelaxedOp == Inst.getOpcode()) {
208 SmallString<256> Tmp;
209 raw_svector_ostream OS(Tmp);
210 Inst.dump_pretty(OS);
212 report_fatal_error("unexpected instruction to relax: " + OS.str());
215 // The instructions we're relaxing have (so far) the same operands.
216 // We just need to update to the proper opcode.
218 Res.setOpcode(RelaxedOp);
221 bool ARMAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
222 const uint16_t Thumb1_16bitNopEncoding = 0x46c0; // using MOV r8,r8
223 const uint16_t Thumb2_16bitNopEncoding = 0xbf00; // NOP
224 const uint32_t ARMv4_NopEncoding = 0xe1a00000; // using MOV r0,r0
225 const uint32_t ARMv6T2_NopEncoding = 0xe320f000; // NOP
227 const uint16_t nopEncoding = hasNOP() ? Thumb2_16bitNopEncoding
228 : Thumb1_16bitNopEncoding;
229 uint64_t NumNops = Count / 2;
230 for (uint64_t i = 0; i != NumNops; ++i)
231 OW->Write16(nopEncoding);
237 const uint32_t nopEncoding = hasNOP() ? ARMv6T2_NopEncoding
239 uint64_t NumNops = Count / 4;
240 for (uint64_t i = 0; i != NumNops; ++i)
241 OW->Write32(nopEncoding);
242 // FIXME: should this function return false when unable to write exactly
243 // 'Count' bytes with NOP encodings?
245 default: break; // No leftover bytes to write
246 case 1: OW->Write8(0); break;
247 case 2: OW->Write16(0); break;
248 case 3: OW->Write16(0); OW->Write8(0xa0); break;
254 static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
255 MCContext *Ctx = NULL) {
256 unsigned Kind = Fixup.getKind();
259 llvm_unreachable("Unknown fixup kind!");
264 case ARM::fixup_arm_movt_hi16:
267 case ARM::fixup_arm_movw_lo16:
268 case ARM::fixup_arm_movt_hi16_pcrel:
269 case ARM::fixup_arm_movw_lo16_pcrel: {
270 unsigned Hi4 = (Value & 0xF000) >> 12;
271 unsigned Lo12 = Value & 0x0FFF;
272 // inst{19-16} = Hi4;
273 // inst{11-0} = Lo12;
274 Value = (Hi4 << 16) | (Lo12);
277 case ARM::fixup_t2_movt_hi16:
280 case ARM::fixup_t2_movw_lo16:
281 case ARM::fixup_t2_movt_hi16_pcrel: //FIXME: Shouldn't this be shifted like
282 // the other hi16 fixup?
283 case ARM::fixup_t2_movw_lo16_pcrel: {
284 unsigned Hi4 = (Value & 0xF000) >> 12;
285 unsigned i = (Value & 0x800) >> 11;
286 unsigned Mid3 = (Value & 0x700) >> 8;
287 unsigned Lo8 = Value & 0x0FF;
288 // inst{19-16} = Hi4;
290 // inst{14-12} = Mid3;
292 Value = (Hi4 << 16) | (i << 26) | (Mid3 << 12) | (Lo8);
293 uint64_t swapped = (Value & 0xFFFF0000) >> 16;
294 swapped |= (Value & 0x0000FFFF) << 16;
297 case ARM::fixup_arm_ldst_pcrel_12:
298 // ARM PC-relative values are offset by 8.
301 case ARM::fixup_t2_ldst_pcrel_12: {
302 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
305 if ((int64_t)Value < 0) {
309 if (Ctx && Value >= 4096)
310 Ctx->FatalError(Fixup.getLoc(), "out of range pc-relative fixup value");
311 Value |= isAdd << 23;
313 // Same addressing mode as fixup_arm_pcrel_10,
314 // but with 16-bit halfwords swapped.
315 if (Kind == ARM::fixup_t2_ldst_pcrel_12) {
316 uint64_t swapped = (Value & 0xFFFF0000) >> 16;
317 swapped |= (Value & 0x0000FFFF) << 16;
323 case ARM::fixup_thumb_adr_pcrel_10:
324 return ((Value - 4) >> 2) & 0xff;
325 case ARM::fixup_arm_adr_pcrel_12: {
326 // ARM PC-relative values are offset by 8.
328 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100
329 if ((int64_t)Value < 0) {
333 if (Ctx && ARM_AM::getSOImmVal(Value) == -1)
334 Ctx->FatalError(Fixup.getLoc(), "out of range pc-relative fixup value");
335 // Encode the immediate and shift the opcode into place.
336 return ARM_AM::getSOImmVal(Value) | (opc << 21);
339 case ARM::fixup_t2_adr_pcrel_12: {
342 if ((int64_t)Value < 0) {
347 uint32_t out = (opc << 21);
348 out |= (Value & 0x800) << 15;
349 out |= (Value & 0x700) << 4;
350 out |= (Value & 0x0FF);
352 uint64_t swapped = (out & 0xFFFF0000) >> 16;
353 swapped |= (out & 0x0000FFFF) << 16;
357 case ARM::fixup_arm_condbranch:
358 case ARM::fixup_arm_uncondbranch:
359 case ARM::fixup_arm_uncondbl:
360 case ARM::fixup_arm_condbl:
361 case ARM::fixup_arm_blx:
362 // These values don't encode the low two bits since they're always zero.
363 // Offset by 8 just as above.
364 return 0xffffff & ((Value - 8) >> 2);
365 case ARM::fixup_t2_uncondbranch: {
367 Value >>= 1; // Low bit is not encoded.
370 bool I = Value & 0x800000;
371 bool J1 = Value & 0x400000;
372 bool J2 = Value & 0x200000;
376 out |= I << 26; // S bit
377 out |= !J1 << 13; // J1 bit
378 out |= !J2 << 11; // J2 bit
379 out |= (Value & 0x1FF800) << 5; // imm6 field
380 out |= (Value & 0x0007FF); // imm11 field
382 uint64_t swapped = (out & 0xFFFF0000) >> 16;
383 swapped |= (out & 0x0000FFFF) << 16;
386 case ARM::fixup_t2_condbranch: {
388 Value >>= 1; // Low bit is not encoded.
391 out |= (Value & 0x80000) << 7; // S bit
392 out |= (Value & 0x40000) >> 7; // J2 bit
393 out |= (Value & 0x20000) >> 4; // J1 bit
394 out |= (Value & 0x1F800) << 5; // imm6 field
395 out |= (Value & 0x007FF); // imm11 field
397 uint32_t swapped = (out & 0xFFFF0000) >> 16;
398 swapped |= (out & 0x0000FFFF) << 16;
401 case ARM::fixup_arm_thumb_bl: {
402 // The value doesn't encode the low bit (always zero) and is offset by
403 // four. The 32-bit immediate value is encoded as
404 // imm32 = SignExtend(S:I1:I2:imm10:imm11:0)
405 // where I1 = NOT(J1 ^ S) and I2 = NOT(J2 ^ S).
406 // The value is encoded into disjoint bit positions in the destination
407 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit,
408 // J = either J1 or J2 bit
410 // BL: xxxxxSIIIIIIIIII xxJxJIIIIIIIIIII
412 // Note that the halfwords are stored high first, low second; so we need
413 // to transpose the fixup value here to map properly.
414 uint32_t offset = (Value - 4) >> 1;
415 uint32_t signBit = (offset & 0x800000) >> 23;
416 uint32_t I1Bit = (offset & 0x400000) >> 22;
417 uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit;
418 uint32_t I2Bit = (offset & 0x200000) >> 21;
419 uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit;
420 uint32_t imm10Bits = (offset & 0x1FF800) >> 11;
421 uint32_t imm11Bits = (offset & 0x000007FF);
424 uint32_t firstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10Bits);
425 uint32_t secondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) |
426 (uint16_t)imm11Bits);
427 Binary |= secondHalf << 16;
432 case ARM::fixup_arm_thumb_blx: {
433 // The value doesn't encode the low two bits (always zero) and is offset by
434 // four (see fixup_arm_thumb_cp). The 32-bit immediate value is encoded as
435 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:00)
436 // where I1 = NOT(J1 ^ S) and I2 = NOT(J2 ^ S).
437 // The value is encoded into disjoint bit positions in the destination
438 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit,
439 // J = either J1 or J2 bit, 0 = zero.
441 // BLX: xxxxxSIIIIIIIIII xxJxJIIIIIIIIII0
443 // Note that the halfwords are stored high first, low second; so we need
444 // to transpose the fixup value here to map properly.
445 uint32_t offset = (Value - 2) >> 2;
446 uint32_t signBit = (offset & 0x400000) >> 22;
447 uint32_t I1Bit = (offset & 0x200000) >> 21;
448 uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit;
449 uint32_t I2Bit = (offset & 0x100000) >> 20;
450 uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit;
451 uint32_t imm10HBits = (offset & 0xFFC00) >> 10;
452 uint32_t imm10LBits = (offset & 0x3FF);
455 uint32_t firstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10HBits);
456 uint32_t secondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) |
457 ((uint16_t)imm10LBits) << 1);
458 Binary |= secondHalf << 16;
462 case ARM::fixup_arm_thumb_cp:
463 // Offset by 4, and don't encode the low two bits. Two bytes of that
464 // 'off by 4' is implicitly handled by the half-word ordering of the
465 // Thumb encoding, so we only need to adjust by 2 here.
466 return ((Value - 2) >> 2) & 0xff;
467 case ARM::fixup_arm_thumb_cb: {
468 // Offset by 4 and don't encode the lower bit, which is always 0.
469 uint32_t Binary = (Value - 4) >> 1;
470 return ((Binary & 0x20) << 4) | ((Binary & 0x1f) << 3);
472 case ARM::fixup_arm_thumb_br:
473 // Offset by 4 and don't encode the lower bit, which is always 0.
474 return ((Value - 4) >> 1) & 0x7ff;
475 case ARM::fixup_arm_thumb_bcc:
476 // Offset by 4 and don't encode the lower bit, which is always 0.
477 return ((Value - 4) >> 1) & 0xff;
478 case ARM::fixup_arm_pcrel_10_unscaled: {
479 Value = Value - 8; // ARM fixups offset by an additional word and don't
480 // need to adjust for the half-word ordering.
482 if ((int64_t)Value < 0) {
486 // The value has the low 4 bits encoded in [3:0] and the high 4 in [11:8].
487 if (Ctx && Value >= 256)
488 Ctx->FatalError(Fixup.getLoc(), "out of range pc-relative fixup value");
489 Value = (Value & 0xf) | ((Value & 0xf0) << 4);
490 return Value | (isAdd << 23);
492 case ARM::fixup_arm_pcrel_10:
493 Value = Value - 4; // ARM fixups offset by an additional word and don't
494 // need to adjust for the half-word ordering.
496 case ARM::fixup_t2_pcrel_10: {
497 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
500 if ((int64_t)Value < 0) {
504 // These values don't encode the low two bits since they're always zero.
506 if (Ctx && Value >= 256)
507 Ctx->FatalError(Fixup.getLoc(), "out of range pc-relative fixup value");
508 Value |= isAdd << 23;
510 // Same addressing mode as fixup_arm_pcrel_10, but with 16-bit halfwords
512 if (Kind == ARM::fixup_t2_pcrel_10) {
513 uint32_t swapped = (Value & 0xFFFF0000) >> 16;
514 swapped |= (Value & 0x0000FFFF) << 16;
523 void ARMAsmBackend::processFixupValue(const MCAssembler &Asm,
524 const MCAsmLayout &Layout,
525 const MCFixup &Fixup,
526 const MCFragment *DF,
527 MCValue &Target, uint64_t &Value,
529 const MCSymbolRefExpr *A = Target.getSymA();
530 // Some fixups to thumb function symbols need the low bit (thumb bit)
532 if ((unsigned)Fixup.getKind() != ARM::fixup_arm_ldst_pcrel_12 &&
533 (unsigned)Fixup.getKind() != ARM::fixup_t2_ldst_pcrel_12 &&
534 (unsigned)Fixup.getKind() != ARM::fixup_arm_adr_pcrel_12 &&
535 (unsigned)Fixup.getKind() != ARM::fixup_thumb_adr_pcrel_10 &&
536 (unsigned)Fixup.getKind() != ARM::fixup_t2_adr_pcrel_12 &&
537 (unsigned)Fixup.getKind() != ARM::fixup_arm_thumb_cp) {
539 const MCSymbol &Sym = A->getSymbol().AliasedSymbol();
540 if (Asm.isThumbFunc(&Sym))
544 // We must always generate a relocation for BL/BLX instructions if we have
545 // a symbol to reference, as the linker relies on knowing the destination
546 // symbol's thumb-ness to get interworking right.
547 if (A && ((unsigned)Fixup.getKind() == ARM::fixup_arm_thumb_blx ||
548 (unsigned)Fixup.getKind() == ARM::fixup_arm_thumb_bl ||
549 (unsigned)Fixup.getKind() == ARM::fixup_arm_blx ||
550 (unsigned)Fixup.getKind() == ARM::fixup_arm_uncondbl ||
551 (unsigned)Fixup.getKind() == ARM::fixup_arm_condbl))
554 // Try to get the encoded value for the fixup as-if we're mapping it into
555 // the instruction. This allows adjustFixupValue() to issue a diagnostic
556 // if the value aren't invalid.
557 (void)adjustFixupValue(Fixup, Value, &Asm.getContext());
560 /// getFixupKindNumBytes - The number of bytes the fixup may change.
561 static unsigned getFixupKindNumBytes(unsigned Kind) {
564 llvm_unreachable("Unknown fixup kind!");
567 case ARM::fixup_arm_thumb_bcc:
568 case ARM::fixup_arm_thumb_cp:
569 case ARM::fixup_thumb_adr_pcrel_10:
573 case ARM::fixup_arm_thumb_br:
574 case ARM::fixup_arm_thumb_cb:
577 case ARM::fixup_arm_pcrel_10_unscaled:
578 case ARM::fixup_arm_ldst_pcrel_12:
579 case ARM::fixup_arm_pcrel_10:
580 case ARM::fixup_arm_adr_pcrel_12:
581 case ARM::fixup_arm_uncondbl:
582 case ARM::fixup_arm_condbl:
583 case ARM::fixup_arm_blx:
584 case ARM::fixup_arm_condbranch:
585 case ARM::fixup_arm_uncondbranch:
589 case ARM::fixup_t2_ldst_pcrel_12:
590 case ARM::fixup_t2_condbranch:
591 case ARM::fixup_t2_uncondbranch:
592 case ARM::fixup_t2_pcrel_10:
593 case ARM::fixup_t2_adr_pcrel_12:
594 case ARM::fixup_arm_thumb_bl:
595 case ARM::fixup_arm_thumb_blx:
596 case ARM::fixup_arm_movt_hi16:
597 case ARM::fixup_arm_movw_lo16:
598 case ARM::fixup_arm_movt_hi16_pcrel:
599 case ARM::fixup_arm_movw_lo16_pcrel:
600 case ARM::fixup_t2_movt_hi16:
601 case ARM::fixup_t2_movw_lo16:
602 case ARM::fixup_t2_movt_hi16_pcrel:
603 case ARM::fixup_t2_movw_lo16_pcrel:
608 void ARMAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
609 unsigned DataSize, uint64_t Value) const {
610 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
611 Value = adjustFixupValue(Fixup, Value);
612 if (!Value) return; // Doesn't change encoding.
614 unsigned Offset = Fixup.getOffset();
615 assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!");
617 // For each byte of the fragment that the fixup touches, mask in the bits from
618 // the fixup value. The Value has been "split up" into the appropriate
620 for (unsigned i = 0; i != NumBytes; ++i)
621 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
626 // FIXME: This should be in a separate file.
627 // ELF is an ELF of course...
628 class ELFARMAsmBackend : public ARMAsmBackend {
631 ELFARMAsmBackend(const Target &T, const StringRef TT,
633 : ARMAsmBackend(T, TT), OSABI(_OSABI) { }
635 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
636 return createARMELFObjectWriter(OS, OSABI);
640 // FIXME: This should be in a separate file.
641 class DarwinARMAsmBackend : public ARMAsmBackend {
643 const object::mach::CPUSubtypeARM Subtype;
644 DarwinARMAsmBackend(const Target &T, const StringRef TT,
645 object::mach::CPUSubtypeARM st)
646 : ARMAsmBackend(T, TT), Subtype(st) {
647 HasDataInCodeSupport = true;
650 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
651 return createARMMachObjectWriter(OS, /*Is64Bit=*/false,
652 object::mach::CTM_ARM,
656 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
661 } // end anonymous namespace
663 MCAsmBackend *llvm::createARMAsmBackend(const Target &T, StringRef TT, StringRef CPU) {
664 Triple TheTriple(TT);
666 if (TheTriple.isOSDarwin()) {
667 object::mach::CPUSubtypeARM CS =
668 StringSwitch<object::mach::CPUSubtypeARM>(TheTriple.getArchName())
669 .Cases("armv4t", "thumbv4t", object::mach::CSARM_V4T)
670 .Cases("armv5e", "thumbv5e",object::mach::CSARM_V5TEJ)
671 .Cases("armv6", "thumbv6", object::mach::CSARM_V6)
672 .Cases("armv6m", "thumbv6m", object::mach::CSARM_V6M)
673 .Cases("armv7em", "thumbv7em", object::mach::CSARM_V7EM)
674 .Cases("armv7f", "thumbv7f", object::mach::CSARM_V7F)
675 .Cases("armv7k", "thumbv7k", object::mach::CSARM_V7K)
676 .Cases("armv7m", "thumbv7m", object::mach::CSARM_V7M)
677 .Cases("armv7s", "thumbv7s", object::mach::CSARM_V7S)
678 .Default(object::mach::CSARM_V7);
680 return new DarwinARMAsmBackend(T, TT, CS);
684 // FIXME: Introduce yet another checker but assert(0).
685 if (TheTriple.isOSBinFormatCOFF())
686 assert(0 && "Windows not supported on ARM");
689 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(Triple(TT).getOS());
690 return new ELFARMAsmBackend(T, TT, OSABI);