1 //===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/ARMMCTargetDesc.h"
11 #include "MCTargetDesc/ARMAddressingModes.h"
12 #include "MCTargetDesc/ARMAsmBackend.h"
13 #include "MCTargetDesc/ARMAsmBackendDarwin.h"
14 #include "MCTargetDesc/ARMAsmBackendELF.h"
15 #include "MCTargetDesc/ARMAsmBackendWinCOFF.h"
16 #include "MCTargetDesc/ARMBaseInfo.h"
17 #include "MCTargetDesc/ARMFixupKinds.h"
18 #include "llvm/ADT/StringSwitch.h"
19 #include "llvm/MC/MCAsmBackend.h"
20 #include "llvm/MC/MCAssembler.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCDirectives.h"
23 #include "llvm/MC/MCELFObjectWriter.h"
24 #include "llvm/MC/MCExpr.h"
25 #include "llvm/MC/MCFixupKindInfo.h"
26 #include "llvm/MC/MCMachObjectWriter.h"
27 #include "llvm/MC/MCObjectWriter.h"
28 #include "llvm/MC/MCSectionELF.h"
29 #include "llvm/MC/MCSectionMachO.h"
30 #include "llvm/MC/MCSubtargetInfo.h"
31 #include "llvm/MC/MCValue.h"
32 #include "llvm/Support/ELF.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/MachO.h"
35 #include "llvm/Support/raw_ostream.h"
39 class ARMELFObjectWriter : public MCELFObjectTargetWriter {
41 ARMELFObjectWriter(uint8_t OSABI)
42 : MCELFObjectTargetWriter(/*Is64Bit*/ false, OSABI, ELF::EM_ARM,
43 /*HasRelocationAddend*/ false) {}
46 const MCFixupKindInfo &ARMAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
47 const static MCFixupKindInfo InfosLE[ARM::NumTargetFixupKinds] = {
48 // This table *must* be in the order that the fixup_* kinds are defined in
51 // Name Offset (bits) Size (bits) Flags
52 {"fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
53 {"fixup_t2_ldst_pcrel_12", 0, 32,
54 MCFixupKindInfo::FKF_IsPCRel |
55 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
56 {"fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
57 {"fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
58 {"fixup_t2_pcrel_10", 0, 32,
59 MCFixupKindInfo::FKF_IsPCRel |
60 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
61 {"fixup_thumb_adr_pcrel_10", 0, 8,
62 MCFixupKindInfo::FKF_IsPCRel |
63 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
64 {"fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
65 {"fixup_t2_adr_pcrel_12", 0, 32,
66 MCFixupKindInfo::FKF_IsPCRel |
67 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
68 {"fixup_arm_condbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
69 {"fixup_arm_uncondbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
70 {"fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
71 {"fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
72 {"fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
73 {"fixup_arm_uncondbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
74 {"fixup_arm_condbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
75 {"fixup_arm_blx", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
76 {"fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
77 {"fixup_arm_thumb_blx", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
78 {"fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
79 {"fixup_arm_thumb_cp", 0, 8,
80 MCFixupKindInfo::FKF_IsPCRel |
81 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
82 {"fixup_arm_thumb_bcc", 0, 8, MCFixupKindInfo::FKF_IsPCRel},
83 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16
85 {"fixup_arm_movt_hi16", 0, 20, 0},
86 {"fixup_arm_movw_lo16", 0, 20, 0},
87 {"fixup_t2_movt_hi16", 0, 20, 0},
88 {"fixup_t2_movw_lo16", 0, 20, 0},
90 const static MCFixupKindInfo InfosBE[ARM::NumTargetFixupKinds] = {
91 // This table *must* be in the order that the fixup_* kinds are defined in
94 // Name Offset (bits) Size (bits) Flags
95 {"fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
96 {"fixup_t2_ldst_pcrel_12", 0, 32,
97 MCFixupKindInfo::FKF_IsPCRel |
98 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
99 {"fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
100 {"fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
101 {"fixup_t2_pcrel_10", 0, 32,
102 MCFixupKindInfo::FKF_IsPCRel |
103 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
104 {"fixup_thumb_adr_pcrel_10", 8, 8,
105 MCFixupKindInfo::FKF_IsPCRel |
106 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
107 {"fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
108 {"fixup_t2_adr_pcrel_12", 0, 32,
109 MCFixupKindInfo::FKF_IsPCRel |
110 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
111 {"fixup_arm_condbranch", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
112 {"fixup_arm_uncondbranch", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
113 {"fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
114 {"fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
115 {"fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
116 {"fixup_arm_uncondbl", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
117 {"fixup_arm_condbl", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
118 {"fixup_arm_blx", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
119 {"fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
120 {"fixup_arm_thumb_blx", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
121 {"fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
122 {"fixup_arm_thumb_cp", 8, 8,
123 MCFixupKindInfo::FKF_IsPCRel |
124 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
125 {"fixup_arm_thumb_bcc", 8, 8, MCFixupKindInfo::FKF_IsPCRel},
126 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16
128 {"fixup_arm_movt_hi16", 12, 20, 0},
129 {"fixup_arm_movw_lo16", 12, 20, 0},
130 {"fixup_t2_movt_hi16", 12, 20, 0},
131 {"fixup_t2_movw_lo16", 12, 20, 0},
134 if (Kind < FirstTargetFixupKind)
135 return MCAsmBackend::getFixupKindInfo(Kind);
137 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
139 return (IsLittleEndian ? InfosLE : InfosBE)[Kind - FirstTargetFixupKind];
142 void ARMAsmBackend::handleAssemblerFlag(MCAssemblerFlag Flag) {
154 } // end anonymous namespace
156 static unsigned getRelaxedOpcode(unsigned Op) {
163 return ARM::t2LDRpci;
175 bool ARMAsmBackend::mayNeedRelaxation(const MCInst &Inst) const {
176 if (getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode())
181 bool ARMAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
182 const MCRelaxableFragment *DF,
183 const MCAsmLayout &Layout) const {
184 switch ((unsigned)Fixup.getKind()) {
185 case ARM::fixup_arm_thumb_br: {
186 // Relaxing tB to t2B. tB has a signed 12-bit displacement with the
187 // low bit being an implied zero. There's an implied +4 offset for the
188 // branch, so we adjust the other way here to determine what's
191 // Relax if the value is too big for a (signed) i8.
192 int64_t Offset = int64_t(Value) - 4;
193 return Offset > 2046 || Offset < -2048;
195 case ARM::fixup_arm_thumb_bcc: {
196 // Relaxing tBcc to t2Bcc. tBcc has a signed 9-bit displacement with the
197 // low bit being an implied zero. There's an implied +4 offset for the
198 // branch, so we adjust the other way here to determine what's
201 // Relax if the value is too big for a (signed) i8.
202 int64_t Offset = int64_t(Value) - 4;
203 return Offset > 254 || Offset < -256;
205 case ARM::fixup_thumb_adr_pcrel_10:
206 case ARM::fixup_arm_thumb_cp: {
207 // If the immediate is negative, greater than 1020, or not a multiple
208 // of four, the wide version of the instruction must be used.
209 int64_t Offset = int64_t(Value) - 4;
210 return Offset > 1020 || Offset < 0 || Offset & 3;
212 case ARM::fixup_arm_thumb_cb:
213 // If we have a Thumb CBZ or CBNZ instruction and its target is the next
214 // instruction it is is actually out of range for the instruction.
215 // It will be changed to a NOP.
216 int64_t Offset = (Value & ~1);
219 llvm_unreachable("Unexpected fixup kind in fixupNeedsRelaxation()!");
222 void ARMAsmBackend::relaxInstruction(const MCInst &Inst, MCInst &Res) const {
223 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode());
225 // Sanity check w/ diagnostic if we get here w/ a bogus instruction.
226 if (RelaxedOp == Inst.getOpcode()) {
227 SmallString<256> Tmp;
228 raw_svector_ostream OS(Tmp);
229 Inst.dump_pretty(OS);
231 report_fatal_error("unexpected instruction to relax: " + OS.str());
234 // If we are changing Thumb CBZ or CBNZ instruction to a NOP, aka tHINT, we
235 // have to change the operands too.
236 if ((Inst.getOpcode() == ARM::tCBZ || Inst.getOpcode() == ARM::tCBNZ) &&
237 RelaxedOp == ARM::tHINT) {
238 Res.setOpcode(RelaxedOp);
239 Res.addOperand(MCOperand::CreateImm(0));
240 Res.addOperand(MCOperand::CreateImm(14));
241 Res.addOperand(MCOperand::CreateReg(0));
245 // The rest of instructions we're relaxing have the same operands.
246 // We just need to update to the proper opcode.
248 Res.setOpcode(RelaxedOp);
251 bool ARMAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
252 const uint16_t Thumb1_16bitNopEncoding = 0x46c0; // using MOV r8,r8
253 const uint16_t Thumb2_16bitNopEncoding = 0xbf00; // NOP
254 const uint32_t ARMv4_NopEncoding = 0xe1a00000; // using MOV r0,r0
255 const uint32_t ARMv6T2_NopEncoding = 0xe320f000; // NOP
257 const uint16_t nopEncoding =
258 hasNOP() ? Thumb2_16bitNopEncoding : Thumb1_16bitNopEncoding;
259 uint64_t NumNops = Count / 2;
260 for (uint64_t i = 0; i != NumNops; ++i)
261 OW->Write16(nopEncoding);
267 const uint32_t nopEncoding =
268 hasNOP() ? ARMv6T2_NopEncoding : ARMv4_NopEncoding;
269 uint64_t NumNops = Count / 4;
270 for (uint64_t i = 0; i != NumNops; ++i)
271 OW->Write32(nopEncoding);
272 // FIXME: should this function return false when unable to write exactly
273 // 'Count' bytes with NOP encodings?
276 break; // No leftover bytes to write
292 static uint32_t swapHalfWords(uint32_t Value, bool IsLittleEndian) {
293 if (IsLittleEndian) {
294 // Note that the halfwords are stored high first and low second in thumb;
295 // so we need to swap the fixup value here to map properly.
296 uint32_t Swapped = (Value & 0xFFFF0000) >> 16;
297 Swapped |= (Value & 0x0000FFFF) << 16;
303 static uint32_t joinHalfWords(uint32_t FirstHalf, uint32_t SecondHalf,
304 bool IsLittleEndian) {
307 if (IsLittleEndian) {
308 Value = (SecondHalf & 0xFFFF) << 16;
309 Value |= (FirstHalf & 0xFFFF);
311 Value = (SecondHalf & 0xFFFF);
312 Value |= (FirstHalf & 0xFFFF) << 16;
318 static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
319 bool IsPCRel, MCContext *Ctx,
320 bool IsLittleEndian) {
321 unsigned Kind = Fixup.getKind();
324 llvm_unreachable("Unknown fixup kind!");
333 case ARM::fixup_arm_movt_hi16:
337 case ARM::fixup_arm_movw_lo16: {
338 unsigned Hi4 = (Value & 0xF000) >> 12;
339 unsigned Lo12 = Value & 0x0FFF;
340 // inst{19-16} = Hi4;
341 // inst{11-0} = Lo12;
342 Value = (Hi4 << 16) | (Lo12);
345 case ARM::fixup_t2_movt_hi16:
349 case ARM::fixup_t2_movw_lo16: {
350 unsigned Hi4 = (Value & 0xF000) >> 12;
351 unsigned i = (Value & 0x800) >> 11;
352 unsigned Mid3 = (Value & 0x700) >> 8;
353 unsigned Lo8 = Value & 0x0FF;
354 // inst{19-16} = Hi4;
356 // inst{14-12} = Mid3;
358 Value = (Hi4 << 16) | (i << 26) | (Mid3 << 12) | (Lo8);
359 return swapHalfWords(Value, IsLittleEndian);
361 case ARM::fixup_arm_ldst_pcrel_12:
362 // ARM PC-relative values are offset by 8.
365 case ARM::fixup_t2_ldst_pcrel_12: {
366 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
369 if ((int64_t)Value < 0) {
373 if (Ctx && Value >= 4096)
374 Ctx->FatalError(Fixup.getLoc(), "out of range pc-relative fixup value");
375 Value |= isAdd << 23;
377 // Same addressing mode as fixup_arm_pcrel_10,
378 // but with 16-bit halfwords swapped.
379 if (Kind == ARM::fixup_t2_ldst_pcrel_12)
380 return swapHalfWords(Value, IsLittleEndian);
384 case ARM::fixup_thumb_adr_pcrel_10:
385 return ((Value - 4) >> 2) & 0xff;
386 case ARM::fixup_arm_adr_pcrel_12: {
387 // ARM PC-relative values are offset by 8.
389 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100
390 if ((int64_t)Value < 0) {
394 if (Ctx && ARM_AM::getSOImmVal(Value) == -1)
395 Ctx->FatalError(Fixup.getLoc(), "out of range pc-relative fixup value");
396 // Encode the immediate and shift the opcode into place.
397 return ARM_AM::getSOImmVal(Value) | (opc << 21);
400 case ARM::fixup_t2_adr_pcrel_12: {
403 if ((int64_t)Value < 0) {
408 uint32_t out = (opc << 21);
409 out |= (Value & 0x800) << 15;
410 out |= (Value & 0x700) << 4;
411 out |= (Value & 0x0FF);
413 return swapHalfWords(out, IsLittleEndian);
416 case ARM::fixup_arm_condbranch:
417 case ARM::fixup_arm_uncondbranch:
418 case ARM::fixup_arm_uncondbl:
419 case ARM::fixup_arm_condbl:
420 case ARM::fixup_arm_blx:
421 // These values don't encode the low two bits since they're always zero.
422 // Offset by 8 just as above.
423 if (const MCSymbolRefExpr *SRE =
424 dyn_cast<MCSymbolRefExpr>(Fixup.getValue()))
425 if (SRE->getKind() == MCSymbolRefExpr::VK_ARM_TLSCALL)
427 return 0xffffff & ((Value - 8) >> 2);
428 case ARM::fixup_t2_uncondbranch: {
430 Value >>= 1; // Low bit is not encoded.
433 bool I = Value & 0x800000;
434 bool J1 = Value & 0x400000;
435 bool J2 = Value & 0x200000;
439 out |= I << 26; // S bit
440 out |= !J1 << 13; // J1 bit
441 out |= !J2 << 11; // J2 bit
442 out |= (Value & 0x1FF800) << 5; // imm6 field
443 out |= (Value & 0x0007FF); // imm11 field
445 return swapHalfWords(out, IsLittleEndian);
447 case ARM::fixup_t2_condbranch: {
449 Value >>= 1; // Low bit is not encoded.
452 out |= (Value & 0x80000) << 7; // S bit
453 out |= (Value & 0x40000) >> 7; // J2 bit
454 out |= (Value & 0x20000) >> 4; // J1 bit
455 out |= (Value & 0x1F800) << 5; // imm6 field
456 out |= (Value & 0x007FF); // imm11 field
458 return swapHalfWords(out, IsLittleEndian);
460 case ARM::fixup_arm_thumb_bl: {
461 // The value doesn't encode the low bit (always zero) and is offset by
462 // four. The 32-bit immediate value is encoded as
463 // imm32 = SignExtend(S:I1:I2:imm10:imm11:0)
464 // where I1 = NOT(J1 ^ S) and I2 = NOT(J2 ^ S).
465 // The value is encoded into disjoint bit positions in the destination
466 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit,
467 // J = either J1 or J2 bit
469 // BL: xxxxxSIIIIIIIIII xxJxJIIIIIIIIIII
471 // Note that the halfwords are stored high first, low second; so we need
472 // to transpose the fixup value here to map properly.
473 uint32_t offset = (Value - 4) >> 1;
474 uint32_t signBit = (offset & 0x800000) >> 23;
475 uint32_t I1Bit = (offset & 0x400000) >> 22;
476 uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit;
477 uint32_t I2Bit = (offset & 0x200000) >> 21;
478 uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit;
479 uint32_t imm10Bits = (offset & 0x1FF800) >> 11;
480 uint32_t imm11Bits = (offset & 0x000007FF);
482 uint32_t FirstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10Bits);
483 uint32_t SecondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) |
484 (uint16_t)imm11Bits);
485 return joinHalfWords(FirstHalf, SecondHalf, IsLittleEndian);
487 case ARM::fixup_arm_thumb_blx: {
488 // The value doesn't encode the low two bits (always zero) and is offset by
489 // four (see fixup_arm_thumb_cp). The 32-bit immediate value is encoded as
490 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:00)
491 // where I1 = NOT(J1 ^ S) and I2 = NOT(J2 ^ S).
492 // The value is encoded into disjoint bit positions in the destination
493 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit,
494 // J = either J1 or J2 bit, 0 = zero.
496 // BLX: xxxxxSIIIIIIIIII xxJxJIIIIIIIIII0
498 // Note that the halfwords are stored high first, low second; so we need
499 // to transpose the fixup value here to map properly.
500 uint32_t offset = (Value - 2) >> 2;
501 if (const MCSymbolRefExpr *SRE =
502 dyn_cast<MCSymbolRefExpr>(Fixup.getValue()))
503 if (SRE->getKind() == MCSymbolRefExpr::VK_ARM_TLSCALL)
505 uint32_t signBit = (offset & 0x400000) >> 22;
506 uint32_t I1Bit = (offset & 0x200000) >> 21;
507 uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit;
508 uint32_t I2Bit = (offset & 0x100000) >> 20;
509 uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit;
510 uint32_t imm10HBits = (offset & 0xFFC00) >> 10;
511 uint32_t imm10LBits = (offset & 0x3FF);
513 uint32_t FirstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10HBits);
514 uint32_t SecondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) |
515 ((uint16_t)imm10LBits) << 1);
516 return joinHalfWords(FirstHalf, SecondHalf, IsLittleEndian);
518 case ARM::fixup_arm_thumb_cp:
519 // Offset by 4, and don't encode the low two bits. Two bytes of that
520 // 'off by 4' is implicitly handled by the half-word ordering of the
521 // Thumb encoding, so we only need to adjust by 2 here.
522 return ((Value - 2) >> 2) & 0xff;
523 case ARM::fixup_arm_thumb_cb: {
524 // Offset by 4 and don't encode the lower bit, which is always 0.
525 uint32_t Binary = (Value - 4) >> 1;
526 return ((Binary & 0x20) << 4) | ((Binary & 0x1f) << 3);
528 case ARM::fixup_arm_thumb_br:
529 // Offset by 4 and don't encode the lower bit, which is always 0.
530 return ((Value - 4) >> 1) & 0x7ff;
531 case ARM::fixup_arm_thumb_bcc:
532 // Offset by 4 and don't encode the lower bit, which is always 0.
533 return ((Value - 4) >> 1) & 0xff;
534 case ARM::fixup_arm_pcrel_10_unscaled: {
535 Value = Value - 8; // ARM fixups offset by an additional word and don't
536 // need to adjust for the half-word ordering.
538 if ((int64_t)Value < 0) {
542 // The value has the low 4 bits encoded in [3:0] and the high 4 in [11:8].
543 if (Ctx && Value >= 256)
544 Ctx->FatalError(Fixup.getLoc(), "out of range pc-relative fixup value");
545 Value = (Value & 0xf) | ((Value & 0xf0) << 4);
546 return Value | (isAdd << 23);
548 case ARM::fixup_arm_pcrel_10:
549 Value = Value - 4; // ARM fixups offset by an additional word and don't
550 // need to adjust for the half-word ordering.
552 case ARM::fixup_t2_pcrel_10: {
553 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
556 if ((int64_t)Value < 0) {
560 // These values don't encode the low two bits since they're always zero.
562 if (Ctx && Value >= 256)
563 Ctx->FatalError(Fixup.getLoc(), "out of range pc-relative fixup value");
564 Value |= isAdd << 23;
566 // Same addressing mode as fixup_arm_pcrel_10, but with 16-bit halfwords
568 if (Kind == ARM::fixup_t2_pcrel_10)
569 return swapHalfWords(Value, IsLittleEndian);
576 void ARMAsmBackend::processFixupValue(const MCAssembler &Asm,
577 const MCAsmLayout &Layout,
578 const MCFixup &Fixup,
579 const MCFragment *DF,
580 const MCValue &Target, uint64_t &Value,
582 const MCSymbolRefExpr *A = Target.getSymA();
583 // Some fixups to thumb function symbols need the low bit (thumb bit)
585 if ((unsigned)Fixup.getKind() != ARM::fixup_arm_ldst_pcrel_12 &&
586 (unsigned)Fixup.getKind() != ARM::fixup_t2_ldst_pcrel_12 &&
587 (unsigned)Fixup.getKind() != ARM::fixup_arm_adr_pcrel_12 &&
588 (unsigned)Fixup.getKind() != ARM::fixup_thumb_adr_pcrel_10 &&
589 (unsigned)Fixup.getKind() != ARM::fixup_t2_adr_pcrel_12 &&
590 (unsigned)Fixup.getKind() != ARM::fixup_arm_thumb_cp) {
592 const MCSymbol &Sym = A->getSymbol().AliasedSymbol();
593 if (Asm.isThumbFunc(&Sym))
597 // For Thumb1 BL instruction, it is possible to be a long jump between
598 // the basic blocks of the same function. Thus, we would like to resolve
599 // the offset when the destination has the same MCFragment.
600 if (A && (unsigned)Fixup.getKind() == ARM::fixup_arm_thumb_bl) {
601 const MCSymbol &Sym = A->getSymbol().AliasedSymbol();
602 const MCSymbolData &SymData = Asm.getSymbolData(Sym);
603 IsResolved = (SymData.getFragment() == DF);
605 // We must always generate a relocation for BL/BLX instructions if we have
606 // a symbol to reference, as the linker relies on knowing the destination
607 // symbol's thumb-ness to get interworking right.
608 if (A && ((unsigned)Fixup.getKind() == ARM::fixup_arm_thumb_blx ||
609 (unsigned)Fixup.getKind() == ARM::fixup_arm_blx ||
610 (unsigned)Fixup.getKind() == ARM::fixup_arm_uncondbl ||
611 (unsigned)Fixup.getKind() == ARM::fixup_arm_condbl))
614 // Try to get the encoded value for the fixup as-if we're mapping it into
615 // the instruction. This allows adjustFixupValue() to issue a diagnostic
616 // if the value aren't invalid.
617 (void)adjustFixupValue(Fixup, Value, false, &Asm.getContext(),
621 /// getFixupKindNumBytes - The number of bytes the fixup may change.
622 static unsigned getFixupKindNumBytes(unsigned Kind) {
625 llvm_unreachable("Unknown fixup kind!");
628 case ARM::fixup_arm_thumb_bcc:
629 case ARM::fixup_arm_thumb_cp:
630 case ARM::fixup_thumb_adr_pcrel_10:
634 case ARM::fixup_arm_thumb_br:
635 case ARM::fixup_arm_thumb_cb:
638 case ARM::fixup_arm_pcrel_10_unscaled:
639 case ARM::fixup_arm_ldst_pcrel_12:
640 case ARM::fixup_arm_pcrel_10:
641 case ARM::fixup_arm_adr_pcrel_12:
642 case ARM::fixup_arm_uncondbl:
643 case ARM::fixup_arm_condbl:
644 case ARM::fixup_arm_blx:
645 case ARM::fixup_arm_condbranch:
646 case ARM::fixup_arm_uncondbranch:
650 case ARM::fixup_t2_ldst_pcrel_12:
651 case ARM::fixup_t2_condbranch:
652 case ARM::fixup_t2_uncondbranch:
653 case ARM::fixup_t2_pcrel_10:
654 case ARM::fixup_t2_adr_pcrel_12:
655 case ARM::fixup_arm_thumb_bl:
656 case ARM::fixup_arm_thumb_blx:
657 case ARM::fixup_arm_movt_hi16:
658 case ARM::fixup_arm_movw_lo16:
659 case ARM::fixup_t2_movt_hi16:
660 case ARM::fixup_t2_movw_lo16:
670 /// getFixupKindContainerSizeBytes - The number of bytes of the
671 /// container involved in big endian.
672 static unsigned getFixupKindContainerSizeBytes(unsigned Kind) {
675 llvm_unreachable("Unknown fixup kind!");
684 case ARM::fixup_arm_thumb_bcc:
685 case ARM::fixup_arm_thumb_cp:
686 case ARM::fixup_thumb_adr_pcrel_10:
687 case ARM::fixup_arm_thumb_br:
688 case ARM::fixup_arm_thumb_cb:
689 // Instruction size is 2 bytes.
692 case ARM::fixup_arm_pcrel_10_unscaled:
693 case ARM::fixup_arm_ldst_pcrel_12:
694 case ARM::fixup_arm_pcrel_10:
695 case ARM::fixup_arm_adr_pcrel_12:
696 case ARM::fixup_arm_uncondbl:
697 case ARM::fixup_arm_condbl:
698 case ARM::fixup_arm_blx:
699 case ARM::fixup_arm_condbranch:
700 case ARM::fixup_arm_uncondbranch:
701 case ARM::fixup_t2_ldst_pcrel_12:
702 case ARM::fixup_t2_condbranch:
703 case ARM::fixup_t2_uncondbranch:
704 case ARM::fixup_t2_pcrel_10:
705 case ARM::fixup_t2_adr_pcrel_12:
706 case ARM::fixup_arm_thumb_bl:
707 case ARM::fixup_arm_thumb_blx:
708 case ARM::fixup_arm_movt_hi16:
709 case ARM::fixup_arm_movw_lo16:
710 case ARM::fixup_t2_movt_hi16:
711 case ARM::fixup_t2_movw_lo16:
712 // Instruction size is 4 bytes.
717 void ARMAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
718 unsigned DataSize, uint64_t Value,
719 bool IsPCRel) const {
720 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
721 Value = adjustFixupValue(Fixup, Value, IsPCRel, nullptr, IsLittleEndian);
723 return; // Doesn't change encoding.
725 unsigned Offset = Fixup.getOffset();
726 assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!");
728 // Used to point to big endian bytes.
729 unsigned FullSizeBytes;
730 if (!IsLittleEndian) {
731 FullSizeBytes = getFixupKindContainerSizeBytes(Fixup.getKind());
732 assert((Offset + FullSizeBytes) <= DataSize && "Invalid fixup size!");
733 assert(NumBytes <= FullSizeBytes && "Invalid fixup size!");
736 // For each byte of the fragment that the fixup touches, mask in the bits from
737 // the fixup value. The Value has been "split up" into the appropriate
739 for (unsigned i = 0; i != NumBytes; ++i) {
740 unsigned Idx = IsLittleEndian ? i : (FullSizeBytes - 1 - i);
741 Data[Offset + Idx] |= uint8_t((Value >> (i * 8)) & 0xff);
745 MCAsmBackend *llvm::createARMAsmBackend(const Target &T,
746 const MCRegisterInfo &MRI, StringRef TT,
747 StringRef CPU, bool isLittle) {
748 Triple TheTriple(TT);
750 switch (TheTriple.getObjectFormat()) {
752 llvm_unreachable("unsupported object format");
753 case Triple::MachO: {
754 MachO::CPUSubTypeARM CS =
755 StringSwitch<MachO::CPUSubTypeARM>(TheTriple.getArchName())
756 .Cases("armv4t", "thumbv4t", MachO::CPU_SUBTYPE_ARM_V4T)
757 .Cases("armv5e", "thumbv5e", MachO::CPU_SUBTYPE_ARM_V5TEJ)
758 .Cases("armv6", "thumbv6", MachO::CPU_SUBTYPE_ARM_V6)
759 .Cases("armv6m", "thumbv6m", MachO::CPU_SUBTYPE_ARM_V6M)
760 .Cases("armv7em", "thumbv7em", MachO::CPU_SUBTYPE_ARM_V7EM)
761 .Cases("armv7k", "thumbv7k", MachO::CPU_SUBTYPE_ARM_V7K)
762 .Cases("armv7m", "thumbv7m", MachO::CPU_SUBTYPE_ARM_V7M)
763 .Cases("armv7s", "thumbv7s", MachO::CPU_SUBTYPE_ARM_V7S)
764 .Default(MachO::CPU_SUBTYPE_ARM_V7);
766 return new ARMAsmBackendDarwin(T, TT, CS);
769 assert(TheTriple.isOSWindows() && "non-Windows ARM COFF is not supported");
770 return new ARMAsmBackendWinCOFF(T, TT);
772 assert(TheTriple.isOSBinFormatELF() && "using ELF for non-ELF target");
773 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(Triple(TT).getOS());
774 return new ARMAsmBackendELF(T, TT, OSABI, isLittle);
778 MCAsmBackend *llvm::createARMLEAsmBackend(const Target &T,
779 const MCRegisterInfo &MRI,
780 StringRef TT, StringRef CPU) {
781 return createARMAsmBackend(T, MRI, TT, CPU, true);
784 MCAsmBackend *llvm::createARMBEAsmBackend(const Target &T,
785 const MCRegisterInfo &MRI,
786 StringRef TT, StringRef CPU) {
787 return createARMAsmBackend(T, MRI, TT, CPU, false);
790 MCAsmBackend *llvm::createThumbLEAsmBackend(const Target &T,
791 const MCRegisterInfo &MRI,
792 StringRef TT, StringRef CPU) {
793 return createARMAsmBackend(T, MRI, TT, CPU, true);
796 MCAsmBackend *llvm::createThumbBEAsmBackend(const Target &T,
797 const MCRegisterInfo &MRI,
798 StringRef TT, StringRef CPU) {
799 return createARMAsmBackend(T, MRI, TT, CPU, false);