1 //===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class prints an ARM MCInst to a .s file.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "asm-printer"
15 #include "ARMInstPrinter.h"
16 #include "MCTargetDesc/ARMBaseInfo.h"
17 #include "MCTargetDesc/ARMAddressingModes.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCAsmInfo.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/Support/raw_ostream.h"
26 #include "ARMGenAsmWriter.inc"
28 /// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing.
30 /// getSORegOffset returns an integer from 0-31, representing '32' as 0.
31 static unsigned translateShiftImm(unsigned imm) {
32 // lsr #32 and asr #32 exist, but should be encoded as a 0.
33 assert((imm & ~0x1f) == 0 && "Invalid shift encoding");
40 /// Prints the shift value with an immediate value.
41 static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc,
43 if (ShOpc == ARM_AM::no_shift || (ShOpc == ARM_AM::lsl && !ShImm))
47 assert (!(ShOpc == ARM_AM::ror && !ShImm) && "Cannot have ror #0");
48 O << getShiftOpcStr(ShOpc);
50 if (ShOpc != ARM_AM::rrx)
51 O << " #" << translateShiftImm(ShImm);
54 ARMInstPrinter::ARMInstPrinter(const MCAsmInfo &MAI,
55 const MCInstrInfo &MII,
56 const MCRegisterInfo &MRI,
57 const MCSubtargetInfo &STI) :
58 MCInstPrinter(MAI, MII, MRI) {
59 // Initialize the set of available features.
60 setAvailableFeatures(STI.getFeatureBits());
63 void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
64 OS << getRegisterName(RegNo);
67 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
69 unsigned Opcode = MI->getOpcode();
71 // Check for HINT instructions w/ canonical names.
72 if (Opcode == ARM::HINT || Opcode == ARM::t2HINT) {
73 switch (MI->getOperand(0).getImm()) {
74 case 0: O << "\tnop"; break;
75 case 1: O << "\tyield"; break;
76 case 2: O << "\twfe"; break;
77 case 3: O << "\twfi"; break;
78 case 4: O << "\tsev"; break;
80 // Anything else should just print normally.
81 printInstruction(MI, O);
82 printAnnotation(O, Annot);
85 printPredicateOperand(MI, 1, O);
86 if (Opcode == ARM::t2HINT)
88 printAnnotation(O, Annot);
92 // Check for MOVs and print canonical forms, instead.
93 if (Opcode == ARM::MOVsr) {
94 // FIXME: Thumb variants?
95 const MCOperand &Dst = MI->getOperand(0);
96 const MCOperand &MO1 = MI->getOperand(1);
97 const MCOperand &MO2 = MI->getOperand(2);
98 const MCOperand &MO3 = MI->getOperand(3);
100 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
101 printSBitModifierOperand(MI, 6, O);
102 printPredicateOperand(MI, 4, O);
104 O << '\t' << getRegisterName(Dst.getReg())
105 << ", " << getRegisterName(MO1.getReg());
107 O << ", " << getRegisterName(MO2.getReg());
108 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
109 printAnnotation(O, Annot);
113 if (Opcode == ARM::MOVsi) {
114 // FIXME: Thumb variants?
115 const MCOperand &Dst = MI->getOperand(0);
116 const MCOperand &MO1 = MI->getOperand(1);
117 const MCOperand &MO2 = MI->getOperand(2);
119 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()));
120 printSBitModifierOperand(MI, 5, O);
121 printPredicateOperand(MI, 3, O);
123 O << '\t' << getRegisterName(Dst.getReg())
124 << ", " << getRegisterName(MO1.getReg());
126 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) {
127 printAnnotation(O, Annot);
131 O << ", #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
132 printAnnotation(O, Annot);
138 if ((Opcode == ARM::STMDB_UPD || Opcode == ARM::t2STMDB_UPD) &&
139 MI->getOperand(0).getReg() == ARM::SP &&
140 MI->getNumOperands() > 5) {
141 // Should only print PUSH if there are at least two registers in the list.
143 printPredicateOperand(MI, 2, O);
144 if (Opcode == ARM::t2STMDB_UPD)
147 printRegisterList(MI, 4, O);
148 printAnnotation(O, Annot);
151 if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP &&
152 MI->getOperand(3).getImm() == -4) {
154 printPredicateOperand(MI, 4, O);
155 O << "\t{" << getRegisterName(MI->getOperand(1).getReg()) << "}";
156 printAnnotation(O, Annot);
161 if ((Opcode == ARM::LDMIA_UPD || Opcode == ARM::t2LDMIA_UPD) &&
162 MI->getOperand(0).getReg() == ARM::SP &&
163 MI->getNumOperands() > 5) {
164 // Should only print POP if there are at least two registers in the list.
166 printPredicateOperand(MI, 2, O);
167 if (Opcode == ARM::t2LDMIA_UPD)
170 printRegisterList(MI, 4, O);
171 printAnnotation(O, Annot);
174 if (Opcode == ARM::LDR_POST_IMM && MI->getOperand(2).getReg() == ARM::SP &&
175 MI->getOperand(4).getImm() == 4) {
177 printPredicateOperand(MI, 5, O);
178 O << "\t{" << getRegisterName(MI->getOperand(0).getReg()) << "}";
179 printAnnotation(O, Annot);
185 if ((Opcode == ARM::VSTMSDB_UPD || Opcode == ARM::VSTMDDB_UPD) &&
186 MI->getOperand(0).getReg() == ARM::SP) {
187 O << '\t' << "vpush";
188 printPredicateOperand(MI, 2, O);
190 printRegisterList(MI, 4, O);
191 printAnnotation(O, Annot);
196 if ((Opcode == ARM::VLDMSIA_UPD || Opcode == ARM::VLDMDIA_UPD) &&
197 MI->getOperand(0).getReg() == ARM::SP) {
199 printPredicateOperand(MI, 2, O);
201 printRegisterList(MI, 4, O);
202 printAnnotation(O, Annot);
206 if (Opcode == ARM::tLDMIA) {
207 bool Writeback = true;
208 unsigned BaseReg = MI->getOperand(0).getReg();
209 for (unsigned i = 3; i < MI->getNumOperands(); ++i) {
210 if (MI->getOperand(i).getReg() == BaseReg)
216 printPredicateOperand(MI, 1, O);
217 O << '\t' << getRegisterName(BaseReg);
218 if (Writeback) O << "!";
220 printRegisterList(MI, 3, O);
221 printAnnotation(O, Annot);
226 if (Opcode == ARM::tMOVr && MI->getOperand(0).getReg() == ARM::R8 &&
227 MI->getOperand(1).getReg() == ARM::R8) {
229 printPredicateOperand(MI, 2, O);
230 printAnnotation(O, Annot);
234 printInstruction(MI, O);
235 printAnnotation(O, Annot);
238 void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
240 const MCOperand &Op = MI->getOperand(OpNo);
242 unsigned Reg = Op.getReg();
243 O << getRegisterName(Reg);
244 } else if (Op.isImm()) {
245 O << '#' << Op.getImm();
247 assert(Op.isExpr() && "unknown operand kind in printOperand");
248 // If a symbolic branch target was added as a constant expression then print
249 // that address in hex. And only print 32 unsigned bits for the address.
250 const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr());
252 if (BranchTarget && BranchTarget->EvaluateAsAbsolute(Address)) {
254 O.write_hex((uint32_t)Address);
257 // Otherwise, just print the expression.
263 void ARMInstPrinter::printT2LdrLabelOperand(const MCInst *MI, unsigned OpNum,
265 const MCOperand &MO1 = MI->getOperand(OpNum);
268 else if (MO1.isImm())
269 O << "[pc, #" << MO1.getImm() << "]";
271 llvm_unreachable("Unknown LDR label operand?");
274 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
275 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
277 // REG REG 0,SH_OPC - e.g. R5, ROR R3
278 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
279 void ARMInstPrinter::printSORegRegOperand(const MCInst *MI, unsigned OpNum,
281 const MCOperand &MO1 = MI->getOperand(OpNum);
282 const MCOperand &MO2 = MI->getOperand(OpNum+1);
283 const MCOperand &MO3 = MI->getOperand(OpNum+2);
285 O << getRegisterName(MO1.getReg());
287 // Print the shift opc.
288 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
289 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
290 if (ShOpc == ARM_AM::rrx)
293 O << ' ' << getRegisterName(MO2.getReg());
294 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
297 void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum,
299 const MCOperand &MO1 = MI->getOperand(OpNum);
300 const MCOperand &MO2 = MI->getOperand(OpNum+1);
302 O << getRegisterName(MO1.getReg());
304 // Print the shift opc.
305 printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()),
306 ARM_AM::getSORegOffset(MO2.getImm()));
310 //===--------------------------------------------------------------------===//
311 // Addressing Mode #2
312 //===--------------------------------------------------------------------===//
314 void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
316 const MCOperand &MO1 = MI->getOperand(Op);
317 const MCOperand &MO2 = MI->getOperand(Op+1);
318 const MCOperand &MO3 = MI->getOperand(Op+2);
320 O << "[" << getRegisterName(MO1.getReg());
323 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
325 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
326 << ARM_AM::getAM2Offset(MO3.getImm());
332 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
333 << getRegisterName(MO2.getReg());
335 printRegImmShift(O, ARM_AM::getAM2ShiftOpc(MO3.getImm()),
336 ARM_AM::getAM2Offset(MO3.getImm()));
340 void ARMInstPrinter::printAddrModeTBB(const MCInst *MI, unsigned Op,
342 const MCOperand &MO1 = MI->getOperand(Op);
343 const MCOperand &MO2 = MI->getOperand(Op+1);
344 O << "[" << getRegisterName(MO1.getReg()) << ", "
345 << getRegisterName(MO2.getReg()) << "]";
348 void ARMInstPrinter::printAddrModeTBH(const MCInst *MI, unsigned Op,
350 const MCOperand &MO1 = MI->getOperand(Op);
351 const MCOperand &MO2 = MI->getOperand(Op+1);
352 O << "[" << getRegisterName(MO1.getReg()) << ", "
353 << getRegisterName(MO2.getReg()) << ", lsl #1]";
356 void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
358 const MCOperand &MO1 = MI->getOperand(Op);
360 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
361 printOperand(MI, Op, O);
365 const MCOperand &MO3 = MI->getOperand(Op+2);
366 unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm());
367 assert(IdxMode != ARMII::IndexModePost &&
368 "Should be pre or offset index op");
370 printAM2PreOrOffsetIndexOp(MI, Op, O);
373 void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
376 const MCOperand &MO1 = MI->getOperand(OpNum);
377 const MCOperand &MO2 = MI->getOperand(OpNum+1);
380 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
382 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
387 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
388 << getRegisterName(MO1.getReg());
390 printRegImmShift(O, ARM_AM::getAM2ShiftOpc(MO2.getImm()),
391 ARM_AM::getAM2Offset(MO2.getImm()));
394 //===--------------------------------------------------------------------===//
395 // Addressing Mode #3
396 //===--------------------------------------------------------------------===//
398 void ARMInstPrinter::printAM3PostIndexOp(const MCInst *MI, unsigned Op,
400 const MCOperand &MO1 = MI->getOperand(Op);
401 const MCOperand &MO2 = MI->getOperand(Op+1);
402 const MCOperand &MO3 = MI->getOperand(Op+2);
404 O << "[" << getRegisterName(MO1.getReg()) << "], ";
407 O << (char)ARM_AM::getAM3Op(MO3.getImm())
408 << getRegisterName(MO2.getReg());
412 unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
414 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
418 void ARMInstPrinter::printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
420 const MCOperand &MO1 = MI->getOperand(Op);
421 const MCOperand &MO2 = MI->getOperand(Op+1);
422 const MCOperand &MO3 = MI->getOperand(Op+2);
424 O << '[' << getRegisterName(MO1.getReg());
427 O << ", " << getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
428 << getRegisterName(MO2.getReg()) << ']';
432 //If the op is sub we have to print the immediate even if it is 0
433 unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
434 ARM_AM::AddrOpc op = ARM_AM::getAM3Op(MO3.getImm());
436 if (ImmOffs || (op == ARM_AM::sub))
438 << ARM_AM::getAddrOpcStr(op)
443 void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned Op,
445 const MCOperand &MO1 = MI->getOperand(Op);
446 if (!MO1.isReg()) { // For label symbolic references.
447 printOperand(MI, Op, O);
451 const MCOperand &MO3 = MI->getOperand(Op+2);
452 unsigned IdxMode = ARM_AM::getAM3IdxMode(MO3.getImm());
454 if (IdxMode == ARMII::IndexModePost) {
455 printAM3PostIndexOp(MI, Op, O);
458 printAM3PreOrOffsetIndexOp(MI, Op, O);
461 void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
464 const MCOperand &MO1 = MI->getOperand(OpNum);
465 const MCOperand &MO2 = MI->getOperand(OpNum+1);
468 O << getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
469 << getRegisterName(MO1.getReg());
473 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
475 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
479 void ARMInstPrinter::printPostIdxImm8Operand(const MCInst *MI,
482 const MCOperand &MO = MI->getOperand(OpNum);
483 unsigned Imm = MO.getImm();
484 O << '#' << ((Imm & 256) ? "" : "-") << (Imm & 0xff);
487 void ARMInstPrinter::printPostIdxRegOperand(const MCInst *MI, unsigned OpNum,
489 const MCOperand &MO1 = MI->getOperand(OpNum);
490 const MCOperand &MO2 = MI->getOperand(OpNum+1);
492 O << (MO2.getImm() ? "" : "-") << getRegisterName(MO1.getReg());
495 void ARMInstPrinter::printPostIdxImm8s4Operand(const MCInst *MI,
498 const MCOperand &MO = MI->getOperand(OpNum);
499 unsigned Imm = MO.getImm();
500 O << '#' << ((Imm & 256) ? "" : "-") << ((Imm & 0xff) << 2);
504 void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
506 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MI->getOperand(OpNum)
508 O << ARM_AM::getAMSubModeStr(Mode);
511 void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
513 const MCOperand &MO1 = MI->getOperand(OpNum);
514 const MCOperand &MO2 = MI->getOperand(OpNum+1);
516 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
517 printOperand(MI, OpNum, O);
521 O << "[" << getRegisterName(MO1.getReg());
523 unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm());
524 unsigned Op = ARM_AM::getAM5Op(MO2.getImm());
525 if (ImmOffs || Op == ARM_AM::sub) {
527 << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
533 void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
535 const MCOperand &MO1 = MI->getOperand(OpNum);
536 const MCOperand &MO2 = MI->getOperand(OpNum+1);
538 O << "[" << getRegisterName(MO1.getReg());
540 // FIXME: Both darwin as and GNU as violate ARM docs here.
541 O << ", :" << (MO2.getImm() << 3);
546 void ARMInstPrinter::printAddrMode7Operand(const MCInst *MI, unsigned OpNum,
548 const MCOperand &MO1 = MI->getOperand(OpNum);
549 O << "[" << getRegisterName(MO1.getReg()) << "]";
552 void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
555 const MCOperand &MO = MI->getOperand(OpNum);
556 if (MO.getReg() == 0)
559 O << ", " << getRegisterName(MO.getReg());
562 void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
565 const MCOperand &MO = MI->getOperand(OpNum);
566 uint32_t v = ~MO.getImm();
567 int32_t lsb = CountTrailingZeros_32(v);
568 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
569 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
570 O << '#' << lsb << ", #" << width;
573 void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
575 unsigned val = MI->getOperand(OpNum).getImm();
576 O << ARM_MB::MemBOptToString(val);
579 void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
581 unsigned ShiftOp = MI->getOperand(OpNum).getImm();
582 bool isASR = (ShiftOp & (1 << 5)) != 0;
583 unsigned Amt = ShiftOp & 0x1f;
585 O << ", asr #" << (Amt == 0 ? 32 : Amt);
587 O << ", lsl #" << Amt;
590 void ARMInstPrinter::printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum,
592 unsigned Imm = MI->getOperand(OpNum).getImm();
595 assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!");
596 O << ", lsl #" << Imm;
599 void ARMInstPrinter::printPKHASRShiftImm(const MCInst *MI, unsigned OpNum,
601 unsigned Imm = MI->getOperand(OpNum).getImm();
602 // A shift amount of 32 is encoded as 0.
605 assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!");
606 O << ", asr #" << Imm;
609 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
612 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
613 if (i != OpNum) O << ", ";
614 O << getRegisterName(MI->getOperand(i).getReg());
619 void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
621 const MCOperand &Op = MI->getOperand(OpNum);
628 void ARMInstPrinter::printCPSIMod(const MCInst *MI, unsigned OpNum,
630 const MCOperand &Op = MI->getOperand(OpNum);
631 O << ARM_PROC::IModToString(Op.getImm());
634 void ARMInstPrinter::printCPSIFlag(const MCInst *MI, unsigned OpNum,
636 const MCOperand &Op = MI->getOperand(OpNum);
637 unsigned IFlags = Op.getImm();
638 for (int i=2; i >= 0; --i)
639 if (IFlags & (1 << i))
640 O << ARM_PROC::IFlagsToString(1 << i);
646 void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
648 const MCOperand &Op = MI->getOperand(OpNum);
649 unsigned SpecRegRBit = Op.getImm() >> 4;
650 unsigned Mask = Op.getImm() & 0xf;
652 if (getAvailableFeatures() & ARM::FeatureMClass) {
653 unsigned SYSm = Op.getImm();
654 unsigned Opcode = MI->getOpcode();
655 // For reads of the special registers ignore the "mask encoding" bits
656 // which are only for writes.
657 if (Opcode == ARM::t2MRS_M)
660 default: llvm_unreachable("Unexpected mask value!");
662 case 0x800: O << "apsr"; return; // with _nzcvq bits is an alias for aspr
663 case 0x400: O << "apsr_g"; return;
664 case 0xc00: O << "apsr_nzcvqg"; return;
666 case 0x801: O << "iapsr"; return; // with _nzcvq bits is an alias for iapsr
667 case 0x401: O << "iapsr_g"; return;
668 case 0xc01: O << "iapsr_nzcvqg"; return;
670 case 0x802: O << "eapsr"; return; // with _nzcvq bits is an alias for eapsr
671 case 0x402: O << "eapsr_g"; return;
672 case 0xc02: O << "eapsr_nzcvqg"; return;
674 case 0x803: O << "xpsr"; return; // with _nzcvq bits is an alias for xpsr
675 case 0x403: O << "xpsr_g"; return;
676 case 0xc03: O << "xpsr_nzcvqg"; return;
678 case 0x805: O << "ipsr"; return;
680 case 0x806: O << "epsr"; return;
682 case 0x807: O << "iepsr"; return;
684 case 0x808: O << "msp"; return;
686 case 0x809: O << "psp"; return;
688 case 0x810: O << "primask"; return;
690 case 0x811: O << "basepri"; return;
692 case 0x812: O << "basepri_max"; return;
694 case 0x813: O << "faultmask"; return;
696 case 0x814: O << "control"; return;
700 // As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as
701 // APSR_nzcvq, APSR_g and APSRnzcvqg, respectively.
702 if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) {
705 default: llvm_unreachable("Unexpected mask value!");
706 case 4: O << "g"; return;
707 case 8: O << "nzcvq"; return;
708 case 12: O << "nzcvqg"; return;
719 if (Mask & 8) O << 'f';
720 if (Mask & 4) O << 's';
721 if (Mask & 2) O << 'x';
722 if (Mask & 1) O << 'c';
726 void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
728 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
729 // Handle the undefined 15 CC value here for printing so we don't abort().
730 if ((unsigned)CC == 15)
732 else if (CC != ARMCC::AL)
733 O << ARMCondCodeToString(CC);
736 void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI,
739 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
740 O << ARMCondCodeToString(CC);
743 void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
745 if (MI->getOperand(OpNum).getReg()) {
746 assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
747 "Expect ARM CPSR register!");
752 void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
754 O << MI->getOperand(OpNum).getImm();
757 void ARMInstPrinter::printPImmediate(const MCInst *MI, unsigned OpNum,
759 O << "p" << MI->getOperand(OpNum).getImm();
762 void ARMInstPrinter::printCImmediate(const MCInst *MI, unsigned OpNum,
764 O << "c" << MI->getOperand(OpNum).getImm();
767 void ARMInstPrinter::printCoprocOptionImm(const MCInst *MI, unsigned OpNum,
769 O << "{" << MI->getOperand(OpNum).getImm() << "}";
772 void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
774 llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
777 void ARMInstPrinter::printAdrLabelOperand(const MCInst *MI, unsigned OpNum,
779 const MCOperand &MO = MI->getOperand(OpNum);
786 int32_t OffImm = (int32_t)MO.getImm();
788 if (OffImm == INT32_MIN)
791 O << "#-" << -OffImm;
796 void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
798 O << "#" << MI->getOperand(OpNum).getImm() * 4;
801 void ARMInstPrinter::printThumbSRImm(const MCInst *MI, unsigned OpNum,
803 unsigned Imm = MI->getOperand(OpNum).getImm();
804 O << "#" << (Imm == 0 ? 32 : Imm);
807 void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
809 // (3 - the number of trailing zeros) is the number of then / else.
810 unsigned Mask = MI->getOperand(OpNum).getImm();
811 unsigned Firstcond = MI->getOperand(OpNum-1).getImm();
812 unsigned CondBit0 = Firstcond & 1;
813 unsigned NumTZ = CountTrailingZeros_32(Mask);
814 assert(NumTZ <= 3 && "Invalid IT mask!");
815 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
816 bool T = ((Mask >> Pos) & 1) == CondBit0;
824 void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
826 const MCOperand &MO1 = MI->getOperand(Op);
827 const MCOperand &MO2 = MI->getOperand(Op + 1);
829 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
830 printOperand(MI, Op, O);
834 O << "[" << getRegisterName(MO1.getReg());
835 if (unsigned RegNum = MO2.getReg())
836 O << ", " << getRegisterName(RegNum);
840 void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI,
844 const MCOperand &MO1 = MI->getOperand(Op);
845 const MCOperand &MO2 = MI->getOperand(Op + 1);
847 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
848 printOperand(MI, Op, O);
852 O << "[" << getRegisterName(MO1.getReg());
853 if (unsigned ImmOffs = MO2.getImm())
854 O << ", #" << ImmOffs * Scale;
858 void ARMInstPrinter::printThumbAddrModeImm5S1Operand(const MCInst *MI,
861 printThumbAddrModeImm5SOperand(MI, Op, O, 1);
864 void ARMInstPrinter::printThumbAddrModeImm5S2Operand(const MCInst *MI,
867 printThumbAddrModeImm5SOperand(MI, Op, O, 2);
870 void ARMInstPrinter::printThumbAddrModeImm5S4Operand(const MCInst *MI,
873 printThumbAddrModeImm5SOperand(MI, Op, O, 4);
876 void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
878 printThumbAddrModeImm5SOperand(MI, Op, O, 4);
881 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
882 // register with shift forms.
884 // REG IMM, SH_OPC - e.g. R5, LSL #3
885 void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
887 const MCOperand &MO1 = MI->getOperand(OpNum);
888 const MCOperand &MO2 = MI->getOperand(OpNum+1);
890 unsigned Reg = MO1.getReg();
891 O << getRegisterName(Reg);
893 // Print the shift opc.
894 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
895 printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()),
896 ARM_AM::getSORegOffset(MO2.getImm()));
899 void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
901 const MCOperand &MO1 = MI->getOperand(OpNum);
902 const MCOperand &MO2 = MI->getOperand(OpNum+1);
904 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
905 printOperand(MI, OpNum, O);
909 O << "[" << getRegisterName(MO1.getReg());
911 int32_t OffImm = (int32_t)MO2.getImm();
912 bool isSub = OffImm < 0;
913 // Special value for #-0. All others are normal.
914 if (OffImm == INT32_MIN)
917 O << ", #-" << -OffImm;
919 O << ", #" << OffImm;
923 void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
926 const MCOperand &MO1 = MI->getOperand(OpNum);
927 const MCOperand &MO2 = MI->getOperand(OpNum+1);
929 O << "[" << getRegisterName(MO1.getReg());
931 int32_t OffImm = (int32_t)MO2.getImm();
933 if (OffImm == INT32_MIN)
936 O << ", #-" << -OffImm;
938 O << ", #" << OffImm;
942 void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
945 const MCOperand &MO1 = MI->getOperand(OpNum);
946 const MCOperand &MO2 = MI->getOperand(OpNum+1);
948 if (!MO1.isReg()) { // For label symbolic references.
949 printOperand(MI, OpNum, O);
953 O << "[" << getRegisterName(MO1.getReg());
955 int32_t OffImm = (int32_t)MO2.getImm();
957 assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
960 if (OffImm == INT32_MIN)
963 O << ", #-" << -OffImm;
965 O << ", #" << OffImm;
969 void ARMInstPrinter::printT2AddrModeImm0_1020s4Operand(const MCInst *MI,
972 const MCOperand &MO1 = MI->getOperand(OpNum);
973 const MCOperand &MO2 = MI->getOperand(OpNum+1);
975 O << "[" << getRegisterName(MO1.getReg());
977 O << ", #" << MO2.getImm() * 4;
981 void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI,
984 const MCOperand &MO1 = MI->getOperand(OpNum);
985 int32_t OffImm = (int32_t)MO1.getImm();
988 O << ", #-" << -OffImm;
990 O << ", #" << OffImm;
993 void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI,
996 const MCOperand &MO1 = MI->getOperand(OpNum);
997 int32_t OffImm = (int32_t)MO1.getImm();
999 assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
1002 if (OffImm == INT32_MIN)
1004 else if (OffImm < 0)
1005 O << ", #-" << -OffImm;
1006 else if (OffImm > 0)
1007 O << ", #" << OffImm;
1010 void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
1013 const MCOperand &MO1 = MI->getOperand(OpNum);
1014 const MCOperand &MO2 = MI->getOperand(OpNum+1);
1015 const MCOperand &MO3 = MI->getOperand(OpNum+2);
1017 O << "[" << getRegisterName(MO1.getReg());
1019 assert(MO2.getReg() && "Invalid so_reg load / store address!");
1020 O << ", " << getRegisterName(MO2.getReg());
1022 unsigned ShAmt = MO3.getImm();
1024 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
1025 O << ", lsl #" << ShAmt;
1030 void ARMInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
1032 const MCOperand &MO = MI->getOperand(OpNum);
1033 O << '#' << ARM_AM::getFPImmFloat(MO.getImm());
1036 void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
1038 unsigned EncodedImm = MI->getOperand(OpNum).getImm();
1040 uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
1045 void ARMInstPrinter::printImmPlusOneOperand(const MCInst *MI, unsigned OpNum,
1047 unsigned Imm = MI->getOperand(OpNum).getImm();
1048 O << "#" << Imm + 1;
1051 void ARMInstPrinter::printRotImmOperand(const MCInst *MI, unsigned OpNum,
1053 unsigned Imm = MI->getOperand(OpNum).getImm();
1058 default: assert (0 && "illegal ror immediate!");
1059 case 1: O << "8"; break;
1060 case 2: O << "16"; break;
1061 case 3: O << "24"; break;
1065 void ARMInstPrinter::printFBits16(const MCInst *MI, unsigned OpNum,
1067 O << "#" << 16 - MI->getOperand(OpNum).getImm();
1070 void ARMInstPrinter::printFBits32(const MCInst *MI, unsigned OpNum,
1072 O << "#" << 32 - MI->getOperand(OpNum).getImm();
1075 void ARMInstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
1077 O << "[" << MI->getOperand(OpNum).getImm() << "]";
1080 void ARMInstPrinter::printVectorListOne(const MCInst *MI, unsigned OpNum,
1082 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "}";
1085 void ARMInstPrinter::printVectorListTwo(const MCInst *MI, unsigned OpNum,
1087 unsigned Reg = MI->getOperand(OpNum).getReg();
1088 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1089 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
1090 O << "{" << getRegisterName(Reg0) << ", " << getRegisterName(Reg1) << "}";
1093 void ARMInstPrinter::printVectorListTwoSpaced(const MCInst *MI,
1096 unsigned Reg = MI->getOperand(OpNum).getReg();
1097 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1098 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
1099 O << "{" << getRegisterName(Reg0) << ", " << getRegisterName(Reg1) << "}";
1102 void ARMInstPrinter::printVectorListThree(const MCInst *MI, unsigned OpNum,
1104 // Normally, it's not safe to use register enum values directly with
1105 // addition to get the next register, but for VFP registers, the
1106 // sort order is guaranteed because they're all of the form D<n>.
1107 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", "
1108 << getRegisterName(MI->getOperand(OpNum).getReg() + 1) << ", "
1109 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "}";
1112 void ARMInstPrinter::printVectorListFour(const MCInst *MI, unsigned OpNum,
1114 // Normally, it's not safe to use register enum values directly with
1115 // addition to get the next register, but for VFP registers, the
1116 // sort order is guaranteed because they're all of the form D<n>.
1117 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", "
1118 << getRegisterName(MI->getOperand(OpNum).getReg() + 1) << ", "
1119 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << ", "
1120 << getRegisterName(MI->getOperand(OpNum).getReg() + 3) << "}";
1123 void ARMInstPrinter::printVectorListOneAllLanes(const MCInst *MI,
1126 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[]}";
1129 void ARMInstPrinter::printVectorListTwoAllLanes(const MCInst *MI,
1132 unsigned Reg = MI->getOperand(OpNum).getReg();
1133 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1134 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
1135 O << "{" << getRegisterName(Reg0) << "[], " << getRegisterName(Reg1) << "[]}";
1138 void ARMInstPrinter::printVectorListThreeAllLanes(const MCInst *MI,
1141 // Normally, it's not safe to use register enum values directly with
1142 // addition to get the next register, but for VFP registers, the
1143 // sort order is guaranteed because they're all of the form D<n>.
1144 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], "
1145 << getRegisterName(MI->getOperand(OpNum).getReg() + 1) << "[], "
1146 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "[]}";
1149 void ARMInstPrinter::printVectorListFourAllLanes(const MCInst *MI,
1152 // Normally, it's not safe to use register enum values directly with
1153 // addition to get the next register, but for VFP registers, the
1154 // sort order is guaranteed because they're all of the form D<n>.
1155 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], "
1156 << getRegisterName(MI->getOperand(OpNum).getReg() + 1) << "[], "
1157 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "[], "
1158 << getRegisterName(MI->getOperand(OpNum).getReg() + 3) << "[]}";
1161 void ARMInstPrinter::printVectorListTwoSpacedAllLanes(const MCInst *MI,
1164 unsigned Reg = MI->getOperand(OpNum).getReg();
1165 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1166 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
1167 O << "{" << getRegisterName(Reg0) << "[], " << getRegisterName(Reg1) << "[]}";
1170 void ARMInstPrinter::printVectorListThreeSpacedAllLanes(const MCInst *MI,
1173 // Normally, it's not safe to use register enum values directly with
1174 // addition to get the next register, but for VFP registers, the
1175 // sort order is guaranteed because they're all of the form D<n>.
1176 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], "
1177 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "[], "
1178 << getRegisterName(MI->getOperand(OpNum).getReg() + 4) << "[]}";
1181 void ARMInstPrinter::printVectorListFourSpacedAllLanes(const MCInst *MI,
1184 // Normally, it's not safe to use register enum values directly with
1185 // addition to get the next register, but for VFP registers, the
1186 // sort order is guaranteed because they're all of the form D<n>.
1187 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], "
1188 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "[], "
1189 << getRegisterName(MI->getOperand(OpNum).getReg() + 4) << "[], "
1190 << getRegisterName(MI->getOperand(OpNum).getReg() + 6) << "[]}";
1193 void ARMInstPrinter::printVectorListThreeSpaced(const MCInst *MI,
1196 // Normally, it's not safe to use register enum values directly with
1197 // addition to get the next register, but for VFP registers, the
1198 // sort order is guaranteed because they're all of the form D<n>.
1199 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", "
1200 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << ", "
1201 << getRegisterName(MI->getOperand(OpNum).getReg() + 4) << "}";
1204 void ARMInstPrinter::printVectorListFourSpaced(const MCInst *MI,
1207 // Normally, it's not safe to use register enum values directly with
1208 // addition to get the next register, but for VFP registers, the
1209 // sort order is guaranteed because they're all of the form D<n>.
1210 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", "
1211 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << ", "
1212 << getRegisterName(MI->getOperand(OpNum).getReg() + 4) << ", "
1213 << getRegisterName(MI->getOperand(OpNum).getReg() + 6) << "}";