1 //===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class prints an ARM MCInst to a .s file.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "asm-printer"
15 #include "ARMInstPrinter.h"
16 #include "MCTargetDesc/ARMBaseInfo.h"
17 #include "MCTargetDesc/ARMAddressingModes.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCAsmInfo.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/Support/raw_ostream.h"
24 #define GET_INSTRUCTION_NAME
25 #include "ARMGenAsmWriter.inc"
27 /// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing.
29 /// getSORegOffset returns an integer from 0-31, representing '32' as 0.
30 static unsigned translateShiftImm(unsigned imm) {
37 ARMInstPrinter::ARMInstPrinter(const MCAsmInfo &MAI,
38 const MCSubtargetInfo &STI) :
40 // Initialize the set of available features.
41 setAvailableFeatures(STI.getFeatureBits());
44 StringRef ARMInstPrinter::getOpcodeName(unsigned Opcode) const {
45 return getInstructionName(Opcode);
48 void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
49 OS << getRegisterName(RegNo);
52 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
54 unsigned Opcode = MI->getOpcode();
56 // Check for MOVs and print canonical forms, instead.
57 if (Opcode == ARM::MOVsr) {
58 // FIXME: Thumb variants?
59 const MCOperand &Dst = MI->getOperand(0);
60 const MCOperand &MO1 = MI->getOperand(1);
61 const MCOperand &MO2 = MI->getOperand(2);
62 const MCOperand &MO3 = MI->getOperand(3);
64 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
65 printSBitModifierOperand(MI, 6, O);
66 printPredicateOperand(MI, 4, O);
68 O << '\t' << getRegisterName(Dst.getReg())
69 << ", " << getRegisterName(MO1.getReg());
71 O << ", " << getRegisterName(MO2.getReg());
72 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
73 printAnnotation(O, Annot);
77 if (Opcode == ARM::MOVsi) {
78 // FIXME: Thumb variants?
79 const MCOperand &Dst = MI->getOperand(0);
80 const MCOperand &MO1 = MI->getOperand(1);
81 const MCOperand &MO2 = MI->getOperand(2);
83 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()));
84 printSBitModifierOperand(MI, 5, O);
85 printPredicateOperand(MI, 3, O);
87 O << '\t' << getRegisterName(Dst.getReg())
88 << ", " << getRegisterName(MO1.getReg());
90 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) {
91 printAnnotation(O, Annot);
95 O << ", #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
96 printAnnotation(O, Annot);
102 if ((Opcode == ARM::STMDB_UPD || Opcode == ARM::t2STMDB_UPD) &&
103 MI->getOperand(0).getReg() == ARM::SP &&
104 MI->getNumOperands() > 5) {
105 // Should only print PUSH if there are at least two registers in the list.
107 printPredicateOperand(MI, 2, O);
108 if (Opcode == ARM::t2STMDB_UPD)
111 printRegisterList(MI, 4, O);
112 printAnnotation(O, Annot);
115 if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP &&
116 MI->getOperand(3).getImm() == -4) {
118 printPredicateOperand(MI, 4, O);
119 O << "\t{" << getRegisterName(MI->getOperand(1).getReg()) << "}";
120 printAnnotation(O, Annot);
125 if ((Opcode == ARM::LDMIA_UPD || Opcode == ARM::t2LDMIA_UPD) &&
126 MI->getOperand(0).getReg() == ARM::SP &&
127 MI->getNumOperands() > 5) {
128 // Should only print POP if there are at least two registers in the list.
130 printPredicateOperand(MI, 2, O);
131 if (Opcode == ARM::t2LDMIA_UPD)
134 printRegisterList(MI, 4, O);
135 printAnnotation(O, Annot);
138 if (Opcode == ARM::LDR_POST_IMM && MI->getOperand(2).getReg() == ARM::SP &&
139 MI->getOperand(4).getImm() == 4) {
141 printPredicateOperand(MI, 5, O);
142 O << "\t{" << getRegisterName(MI->getOperand(0).getReg()) << "}";
143 printAnnotation(O, Annot);
149 if ((Opcode == ARM::VSTMSDB_UPD || Opcode == ARM::VSTMDDB_UPD) &&
150 MI->getOperand(0).getReg() == ARM::SP) {
151 O << '\t' << "vpush";
152 printPredicateOperand(MI, 2, O);
154 printRegisterList(MI, 4, O);
155 printAnnotation(O, Annot);
160 if ((Opcode == ARM::VLDMSIA_UPD || Opcode == ARM::VLDMDIA_UPD) &&
161 MI->getOperand(0).getReg() == ARM::SP) {
163 printPredicateOperand(MI, 2, O);
165 printRegisterList(MI, 4, O);
166 printAnnotation(O, Annot);
170 if (Opcode == ARM::tLDMIA) {
171 bool Writeback = true;
172 unsigned BaseReg = MI->getOperand(0).getReg();
173 for (unsigned i = 3; i < MI->getNumOperands(); ++i) {
174 if (MI->getOperand(i).getReg() == BaseReg)
180 printPredicateOperand(MI, 1, O);
181 O << '\t' << getRegisterName(BaseReg);
182 if (Writeback) O << "!";
184 printRegisterList(MI, 3, O);
185 printAnnotation(O, Annot);
190 if (Opcode == ARM::tMOVr && MI->getOperand(0).getReg() == ARM::R8 &&
191 MI->getOperand(1).getReg() == ARM::R8) {
193 printPredicateOperand(MI, 2, O);
194 printAnnotation(O, Annot);
198 printInstruction(MI, O);
199 printAnnotation(O, Annot);
202 void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
204 const MCOperand &Op = MI->getOperand(OpNo);
206 unsigned Reg = Op.getReg();
207 O << getRegisterName(Reg);
208 } else if (Op.isImm()) {
209 O << '#' << Op.getImm();
211 assert(Op.isExpr() && "unknown operand kind in printOperand");
212 // If a symbolic branch target was added as a constant expression then print
213 // that address in hex.
214 const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr());
216 if (BranchTarget && BranchTarget->EvaluateAsAbsolute(Address)) {
218 O.write_hex(Address);
221 // Otherwise, just print the expression.
227 void ARMInstPrinter::printT2LdrLabelOperand(const MCInst *MI, unsigned OpNum,
229 const MCOperand &MO1 = MI->getOperand(OpNum);
232 else if (MO1.isImm())
233 O << "[pc, #" << MO1.getImm() << "]";
235 llvm_unreachable("Unknown LDR label operand?");
238 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
239 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
241 // REG REG 0,SH_OPC - e.g. R5, ROR R3
242 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
243 void ARMInstPrinter::printSORegRegOperand(const MCInst *MI, unsigned OpNum,
245 const MCOperand &MO1 = MI->getOperand(OpNum);
246 const MCOperand &MO2 = MI->getOperand(OpNum+1);
247 const MCOperand &MO3 = MI->getOperand(OpNum+2);
249 O << getRegisterName(MO1.getReg());
251 // Print the shift opc.
252 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
253 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
254 if (ShOpc == ARM_AM::rrx)
257 O << ' ' << getRegisterName(MO2.getReg());
258 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
261 void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum,
263 const MCOperand &MO1 = MI->getOperand(OpNum);
264 const MCOperand &MO2 = MI->getOperand(OpNum+1);
266 O << getRegisterName(MO1.getReg());
268 // Print the shift opc.
269 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
270 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
271 if (ShOpc == ARM_AM::rrx)
273 O << " #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
277 //===--------------------------------------------------------------------===//
278 // Addressing Mode #2
279 //===--------------------------------------------------------------------===//
281 void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
283 const MCOperand &MO1 = MI->getOperand(Op);
284 const MCOperand &MO2 = MI->getOperand(Op+1);
285 const MCOperand &MO3 = MI->getOperand(Op+2);
287 O << "[" << getRegisterName(MO1.getReg());
290 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
292 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
293 << ARM_AM::getAM2Offset(MO3.getImm());
299 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
300 << getRegisterName(MO2.getReg());
302 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
304 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
309 void ARMInstPrinter::printAM2PostIndexOp(const MCInst *MI, unsigned Op,
311 const MCOperand &MO1 = MI->getOperand(Op);
312 const MCOperand &MO2 = MI->getOperand(Op+1);
313 const MCOperand &MO3 = MI->getOperand(Op+2);
315 O << "[" << getRegisterName(MO1.getReg()) << "], ";
318 unsigned ImmOffs = ARM_AM::getAM2Offset(MO3.getImm());
320 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
325 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
326 << getRegisterName(MO2.getReg());
328 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
330 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
334 void ARMInstPrinter::printAddrModeTBB(const MCInst *MI, unsigned Op,
336 const MCOperand &MO1 = MI->getOperand(Op);
337 const MCOperand &MO2 = MI->getOperand(Op+1);
338 O << "[" << getRegisterName(MO1.getReg()) << ", "
339 << getRegisterName(MO2.getReg()) << "]";
342 void ARMInstPrinter::printAddrModeTBH(const MCInst *MI, unsigned Op,
344 const MCOperand &MO1 = MI->getOperand(Op);
345 const MCOperand &MO2 = MI->getOperand(Op+1);
346 O << "[" << getRegisterName(MO1.getReg()) << ", "
347 << getRegisterName(MO2.getReg()) << ", lsl #1]";
350 void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
352 const MCOperand &MO1 = MI->getOperand(Op);
354 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
355 printOperand(MI, Op, O);
359 const MCOperand &MO3 = MI->getOperand(Op+2);
360 unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm());
362 if (IdxMode == ARMII::IndexModePost) {
363 printAM2PostIndexOp(MI, Op, O);
366 printAM2PreOrOffsetIndexOp(MI, Op, O);
369 void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
372 const MCOperand &MO1 = MI->getOperand(OpNum);
373 const MCOperand &MO2 = MI->getOperand(OpNum+1);
376 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
378 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
383 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
384 << getRegisterName(MO1.getReg());
386 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
388 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
392 //===--------------------------------------------------------------------===//
393 // Addressing Mode #3
394 //===--------------------------------------------------------------------===//
396 void ARMInstPrinter::printAM3PostIndexOp(const MCInst *MI, unsigned Op,
398 const MCOperand &MO1 = MI->getOperand(Op);
399 const MCOperand &MO2 = MI->getOperand(Op+1);
400 const MCOperand &MO3 = MI->getOperand(Op+2);
402 O << "[" << getRegisterName(MO1.getReg()) << "], ";
405 O << (char)ARM_AM::getAM3Op(MO3.getImm())
406 << getRegisterName(MO2.getReg());
410 unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
412 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
416 void ARMInstPrinter::printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
418 const MCOperand &MO1 = MI->getOperand(Op);
419 const MCOperand &MO2 = MI->getOperand(Op+1);
420 const MCOperand &MO3 = MI->getOperand(Op+2);
422 O << '[' << getRegisterName(MO1.getReg());
425 O << ", " << getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
426 << getRegisterName(MO2.getReg()) << ']';
430 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
432 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
437 void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned Op,
439 const MCOperand &MO3 = MI->getOperand(Op+2);
440 unsigned IdxMode = ARM_AM::getAM3IdxMode(MO3.getImm());
442 if (IdxMode == ARMII::IndexModePost) {
443 printAM3PostIndexOp(MI, Op, O);
446 printAM3PreOrOffsetIndexOp(MI, Op, O);
449 void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
452 const MCOperand &MO1 = MI->getOperand(OpNum);
453 const MCOperand &MO2 = MI->getOperand(OpNum+1);
456 O << getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
457 << getRegisterName(MO1.getReg());
461 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
463 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
467 void ARMInstPrinter::printPostIdxImm8Operand(const MCInst *MI,
470 const MCOperand &MO = MI->getOperand(OpNum);
471 unsigned Imm = MO.getImm();
472 O << '#' << ((Imm & 256) ? "" : "-") << (Imm & 0xff);
475 void ARMInstPrinter::printPostIdxRegOperand(const MCInst *MI, unsigned OpNum,
477 const MCOperand &MO1 = MI->getOperand(OpNum);
478 const MCOperand &MO2 = MI->getOperand(OpNum+1);
480 O << (MO2.getImm() ? "" : "-") << getRegisterName(MO1.getReg());
483 void ARMInstPrinter::printPostIdxImm8s4Operand(const MCInst *MI,
486 const MCOperand &MO = MI->getOperand(OpNum);
487 unsigned Imm = MO.getImm();
488 O << '#' << ((Imm & 256) ? "" : "-") << ((Imm & 0xff) << 2);
492 void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
494 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MI->getOperand(OpNum)
496 O << ARM_AM::getAMSubModeStr(Mode);
499 void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
501 const MCOperand &MO1 = MI->getOperand(OpNum);
502 const MCOperand &MO2 = MI->getOperand(OpNum+1);
504 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
505 printOperand(MI, OpNum, O);
509 O << "[" << getRegisterName(MO1.getReg());
511 unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm());
512 unsigned Op = ARM_AM::getAM5Op(MO2.getImm());
513 if (ImmOffs || Op == ARM_AM::sub) {
515 << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
521 void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
523 const MCOperand &MO1 = MI->getOperand(OpNum);
524 const MCOperand &MO2 = MI->getOperand(OpNum+1);
526 O << "[" << getRegisterName(MO1.getReg());
528 // FIXME: Both darwin as and GNU as violate ARM docs here.
529 O << ", :" << (MO2.getImm() << 3);
534 void ARMInstPrinter::printAddrMode7Operand(const MCInst *MI, unsigned OpNum,
536 const MCOperand &MO1 = MI->getOperand(OpNum);
537 O << "[" << getRegisterName(MO1.getReg()) << "]";
540 void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
543 const MCOperand &MO = MI->getOperand(OpNum);
544 if (MO.getReg() == 0)
547 O << ", " << getRegisterName(MO.getReg());
550 void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
553 const MCOperand &MO = MI->getOperand(OpNum);
554 uint32_t v = ~MO.getImm();
555 int32_t lsb = CountTrailingZeros_32(v);
556 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
557 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
558 O << '#' << lsb << ", #" << width;
561 void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
563 unsigned val = MI->getOperand(OpNum).getImm();
564 O << ARM_MB::MemBOptToString(val);
567 void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
569 unsigned ShiftOp = MI->getOperand(OpNum).getImm();
570 bool isASR = (ShiftOp & (1 << 5)) != 0;
571 unsigned Amt = ShiftOp & 0x1f;
573 O << ", asr #" << (Amt == 0 ? 32 : Amt);
575 O << ", lsl #" << Amt;
578 void ARMInstPrinter::printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum,
580 unsigned Imm = MI->getOperand(OpNum).getImm();
583 assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!");
584 O << ", lsl #" << Imm;
587 void ARMInstPrinter::printPKHASRShiftImm(const MCInst *MI, unsigned OpNum,
589 unsigned Imm = MI->getOperand(OpNum).getImm();
590 // A shift amount of 32 is encoded as 0.
593 assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!");
594 O << ", asr #" << Imm;
597 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
600 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
601 if (i != OpNum) O << ", ";
602 O << getRegisterName(MI->getOperand(i).getReg());
607 void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
609 const MCOperand &Op = MI->getOperand(OpNum);
616 void ARMInstPrinter::printCPSIMod(const MCInst *MI, unsigned OpNum,
618 const MCOperand &Op = MI->getOperand(OpNum);
619 O << ARM_PROC::IModToString(Op.getImm());
622 void ARMInstPrinter::printCPSIFlag(const MCInst *MI, unsigned OpNum,
624 const MCOperand &Op = MI->getOperand(OpNum);
625 unsigned IFlags = Op.getImm();
626 for (int i=2; i >= 0; --i)
627 if (IFlags & (1 << i))
628 O << ARM_PROC::IFlagsToString(1 << i);
634 void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
636 const MCOperand &Op = MI->getOperand(OpNum);
637 unsigned SpecRegRBit = Op.getImm() >> 4;
638 unsigned Mask = Op.getImm() & 0xf;
640 if (getAvailableFeatures() & ARM::FeatureMClass) {
641 switch (Op.getImm()) {
642 default: assert(0 && "Unexpected mask value!");
643 case 0: O << "apsr"; return;
644 case 1: O << "iapsr"; return;
645 case 2: O << "eapsr"; return;
646 case 3: O << "xpsr"; return;
647 case 5: O << "ipsr"; return;
648 case 6: O << "epsr"; return;
649 case 7: O << "iepsr"; return;
650 case 8: O << "msp"; return;
651 case 9: O << "psp"; return;
652 case 16: O << "primask"; return;
653 case 17: O << "basepri"; return;
654 case 18: O << "basepri_max"; return;
655 case 19: O << "faultmask"; return;
656 case 20: O << "control"; return;
660 // As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as
661 // APSR_nzcvq, APSR_g and APSRnzcvqg, respectively.
662 if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) {
666 case 4: O << "g"; return;
667 case 8: O << "nzcvq"; return;
668 case 12: O << "nzcvqg"; return;
670 llvm_unreachable("Unexpected mask value!");
680 if (Mask & 8) O << 'f';
681 if (Mask & 4) O << 's';
682 if (Mask & 2) O << 'x';
683 if (Mask & 1) O << 'c';
687 void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
689 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
691 O << ARMCondCodeToString(CC);
694 void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI,
697 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
698 O << ARMCondCodeToString(CC);
701 void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
703 if (MI->getOperand(OpNum).getReg()) {
704 assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
705 "Expect ARM CPSR register!");
710 void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
712 O << MI->getOperand(OpNum).getImm();
715 void ARMInstPrinter::printPImmediate(const MCInst *MI, unsigned OpNum,
717 O << "p" << MI->getOperand(OpNum).getImm();
720 void ARMInstPrinter::printCImmediate(const MCInst *MI, unsigned OpNum,
722 O << "c" << MI->getOperand(OpNum).getImm();
725 void ARMInstPrinter::printCoprocOptionImm(const MCInst *MI, unsigned OpNum,
727 O << "{" << MI->getOperand(OpNum).getImm() << "}";
730 void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
732 llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
735 void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
737 O << "#" << MI->getOperand(OpNum).getImm() * 4;
740 void ARMInstPrinter::printThumbSRImm(const MCInst *MI, unsigned OpNum,
742 unsigned Imm = MI->getOperand(OpNum).getImm();
743 O << "#" << (Imm == 0 ? 32 : Imm);
746 void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
748 // (3 - the number of trailing zeros) is the number of then / else.
749 unsigned Mask = MI->getOperand(OpNum).getImm();
750 unsigned CondBit0 = Mask >> 4 & 1;
751 unsigned NumTZ = CountTrailingZeros_32(Mask);
752 assert(NumTZ <= 3 && "Invalid IT mask!");
753 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
754 bool T = ((Mask >> Pos) & 1) == CondBit0;
762 void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
764 const MCOperand &MO1 = MI->getOperand(Op);
765 const MCOperand &MO2 = MI->getOperand(Op + 1);
767 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
768 printOperand(MI, Op, O);
772 O << "[" << getRegisterName(MO1.getReg());
773 if (unsigned RegNum = MO2.getReg())
774 O << ", " << getRegisterName(RegNum);
778 void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI,
782 const MCOperand &MO1 = MI->getOperand(Op);
783 const MCOperand &MO2 = MI->getOperand(Op + 1);
785 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
786 printOperand(MI, Op, O);
790 O << "[" << getRegisterName(MO1.getReg());
791 if (unsigned ImmOffs = MO2.getImm())
792 O << ", #" << ImmOffs * Scale;
796 void ARMInstPrinter::printThumbAddrModeImm5S1Operand(const MCInst *MI,
799 printThumbAddrModeImm5SOperand(MI, Op, O, 1);
802 void ARMInstPrinter::printThumbAddrModeImm5S2Operand(const MCInst *MI,
805 printThumbAddrModeImm5SOperand(MI, Op, O, 2);
808 void ARMInstPrinter::printThumbAddrModeImm5S4Operand(const MCInst *MI,
811 printThumbAddrModeImm5SOperand(MI, Op, O, 4);
814 void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
816 printThumbAddrModeImm5SOperand(MI, Op, O, 4);
819 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
820 // register with shift forms.
822 // REG IMM, SH_OPC - e.g. R5, LSL #3
823 void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
825 const MCOperand &MO1 = MI->getOperand(OpNum);
826 const MCOperand &MO2 = MI->getOperand(OpNum+1);
828 unsigned Reg = MO1.getReg();
829 O << getRegisterName(Reg);
831 // Print the shift opc.
832 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
833 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
834 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
835 if (ShOpc != ARM_AM::rrx)
836 O << " #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
839 void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
841 const MCOperand &MO1 = MI->getOperand(OpNum);
842 const MCOperand &MO2 = MI->getOperand(OpNum+1);
844 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
845 printOperand(MI, OpNum, O);
849 O << "[" << getRegisterName(MO1.getReg());
851 int32_t OffImm = (int32_t)MO2.getImm();
852 bool isSub = OffImm < 0;
853 // Special value for #-0. All others are normal.
854 if (OffImm == INT32_MIN)
857 O << ", #-" << -OffImm;
859 O << ", #" << OffImm;
863 void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
866 const MCOperand &MO1 = MI->getOperand(OpNum);
867 const MCOperand &MO2 = MI->getOperand(OpNum+1);
869 O << "[" << getRegisterName(MO1.getReg());
871 int32_t OffImm = (int32_t)MO2.getImm();
873 if (OffImm == INT32_MIN)
876 O << ", #-" << -OffImm;
878 O << ", #" << OffImm;
882 void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
885 const MCOperand &MO1 = MI->getOperand(OpNum);
886 const MCOperand &MO2 = MI->getOperand(OpNum+1);
888 O << "[" << getRegisterName(MO1.getReg());
890 int32_t OffImm = (int32_t)MO2.getImm() / 4;
893 O << ", #-" << -OffImm * 4;
895 O << ", #" << OffImm * 4;
899 void ARMInstPrinter::printT2AddrModeImm0_1020s4Operand(const MCInst *MI,
902 const MCOperand &MO1 = MI->getOperand(OpNum);
903 const MCOperand &MO2 = MI->getOperand(OpNum+1);
905 O << "[" << getRegisterName(MO1.getReg());
907 O << ", #" << MO2.getImm() * 4;
911 void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI,
914 const MCOperand &MO1 = MI->getOperand(OpNum);
915 int32_t OffImm = (int32_t)MO1.getImm();
918 O << ", #-" << -OffImm;
920 O << ", #" << OffImm;
923 void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI,
926 const MCOperand &MO1 = MI->getOperand(OpNum);
927 int32_t OffImm = (int32_t)MO1.getImm() / 4;
932 O << "#-" << -OffImm * 4;
934 O << "#" << OffImm * 4;
938 void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
941 const MCOperand &MO1 = MI->getOperand(OpNum);
942 const MCOperand &MO2 = MI->getOperand(OpNum+1);
943 const MCOperand &MO3 = MI->getOperand(OpNum+2);
945 O << "[" << getRegisterName(MO1.getReg());
947 assert(MO2.getReg() && "Invalid so_reg load / store address!");
948 O << ", " << getRegisterName(MO2.getReg());
950 unsigned ShAmt = MO3.getImm();
952 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
953 O << ", lsl #" << ShAmt;
958 void ARMInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
960 const MCOperand &MO = MI->getOperand(OpNum);
961 O << '#' << ARM_AM::getFPImmFloat(MO.getImm());
964 void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
966 unsigned EncodedImm = MI->getOperand(OpNum).getImm();
968 uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
973 void ARMInstPrinter::printImmPlusOneOperand(const MCInst *MI, unsigned OpNum,
975 unsigned Imm = MI->getOperand(OpNum).getImm();
979 void ARMInstPrinter::printRotImmOperand(const MCInst *MI, unsigned OpNum,
981 unsigned Imm = MI->getOperand(OpNum).getImm();
986 default: assert (0 && "illegal ror immediate!");
987 case 1: O << "8"; break;
988 case 2: O << "16"; break;
989 case 3: O << "24"; break;
993 void ARMInstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
995 O << "[" << MI->getOperand(OpNum).getImm() << "]";
998 void ARMInstPrinter::printVectorListOne(const MCInst *MI, unsigned OpNum,
1000 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "}";
1003 void ARMInstPrinter::printVectorListTwo(const MCInst *MI, unsigned OpNum,
1005 // Normally, it's not safe to use register enum values directly with
1006 // addition to get the next register, but for VFP registers, the
1007 // sort order is guaranteed because they're all of the form D<n>.
1008 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", "
1009 << getRegisterName(MI->getOperand(OpNum).getReg() + 1) << "}";
1012 void ARMInstPrinter::printVectorListThree(const MCInst *MI, unsigned OpNum,
1014 // Normally, it's not safe to use register enum values directly with
1015 // addition to get the next register, but for VFP registers, the
1016 // sort order is guaranteed because they're all of the form D<n>.
1017 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", "
1018 << getRegisterName(MI->getOperand(OpNum).getReg() + 1) << ", "
1019 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "}";
1022 void ARMInstPrinter::printVectorListFour(const MCInst *MI, unsigned OpNum,
1024 // Normally, it's not safe to use register enum values directly with
1025 // addition to get the next register, but for VFP registers, the
1026 // sort order is guaranteed because they're all of the form D<n>.
1027 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", "
1028 << getRegisterName(MI->getOperand(OpNum).getReg() + 1) << ", "
1029 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << ", "
1030 << getRegisterName(MI->getOperand(OpNum).getReg() + 3) << "}";
1033 void ARMInstPrinter::printVectorListOneAllLanes(const MCInst *MI,
1036 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[]}";
1039 void ARMInstPrinter::printVectorListTwoAllLanes(const MCInst *MI,
1042 // Normally, it's not safe to use register enum values directly with
1043 // addition to get the next register, but for VFP registers, the
1044 // sort order is guaranteed because they're all of the form D<n>.
1045 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], "
1046 << getRegisterName(MI->getOperand(OpNum).getReg() + 1) << "[]}";