1 //===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class prints an ARM MCInst to a .s file.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "asm-printer"
15 #include "ARMInstPrinter.h"
16 #include "MCTargetDesc/ARMBaseInfo.h"
17 #include "MCTargetDesc/ARMAddressingModes.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCAsmInfo.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/Support/raw_ostream.h"
26 #include "ARMGenAsmWriter.inc"
28 /// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing.
30 /// getSORegOffset returns an integer from 0-31, representing '32' as 0.
31 static unsigned translateShiftImm(unsigned imm) {
38 ARMInstPrinter::ARMInstPrinter(const MCAsmInfo &MAI,
39 const MCInstrInfo &MII,
40 const MCRegisterInfo &MRI,
41 const MCSubtargetInfo &STI) :
42 MCInstPrinter(MAI, MII, MRI) {
43 // Initialize the set of available features.
44 setAvailableFeatures(STI.getFeatureBits());
47 void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
48 OS << getRegisterName(RegNo);
51 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
53 unsigned Opcode = MI->getOpcode();
55 // Check for HINT instructions w/ canonical names.
56 if (Opcode == ARM::HINT || Opcode == ARM::t2HINT) {
57 switch (MI->getOperand(0).getImm()) {
58 case 0: O << "\tnop"; break;
59 case 1: O << "\tyield"; break;
60 case 2: O << "\twfe"; break;
61 case 3: O << "\twfi"; break;
62 case 4: O << "\tsev"; break;
64 // Anything else should just print normally.
65 printInstruction(MI, O);
66 printAnnotation(O, Annot);
69 printPredicateOperand(MI, 1, O);
70 if (Opcode == ARM::t2HINT)
72 printAnnotation(O, Annot);
76 // Check for MOVs and print canonical forms, instead.
77 if (Opcode == ARM::MOVsr) {
78 // FIXME: Thumb variants?
79 const MCOperand &Dst = MI->getOperand(0);
80 const MCOperand &MO1 = MI->getOperand(1);
81 const MCOperand &MO2 = MI->getOperand(2);
82 const MCOperand &MO3 = MI->getOperand(3);
84 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
85 printSBitModifierOperand(MI, 6, O);
86 printPredicateOperand(MI, 4, O);
88 O << '\t' << getRegisterName(Dst.getReg())
89 << ", " << getRegisterName(MO1.getReg());
91 O << ", " << getRegisterName(MO2.getReg());
92 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
93 printAnnotation(O, Annot);
97 if (Opcode == ARM::MOVsi) {
98 // FIXME: Thumb variants?
99 const MCOperand &Dst = MI->getOperand(0);
100 const MCOperand &MO1 = MI->getOperand(1);
101 const MCOperand &MO2 = MI->getOperand(2);
103 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()));
104 printSBitModifierOperand(MI, 5, O);
105 printPredicateOperand(MI, 3, O);
107 O << '\t' << getRegisterName(Dst.getReg())
108 << ", " << getRegisterName(MO1.getReg());
110 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) {
111 printAnnotation(O, Annot);
115 O << ", #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
116 printAnnotation(O, Annot);
122 if ((Opcode == ARM::STMDB_UPD || Opcode == ARM::t2STMDB_UPD) &&
123 MI->getOperand(0).getReg() == ARM::SP &&
124 MI->getNumOperands() > 5) {
125 // Should only print PUSH if there are at least two registers in the list.
127 printPredicateOperand(MI, 2, O);
128 if (Opcode == ARM::t2STMDB_UPD)
131 printRegisterList(MI, 4, O);
132 printAnnotation(O, Annot);
135 if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP &&
136 MI->getOperand(3).getImm() == -4) {
138 printPredicateOperand(MI, 4, O);
139 O << "\t{" << getRegisterName(MI->getOperand(1).getReg()) << "}";
140 printAnnotation(O, Annot);
145 if ((Opcode == ARM::LDMIA_UPD || Opcode == ARM::t2LDMIA_UPD) &&
146 MI->getOperand(0).getReg() == ARM::SP &&
147 MI->getNumOperands() > 5) {
148 // Should only print POP if there are at least two registers in the list.
150 printPredicateOperand(MI, 2, O);
151 if (Opcode == ARM::t2LDMIA_UPD)
154 printRegisterList(MI, 4, O);
155 printAnnotation(O, Annot);
158 if (Opcode == ARM::LDR_POST_IMM && MI->getOperand(2).getReg() == ARM::SP &&
159 MI->getOperand(4).getImm() == 4) {
161 printPredicateOperand(MI, 5, O);
162 O << "\t{" << getRegisterName(MI->getOperand(0).getReg()) << "}";
163 printAnnotation(O, Annot);
169 if ((Opcode == ARM::VSTMSDB_UPD || Opcode == ARM::VSTMDDB_UPD) &&
170 MI->getOperand(0).getReg() == ARM::SP) {
171 O << '\t' << "vpush";
172 printPredicateOperand(MI, 2, O);
174 printRegisterList(MI, 4, O);
175 printAnnotation(O, Annot);
180 if ((Opcode == ARM::VLDMSIA_UPD || Opcode == ARM::VLDMDIA_UPD) &&
181 MI->getOperand(0).getReg() == ARM::SP) {
183 printPredicateOperand(MI, 2, O);
185 printRegisterList(MI, 4, O);
186 printAnnotation(O, Annot);
190 if (Opcode == ARM::tLDMIA) {
191 bool Writeback = true;
192 unsigned BaseReg = MI->getOperand(0).getReg();
193 for (unsigned i = 3; i < MI->getNumOperands(); ++i) {
194 if (MI->getOperand(i).getReg() == BaseReg)
200 printPredicateOperand(MI, 1, O);
201 O << '\t' << getRegisterName(BaseReg);
202 if (Writeback) O << "!";
204 printRegisterList(MI, 3, O);
205 printAnnotation(O, Annot);
210 if (Opcode == ARM::tMOVr && MI->getOperand(0).getReg() == ARM::R8 &&
211 MI->getOperand(1).getReg() == ARM::R8) {
213 printPredicateOperand(MI, 2, O);
214 printAnnotation(O, Annot);
218 printInstruction(MI, O);
219 printAnnotation(O, Annot);
222 void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
224 const MCOperand &Op = MI->getOperand(OpNo);
226 unsigned Reg = Op.getReg();
227 O << getRegisterName(Reg);
228 } else if (Op.isImm()) {
229 O << '#' << Op.getImm();
231 assert(Op.isExpr() && "unknown operand kind in printOperand");
232 // If a symbolic branch target was added as a constant expression then print
233 // that address in hex. And only print 32 unsigned bits for the address.
234 const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr());
236 if (BranchTarget && BranchTarget->EvaluateAsAbsolute(Address)) {
238 O.write_hex((uint32_t)Address);
241 // Otherwise, just print the expression.
247 void ARMInstPrinter::printT2LdrLabelOperand(const MCInst *MI, unsigned OpNum,
249 const MCOperand &MO1 = MI->getOperand(OpNum);
252 else if (MO1.isImm())
253 O << "[pc, #" << MO1.getImm() << "]";
255 llvm_unreachable("Unknown LDR label operand?");
258 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
259 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
261 // REG REG 0,SH_OPC - e.g. R5, ROR R3
262 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
263 void ARMInstPrinter::printSORegRegOperand(const MCInst *MI, unsigned OpNum,
265 const MCOperand &MO1 = MI->getOperand(OpNum);
266 const MCOperand &MO2 = MI->getOperand(OpNum+1);
267 const MCOperand &MO3 = MI->getOperand(OpNum+2);
269 O << getRegisterName(MO1.getReg());
271 // Print the shift opc.
272 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
273 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
274 if (ShOpc == ARM_AM::rrx)
277 O << ' ' << getRegisterName(MO2.getReg());
278 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
281 void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum,
283 const MCOperand &MO1 = MI->getOperand(OpNum);
284 const MCOperand &MO2 = MI->getOperand(OpNum+1);
286 O << getRegisterName(MO1.getReg());
288 // Print the shift opc.
289 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
290 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
291 if (ShOpc == ARM_AM::rrx)
293 O << " #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
297 //===--------------------------------------------------------------------===//
298 // Addressing Mode #2
299 //===--------------------------------------------------------------------===//
301 void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
303 const MCOperand &MO1 = MI->getOperand(Op);
304 const MCOperand &MO2 = MI->getOperand(Op+1);
305 const MCOperand &MO3 = MI->getOperand(Op+2);
307 O << "[" << getRegisterName(MO1.getReg());
310 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
312 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
313 << ARM_AM::getAM2Offset(MO3.getImm());
319 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
320 << getRegisterName(MO2.getReg());
322 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
324 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
329 void ARMInstPrinter::printAM2PostIndexOp(const MCInst *MI, unsigned Op,
331 const MCOperand &MO1 = MI->getOperand(Op);
332 const MCOperand &MO2 = MI->getOperand(Op+1);
333 const MCOperand &MO3 = MI->getOperand(Op+2);
335 O << "[" << getRegisterName(MO1.getReg()) << "], ";
338 unsigned ImmOffs = ARM_AM::getAM2Offset(MO3.getImm());
340 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
345 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
346 << getRegisterName(MO2.getReg());
348 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
350 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
354 void ARMInstPrinter::printAddrModeTBB(const MCInst *MI, unsigned Op,
356 const MCOperand &MO1 = MI->getOperand(Op);
357 const MCOperand &MO2 = MI->getOperand(Op+1);
358 O << "[" << getRegisterName(MO1.getReg()) << ", "
359 << getRegisterName(MO2.getReg()) << "]";
362 void ARMInstPrinter::printAddrModeTBH(const MCInst *MI, unsigned Op,
364 const MCOperand &MO1 = MI->getOperand(Op);
365 const MCOperand &MO2 = MI->getOperand(Op+1);
366 O << "[" << getRegisterName(MO1.getReg()) << ", "
367 << getRegisterName(MO2.getReg()) << ", lsl #1]";
370 void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
372 const MCOperand &MO1 = MI->getOperand(Op);
374 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
375 printOperand(MI, Op, O);
379 const MCOperand &MO3 = MI->getOperand(Op+2);
380 unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm());
382 if (IdxMode == ARMII::IndexModePost) {
383 printAM2PostIndexOp(MI, Op, O);
386 printAM2PreOrOffsetIndexOp(MI, Op, O);
389 void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
392 const MCOperand &MO1 = MI->getOperand(OpNum);
393 const MCOperand &MO2 = MI->getOperand(OpNum+1);
396 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
398 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
403 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
404 << getRegisterName(MO1.getReg());
406 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
408 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
412 //===--------------------------------------------------------------------===//
413 // Addressing Mode #3
414 //===--------------------------------------------------------------------===//
416 void ARMInstPrinter::printAM3PostIndexOp(const MCInst *MI, unsigned Op,
418 const MCOperand &MO1 = MI->getOperand(Op);
419 const MCOperand &MO2 = MI->getOperand(Op+1);
420 const MCOperand &MO3 = MI->getOperand(Op+2);
422 O << "[" << getRegisterName(MO1.getReg()) << "], ";
425 O << (char)ARM_AM::getAM3Op(MO3.getImm())
426 << getRegisterName(MO2.getReg());
430 unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
432 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
436 void ARMInstPrinter::printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
438 const MCOperand &MO1 = MI->getOperand(Op);
439 const MCOperand &MO2 = MI->getOperand(Op+1);
440 const MCOperand &MO3 = MI->getOperand(Op+2);
442 O << '[' << getRegisterName(MO1.getReg());
445 O << ", " << getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
446 << getRegisterName(MO2.getReg()) << ']';
450 //If the op is sub we have to print the immediate even if it is 0
451 unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
452 ARM_AM::AddrOpc op = ARM_AM::getAM3Op(MO3.getImm());
454 if (ImmOffs || (op == ARM_AM::sub))
456 << ARM_AM::getAddrOpcStr(op)
461 void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned Op,
463 const MCOperand &MO1 = MI->getOperand(Op);
464 if (!MO1.isReg()) { // For label symbolic references.
465 printOperand(MI, Op, O);
469 const MCOperand &MO3 = MI->getOperand(Op+2);
470 unsigned IdxMode = ARM_AM::getAM3IdxMode(MO3.getImm());
472 if (IdxMode == ARMII::IndexModePost) {
473 printAM3PostIndexOp(MI, Op, O);
476 printAM3PreOrOffsetIndexOp(MI, Op, O);
479 void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
482 const MCOperand &MO1 = MI->getOperand(OpNum);
483 const MCOperand &MO2 = MI->getOperand(OpNum+1);
486 O << getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
487 << getRegisterName(MO1.getReg());
491 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
493 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
497 void ARMInstPrinter::printPostIdxImm8Operand(const MCInst *MI,
500 const MCOperand &MO = MI->getOperand(OpNum);
501 unsigned Imm = MO.getImm();
502 O << '#' << ((Imm & 256) ? "" : "-") << (Imm & 0xff);
505 void ARMInstPrinter::printPostIdxRegOperand(const MCInst *MI, unsigned OpNum,
507 const MCOperand &MO1 = MI->getOperand(OpNum);
508 const MCOperand &MO2 = MI->getOperand(OpNum+1);
510 O << (MO2.getImm() ? "" : "-") << getRegisterName(MO1.getReg());
513 void ARMInstPrinter::printPostIdxImm8s4Operand(const MCInst *MI,
516 const MCOperand &MO = MI->getOperand(OpNum);
517 unsigned Imm = MO.getImm();
518 O << '#' << ((Imm & 256) ? "" : "-") << ((Imm & 0xff) << 2);
522 void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
524 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MI->getOperand(OpNum)
526 O << ARM_AM::getAMSubModeStr(Mode);
529 void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
531 const MCOperand &MO1 = MI->getOperand(OpNum);
532 const MCOperand &MO2 = MI->getOperand(OpNum+1);
534 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
535 printOperand(MI, OpNum, O);
539 O << "[" << getRegisterName(MO1.getReg());
541 unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm());
542 unsigned Op = ARM_AM::getAM5Op(MO2.getImm());
543 if (ImmOffs || Op == ARM_AM::sub) {
545 << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
551 void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
553 const MCOperand &MO1 = MI->getOperand(OpNum);
554 const MCOperand &MO2 = MI->getOperand(OpNum+1);
556 O << "[" << getRegisterName(MO1.getReg());
558 // FIXME: Both darwin as and GNU as violate ARM docs here.
559 O << ", :" << (MO2.getImm() << 3);
564 void ARMInstPrinter::printAddrMode7Operand(const MCInst *MI, unsigned OpNum,
566 const MCOperand &MO1 = MI->getOperand(OpNum);
567 O << "[" << getRegisterName(MO1.getReg()) << "]";
570 void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
573 const MCOperand &MO = MI->getOperand(OpNum);
574 if (MO.getReg() == 0)
577 O << ", " << getRegisterName(MO.getReg());
580 void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
583 const MCOperand &MO = MI->getOperand(OpNum);
584 uint32_t v = ~MO.getImm();
585 int32_t lsb = CountTrailingZeros_32(v);
586 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
587 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
588 O << '#' << lsb << ", #" << width;
591 void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
593 unsigned val = MI->getOperand(OpNum).getImm();
594 O << ARM_MB::MemBOptToString(val);
597 void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
599 unsigned ShiftOp = MI->getOperand(OpNum).getImm();
600 bool isASR = (ShiftOp & (1 << 5)) != 0;
601 unsigned Amt = ShiftOp & 0x1f;
603 O << ", asr #" << (Amt == 0 ? 32 : Amt);
605 O << ", lsl #" << Amt;
608 void ARMInstPrinter::printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum,
610 unsigned Imm = MI->getOperand(OpNum).getImm();
613 assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!");
614 O << ", lsl #" << Imm;
617 void ARMInstPrinter::printPKHASRShiftImm(const MCInst *MI, unsigned OpNum,
619 unsigned Imm = MI->getOperand(OpNum).getImm();
620 // A shift amount of 32 is encoded as 0.
623 assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!");
624 O << ", asr #" << Imm;
627 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
630 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
631 if (i != OpNum) O << ", ";
632 O << getRegisterName(MI->getOperand(i).getReg());
637 void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
639 const MCOperand &Op = MI->getOperand(OpNum);
646 void ARMInstPrinter::printCPSIMod(const MCInst *MI, unsigned OpNum,
648 const MCOperand &Op = MI->getOperand(OpNum);
649 O << ARM_PROC::IModToString(Op.getImm());
652 void ARMInstPrinter::printCPSIFlag(const MCInst *MI, unsigned OpNum,
654 const MCOperand &Op = MI->getOperand(OpNum);
655 unsigned IFlags = Op.getImm();
656 for (int i=2; i >= 0; --i)
657 if (IFlags & (1 << i))
658 O << ARM_PROC::IFlagsToString(1 << i);
664 void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
666 const MCOperand &Op = MI->getOperand(OpNum);
667 unsigned SpecRegRBit = Op.getImm() >> 4;
668 unsigned Mask = Op.getImm() & 0xf;
670 if (getAvailableFeatures() & ARM::FeatureMClass) {
671 unsigned SYSm = Op.getImm();
672 unsigned Opcode = MI->getOpcode();
673 // For reads of the special registers ignore the "mask encoding" bits
674 // which are only for writes.
675 if (Opcode == ARM::t2MRS_M)
678 default: llvm_unreachable("Unexpected mask value!");
680 case 0x800: O << "apsr"; return; // with _nzcvq bits is an alias for aspr
681 case 0x400: O << "apsr_g"; return;
682 case 0xc00: O << "apsr_nzcvqg"; return;
684 case 0x801: O << "iapsr"; return; // with _nzcvq bits is an alias for iapsr
685 case 0x401: O << "iapsr_g"; return;
686 case 0xc01: O << "iapsr_nzcvqg"; return;
688 case 0x802: O << "eapsr"; return; // with _nzcvq bits is an alias for eapsr
689 case 0x402: O << "eapsr_g"; return;
690 case 0xc02: O << "eapsr_nzcvqg"; return;
692 case 0x803: O << "xpsr"; return; // with _nzcvq bits is an alias for xpsr
693 case 0x403: O << "xpsr_g"; return;
694 case 0xc03: O << "xpsr_nzcvqg"; return;
696 case 0x805: O << "ipsr"; return;
698 case 0x806: O << "epsr"; return;
700 case 0x807: O << "iepsr"; return;
702 case 0x808: O << "msp"; return;
704 case 0x809: O << "psp"; return;
706 case 0x810: O << "primask"; return;
708 case 0x811: O << "basepri"; return;
710 case 0x812: O << "basepri_max"; return;
712 case 0x813: O << "faultmask"; return;
714 case 0x814: O << "control"; return;
718 // As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as
719 // APSR_nzcvq, APSR_g and APSRnzcvqg, respectively.
720 if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) {
723 default: llvm_unreachable("Unexpected mask value!");
724 case 4: O << "g"; return;
725 case 8: O << "nzcvq"; return;
726 case 12: O << "nzcvqg"; return;
737 if (Mask & 8) O << 'f';
738 if (Mask & 4) O << 's';
739 if (Mask & 2) O << 'x';
740 if (Mask & 1) O << 'c';
744 void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
746 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
747 // Handle the undefined 15 CC value here for printing so we don't abort().
748 if ((unsigned)CC == 15)
750 else if (CC != ARMCC::AL)
751 O << ARMCondCodeToString(CC);
754 void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI,
757 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
758 O << ARMCondCodeToString(CC);
761 void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
763 if (MI->getOperand(OpNum).getReg()) {
764 assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
765 "Expect ARM CPSR register!");
770 void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
772 O << MI->getOperand(OpNum).getImm();
775 void ARMInstPrinter::printPImmediate(const MCInst *MI, unsigned OpNum,
777 O << "p" << MI->getOperand(OpNum).getImm();
780 void ARMInstPrinter::printCImmediate(const MCInst *MI, unsigned OpNum,
782 O << "c" << MI->getOperand(OpNum).getImm();
785 void ARMInstPrinter::printCoprocOptionImm(const MCInst *MI, unsigned OpNum,
787 O << "{" << MI->getOperand(OpNum).getImm() << "}";
790 void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
792 llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
795 void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
797 O << "#" << MI->getOperand(OpNum).getImm() * 4;
800 void ARMInstPrinter::printThumbSRImm(const MCInst *MI, unsigned OpNum,
802 unsigned Imm = MI->getOperand(OpNum).getImm();
803 O << "#" << (Imm == 0 ? 32 : Imm);
806 void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
808 // (3 - the number of trailing zeros) is the number of then / else.
809 unsigned Mask = MI->getOperand(OpNum).getImm();
810 unsigned Firstcond = MI->getOperand(OpNum-1).getImm();
811 unsigned CondBit0 = Firstcond & 1;
812 unsigned NumTZ = CountTrailingZeros_32(Mask);
813 assert(NumTZ <= 3 && "Invalid IT mask!");
814 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
815 bool T = ((Mask >> Pos) & 1) == CondBit0;
823 void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
825 const MCOperand &MO1 = MI->getOperand(Op);
826 const MCOperand &MO2 = MI->getOperand(Op + 1);
828 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
829 printOperand(MI, Op, O);
833 O << "[" << getRegisterName(MO1.getReg());
834 if (unsigned RegNum = MO2.getReg())
835 O << ", " << getRegisterName(RegNum);
839 void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI,
843 const MCOperand &MO1 = MI->getOperand(Op);
844 const MCOperand &MO2 = MI->getOperand(Op + 1);
846 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
847 printOperand(MI, Op, O);
851 O << "[" << getRegisterName(MO1.getReg());
852 if (unsigned ImmOffs = MO2.getImm())
853 O << ", #" << ImmOffs * Scale;
857 void ARMInstPrinter::printThumbAddrModeImm5S1Operand(const MCInst *MI,
860 printThumbAddrModeImm5SOperand(MI, Op, O, 1);
863 void ARMInstPrinter::printThumbAddrModeImm5S2Operand(const MCInst *MI,
866 printThumbAddrModeImm5SOperand(MI, Op, O, 2);
869 void ARMInstPrinter::printThumbAddrModeImm5S4Operand(const MCInst *MI,
872 printThumbAddrModeImm5SOperand(MI, Op, O, 4);
875 void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
877 printThumbAddrModeImm5SOperand(MI, Op, O, 4);
880 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
881 // register with shift forms.
883 // REG IMM, SH_OPC - e.g. R5, LSL #3
884 void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
886 const MCOperand &MO1 = MI->getOperand(OpNum);
887 const MCOperand &MO2 = MI->getOperand(OpNum+1);
889 unsigned Reg = MO1.getReg();
890 O << getRegisterName(Reg);
892 // Print the shift opc.
893 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
894 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
895 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
896 if (ShOpc != ARM_AM::rrx)
897 O << " #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
900 void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
902 const MCOperand &MO1 = MI->getOperand(OpNum);
903 const MCOperand &MO2 = MI->getOperand(OpNum+1);
905 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
906 printOperand(MI, OpNum, O);
910 O << "[" << getRegisterName(MO1.getReg());
912 int32_t OffImm = (int32_t)MO2.getImm();
913 bool isSub = OffImm < 0;
914 // Special value for #-0. All others are normal.
915 if (OffImm == INT32_MIN)
918 O << ", #-" << -OffImm;
920 O << ", #" << OffImm;
924 void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
927 const MCOperand &MO1 = MI->getOperand(OpNum);
928 const MCOperand &MO2 = MI->getOperand(OpNum+1);
930 O << "[" << getRegisterName(MO1.getReg());
932 int32_t OffImm = (int32_t)MO2.getImm();
934 if (OffImm == INT32_MIN)
937 O << ", #-" << -OffImm;
939 O << ", #" << OffImm;
943 void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
946 const MCOperand &MO1 = MI->getOperand(OpNum);
947 const MCOperand &MO2 = MI->getOperand(OpNum+1);
949 if (!MO1.isReg()) { // For label symbolic references.
950 printOperand(MI, OpNum, O);
954 O << "[" << getRegisterName(MO1.getReg());
956 int32_t OffImm = (int32_t)MO2.getImm() / 4;
959 O << ", #-" << -OffImm * 4;
961 O << ", #" << OffImm * 4;
965 void ARMInstPrinter::printT2AddrModeImm0_1020s4Operand(const MCInst *MI,
968 const MCOperand &MO1 = MI->getOperand(OpNum);
969 const MCOperand &MO2 = MI->getOperand(OpNum+1);
971 O << "[" << getRegisterName(MO1.getReg());
973 O << ", #" << MO2.getImm() * 4;
977 void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI,
980 const MCOperand &MO1 = MI->getOperand(OpNum);
981 int32_t OffImm = (int32_t)MO1.getImm();
984 O << ", #-" << -OffImm;
986 O << ", #" << OffImm;
989 void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI,
992 const MCOperand &MO1 = MI->getOperand(OpNum);
993 int32_t OffImm = (int32_t)MO1.getImm() / 4;
998 O << "#-" << -OffImm * 4;
1000 O << "#" << OffImm * 4;
1004 void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
1007 const MCOperand &MO1 = MI->getOperand(OpNum);
1008 const MCOperand &MO2 = MI->getOperand(OpNum+1);
1009 const MCOperand &MO3 = MI->getOperand(OpNum+2);
1011 O << "[" << getRegisterName(MO1.getReg());
1013 assert(MO2.getReg() && "Invalid so_reg load / store address!");
1014 O << ", " << getRegisterName(MO2.getReg());
1016 unsigned ShAmt = MO3.getImm();
1018 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
1019 O << ", lsl #" << ShAmt;
1024 void ARMInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
1026 const MCOperand &MO = MI->getOperand(OpNum);
1027 O << '#' << ARM_AM::getFPImmFloat(MO.getImm());
1030 void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
1032 unsigned EncodedImm = MI->getOperand(OpNum).getImm();
1034 uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
1039 void ARMInstPrinter::printImmPlusOneOperand(const MCInst *MI, unsigned OpNum,
1041 unsigned Imm = MI->getOperand(OpNum).getImm();
1042 O << "#" << Imm + 1;
1045 void ARMInstPrinter::printRotImmOperand(const MCInst *MI, unsigned OpNum,
1047 unsigned Imm = MI->getOperand(OpNum).getImm();
1052 default: assert (0 && "illegal ror immediate!");
1053 case 1: O << "8"; break;
1054 case 2: O << "16"; break;
1055 case 3: O << "24"; break;
1059 void ARMInstPrinter::printFBits16(const MCInst *MI, unsigned OpNum,
1061 O << "#" << 16 - MI->getOperand(OpNum).getImm();
1064 void ARMInstPrinter::printFBits32(const MCInst *MI, unsigned OpNum,
1066 O << "#" << 32 - MI->getOperand(OpNum).getImm();
1069 void ARMInstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
1071 O << "[" << MI->getOperand(OpNum).getImm() << "]";
1074 void ARMInstPrinter::printVectorListOne(const MCInst *MI, unsigned OpNum,
1076 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "}";
1079 void ARMInstPrinter::printVectorListTwo(const MCInst *MI, unsigned OpNum,
1081 unsigned Reg = MI->getOperand(OpNum).getReg();
1082 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1083 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
1084 O << "{" << getRegisterName(Reg0) << ", " << getRegisterName(Reg1) << "}";
1087 void ARMInstPrinter::printVectorListTwoSpaced(const MCInst *MI,
1090 unsigned Reg = MI->getOperand(OpNum).getReg();
1091 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1092 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
1093 O << "{" << getRegisterName(Reg0) << ", " << getRegisterName(Reg1) << "}";
1096 void ARMInstPrinter::printVectorListThree(const MCInst *MI, unsigned OpNum,
1098 // Normally, it's not safe to use register enum values directly with
1099 // addition to get the next register, but for VFP registers, the
1100 // sort order is guaranteed because they're all of the form D<n>.
1101 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", "
1102 << getRegisterName(MI->getOperand(OpNum).getReg() + 1) << ", "
1103 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "}";
1106 void ARMInstPrinter::printVectorListFour(const MCInst *MI, unsigned OpNum,
1108 // Normally, it's not safe to use register enum values directly with
1109 // addition to get the next register, but for VFP registers, the
1110 // sort order is guaranteed because they're all of the form D<n>.
1111 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", "
1112 << getRegisterName(MI->getOperand(OpNum).getReg() + 1) << ", "
1113 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << ", "
1114 << getRegisterName(MI->getOperand(OpNum).getReg() + 3) << "}";
1117 void ARMInstPrinter::printVectorListOneAllLanes(const MCInst *MI,
1120 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[]}";
1123 void ARMInstPrinter::printVectorListTwoAllLanes(const MCInst *MI,
1126 unsigned Reg = MI->getOperand(OpNum).getReg();
1127 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1128 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
1129 O << "{" << getRegisterName(Reg0) << "[], " << getRegisterName(Reg1) << "[]}";
1132 void ARMInstPrinter::printVectorListThreeAllLanes(const MCInst *MI,
1135 // Normally, it's not safe to use register enum values directly with
1136 // addition to get the next register, but for VFP registers, the
1137 // sort order is guaranteed because they're all of the form D<n>.
1138 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], "
1139 << getRegisterName(MI->getOperand(OpNum).getReg() + 1) << "[], "
1140 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "[]}";
1143 void ARMInstPrinter::printVectorListFourAllLanes(const MCInst *MI,
1146 // Normally, it's not safe to use register enum values directly with
1147 // addition to get the next register, but for VFP registers, the
1148 // sort order is guaranteed because they're all of the form D<n>.
1149 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], "
1150 << getRegisterName(MI->getOperand(OpNum).getReg() + 1) << "[], "
1151 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "[], "
1152 << getRegisterName(MI->getOperand(OpNum).getReg() + 3) << "[]}";
1155 void ARMInstPrinter::printVectorListTwoSpacedAllLanes(const MCInst *MI,
1158 unsigned Reg = MI->getOperand(OpNum).getReg();
1159 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1160 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
1161 O << "{" << getRegisterName(Reg0) << "[], " << getRegisterName(Reg1) << "[]}";
1164 void ARMInstPrinter::printVectorListThreeSpacedAllLanes(const MCInst *MI,
1167 // Normally, it's not safe to use register enum values directly with
1168 // addition to get the next register, but for VFP registers, the
1169 // sort order is guaranteed because they're all of the form D<n>.
1170 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], "
1171 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "[], "
1172 << getRegisterName(MI->getOperand(OpNum).getReg() + 4) << "[]}";
1175 void ARMInstPrinter::printVectorListFourSpacedAllLanes(const MCInst *MI,
1178 // Normally, it's not safe to use register enum values directly with
1179 // addition to get the next register, but for VFP registers, the
1180 // sort order is guaranteed because they're all of the form D<n>.
1181 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], "
1182 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "[], "
1183 << getRegisterName(MI->getOperand(OpNum).getReg() + 4) << "[], "
1184 << getRegisterName(MI->getOperand(OpNum).getReg() + 6) << "[]}";
1187 void ARMInstPrinter::printVectorListThreeSpaced(const MCInst *MI,
1190 // Normally, it's not safe to use register enum values directly with
1191 // addition to get the next register, but for VFP registers, the
1192 // sort order is guaranteed because they're all of the form D<n>.
1193 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", "
1194 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << ", "
1195 << getRegisterName(MI->getOperand(OpNum).getReg() + 4) << "}";
1198 void ARMInstPrinter::printVectorListFourSpaced(const MCInst *MI,
1201 // Normally, it's not safe to use register enum values directly with
1202 // addition to get the next register, but for VFP registers, the
1203 // sort order is guaranteed because they're all of the form D<n>.
1204 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", "
1205 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << ", "
1206 << getRegisterName(MI->getOperand(OpNum).getReg() + 4) << ", "
1207 << getRegisterName(MI->getOperand(OpNum).getReg() + 6) << "}";