1 //===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class prints an ARM MCInst to a .s file.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "asm-printer"
15 #include "ARMInstPrinter.h"
16 #include "MCTargetDesc/ARMBaseInfo.h"
17 #include "MCTargetDesc/ARMAddressingModes.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCAsmInfo.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/ADT/StringExtras.h"
22 #include "llvm/Support/raw_ostream.h"
25 #define GET_INSTRUCTION_NAME
26 #include "ARMGenAsmWriter.inc"
28 /// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing.
30 /// getSORegOffset returns an integer from 0-31, but '0' should actually be printed
31 /// 32 as the immediate shouldbe within the range 1-32.
32 static unsigned translateShiftImm(unsigned imm) {
38 StringRef ARMInstPrinter::getOpcodeName(unsigned Opcode) const {
39 return getInstructionName(Opcode);
42 void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
43 OS << getRegisterName(RegNo);
46 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
47 unsigned Opcode = MI->getOpcode();
49 // Check for MOVs and print canonical forms, instead.
50 if (Opcode == ARM::MOVsr) {
51 // FIXME: Thumb variants?
52 const MCOperand &Dst = MI->getOperand(0);
53 const MCOperand &MO1 = MI->getOperand(1);
54 const MCOperand &MO2 = MI->getOperand(2);
55 const MCOperand &MO3 = MI->getOperand(3);
57 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
58 printSBitModifierOperand(MI, 6, O);
59 printPredicateOperand(MI, 4, O);
61 O << '\t' << getRegisterName(Dst.getReg())
62 << ", " << getRegisterName(MO1.getReg());
64 O << ", " << getRegisterName(MO2.getReg());
65 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
69 if (Opcode == ARM::MOVsi) {
70 // FIXME: Thumb variants?
71 const MCOperand &Dst = MI->getOperand(0);
72 const MCOperand &MO1 = MI->getOperand(1);
73 const MCOperand &MO2 = MI->getOperand(2);
75 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()));
76 printSBitModifierOperand(MI, 5, O);
77 printPredicateOperand(MI, 3, O);
79 O << '\t' << getRegisterName(Dst.getReg())
80 << ", " << getRegisterName(MO1.getReg());
82 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx)
85 O << ", #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
91 if ((Opcode == ARM::STMDB_UPD || Opcode == ARM::t2STMDB_UPD) &&
92 MI->getOperand(0).getReg() == ARM::SP) {
94 printPredicateOperand(MI, 2, O);
95 if (Opcode == ARM::t2STMDB_UPD)
98 printRegisterList(MI, 4, O);
101 if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP &&
102 MI->getOperand(3).getImm() == -4) {
104 printPredicateOperand(MI, 4, O);
105 O << "\t{" << getRegisterName(MI->getOperand(1).getReg()) << "}";
110 if ((Opcode == ARM::LDMIA_UPD || Opcode == ARM::t2LDMIA_UPD) &&
111 MI->getOperand(0).getReg() == ARM::SP) {
113 printPredicateOperand(MI, 2, O);
114 if (Opcode == ARM::t2LDMIA_UPD)
117 printRegisterList(MI, 4, O);
120 if (Opcode == ARM::LDR_POST_IMM && MI->getOperand(2).getReg() == ARM::SP &&
121 MI->getOperand(4).getImm() == 4) {
123 printPredicateOperand(MI, 5, O);
124 O << "\t{" << getRegisterName(MI->getOperand(0).getReg()) << "}";
130 if ((Opcode == ARM::VSTMSDB_UPD || Opcode == ARM::VSTMDDB_UPD) &&
131 MI->getOperand(0).getReg() == ARM::SP) {
132 O << '\t' << "vpush";
133 printPredicateOperand(MI, 2, O);
135 printRegisterList(MI, 4, O);
140 if ((Opcode == ARM::VLDMSIA_UPD || Opcode == ARM::VLDMDIA_UPD) &&
141 MI->getOperand(0).getReg() == ARM::SP) {
143 printPredicateOperand(MI, 2, O);
145 printRegisterList(MI, 4, O);
149 if (Opcode == ARM::tLDMIA) {
150 bool Writeback = true;
151 unsigned BaseReg = MI->getOperand(0).getReg();
152 for (unsigned i = 3; i < MI->getNumOperands(); ++i) {
153 if (MI->getOperand(i).getReg() == BaseReg)
159 printPredicateOperand(MI, 1, O);
160 O << '\t' << getRegisterName(BaseReg);
161 if (Writeback) O << "!";
163 printRegisterList(MI, 3, O);
168 if (Opcode == ARM::tMOVr && MI->getOperand(0).getReg() == ARM::R8 &&
169 MI->getOperand(1).getReg() == ARM::R8) {
174 printInstruction(MI, O);
177 void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
179 const MCOperand &Op = MI->getOperand(OpNo);
181 unsigned Reg = Op.getReg();
182 O << getRegisterName(Reg);
183 } else if (Op.isImm()) {
184 O << '#' << Op.getImm();
186 assert(Op.isExpr() && "unknown operand kind in printOperand");
191 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
192 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
194 // REG REG 0,SH_OPC - e.g. R5, ROR R3
195 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
196 void ARMInstPrinter::printSORegRegOperand(const MCInst *MI, unsigned OpNum,
198 const MCOperand &MO1 = MI->getOperand(OpNum);
199 const MCOperand &MO2 = MI->getOperand(OpNum+1);
200 const MCOperand &MO3 = MI->getOperand(OpNum+2);
202 O << getRegisterName(MO1.getReg());
204 // Print the shift opc.
205 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
206 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
207 if (ShOpc == ARM_AM::rrx)
210 O << ' ' << getRegisterName(MO2.getReg());
211 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
214 void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum,
216 const MCOperand &MO1 = MI->getOperand(OpNum);
217 const MCOperand &MO2 = MI->getOperand(OpNum+1);
219 O << getRegisterName(MO1.getReg());
221 // Print the shift opc.
222 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
223 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
224 if (ShOpc == ARM_AM::rrx)
226 O << " #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
230 //===--------------------------------------------------------------------===//
231 // Addressing Mode #2
232 //===--------------------------------------------------------------------===//
234 void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
236 const MCOperand &MO1 = MI->getOperand(Op);
237 const MCOperand &MO2 = MI->getOperand(Op+1);
238 const MCOperand &MO3 = MI->getOperand(Op+2);
240 O << "[" << getRegisterName(MO1.getReg());
243 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
245 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
246 << ARM_AM::getAM2Offset(MO3.getImm());
252 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
253 << getRegisterName(MO2.getReg());
255 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
257 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
262 void ARMInstPrinter::printAM2PostIndexOp(const MCInst *MI, unsigned Op,
264 const MCOperand &MO1 = MI->getOperand(Op);
265 const MCOperand &MO2 = MI->getOperand(Op+1);
266 const MCOperand &MO3 = MI->getOperand(Op+2);
268 O << "[" << getRegisterName(MO1.getReg()) << "], ";
271 unsigned ImmOffs = ARM_AM::getAM2Offset(MO3.getImm());
273 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
278 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
279 << getRegisterName(MO2.getReg());
281 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
283 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
287 void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
289 const MCOperand &MO1 = MI->getOperand(Op);
291 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
292 printOperand(MI, Op, O);
296 const MCOperand &MO3 = MI->getOperand(Op+2);
297 unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm());
299 if (IdxMode == ARMII::IndexModePost) {
300 printAM2PostIndexOp(MI, Op, O);
303 printAM2PreOrOffsetIndexOp(MI, Op, O);
306 void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
309 const MCOperand &MO1 = MI->getOperand(OpNum);
310 const MCOperand &MO2 = MI->getOperand(OpNum+1);
313 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
315 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
320 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
321 << getRegisterName(MO1.getReg());
323 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
325 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
329 //===--------------------------------------------------------------------===//
330 // Addressing Mode #3
331 //===--------------------------------------------------------------------===//
333 void ARMInstPrinter::printAM3PostIndexOp(const MCInst *MI, unsigned Op,
335 const MCOperand &MO1 = MI->getOperand(Op);
336 const MCOperand &MO2 = MI->getOperand(Op+1);
337 const MCOperand &MO3 = MI->getOperand(Op+2);
339 O << "[" << getRegisterName(MO1.getReg()) << "], ";
342 O << (char)ARM_AM::getAM3Op(MO3.getImm())
343 << getRegisterName(MO2.getReg());
347 unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
349 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
353 void ARMInstPrinter::printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
355 const MCOperand &MO1 = MI->getOperand(Op);
356 const MCOperand &MO2 = MI->getOperand(Op+1);
357 const MCOperand &MO3 = MI->getOperand(Op+2);
359 O << '[' << getRegisterName(MO1.getReg());
362 O << ", " << getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
363 << getRegisterName(MO2.getReg()) << ']';
367 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
369 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
374 void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned Op,
376 const MCOperand &MO3 = MI->getOperand(Op+2);
377 unsigned IdxMode = ARM_AM::getAM3IdxMode(MO3.getImm());
379 if (IdxMode == ARMII::IndexModePost) {
380 printAM3PostIndexOp(MI, Op, O);
383 printAM3PreOrOffsetIndexOp(MI, Op, O);
386 void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
389 const MCOperand &MO1 = MI->getOperand(OpNum);
390 const MCOperand &MO2 = MI->getOperand(OpNum+1);
393 O << getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
394 << getRegisterName(MO1.getReg());
398 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
400 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
404 void ARMInstPrinter::printPostIdxImm8Operand(const MCInst *MI,
407 const MCOperand &MO = MI->getOperand(OpNum);
408 unsigned Imm = MO.getImm();
409 O << '#' << ((Imm & 256) ? "" : "-") << (Imm & 0xff);
412 void ARMInstPrinter::printPostIdxRegOperand(const MCInst *MI, unsigned OpNum,
414 const MCOperand &MO1 = MI->getOperand(OpNum);
415 const MCOperand &MO2 = MI->getOperand(OpNum+1);
417 O << (MO2.getImm() ? "" : "-") << getRegisterName(MO1.getReg());
420 void ARMInstPrinter::printPostIdxImm8s4Operand(const MCInst *MI,
423 const MCOperand &MO = MI->getOperand(OpNum);
424 unsigned Imm = MO.getImm();
425 O << '#' << ((Imm & 256) ? "" : "-") << ((Imm & 0xff) << 2);
429 void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
431 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MI->getOperand(OpNum)
433 O << ARM_AM::getAMSubModeStr(Mode);
436 void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
438 const MCOperand &MO1 = MI->getOperand(OpNum);
439 const MCOperand &MO2 = MI->getOperand(OpNum+1);
441 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
442 printOperand(MI, OpNum, O);
446 O << "[" << getRegisterName(MO1.getReg());
448 if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
450 << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
456 void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
458 const MCOperand &MO1 = MI->getOperand(OpNum);
459 const MCOperand &MO2 = MI->getOperand(OpNum+1);
461 O << "[" << getRegisterName(MO1.getReg());
463 // FIXME: Both darwin as and GNU as violate ARM docs here.
464 O << ", :" << (MO2.getImm() << 3);
469 void ARMInstPrinter::printAddrMode7Operand(const MCInst *MI, unsigned OpNum,
471 const MCOperand &MO1 = MI->getOperand(OpNum);
472 O << "[" << getRegisterName(MO1.getReg()) << "]";
475 void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
478 const MCOperand &MO = MI->getOperand(OpNum);
479 if (MO.getReg() == 0)
482 O << ", " << getRegisterName(MO.getReg());
485 void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
488 const MCOperand &MO = MI->getOperand(OpNum);
489 uint32_t v = ~MO.getImm();
490 int32_t lsb = CountTrailingZeros_32(v);
491 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
492 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
493 O << '#' << lsb << ", #" << width;
496 void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
498 unsigned val = MI->getOperand(OpNum).getImm();
499 O << ARM_MB::MemBOptToString(val);
502 void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
504 unsigned ShiftOp = MI->getOperand(OpNum).getImm();
505 bool isASR = (ShiftOp & (1 << 5)) != 0;
506 unsigned Amt = ShiftOp & 0x1f;
508 O << ", asr #" << (Amt == 0 ? 32 : Amt);
510 O << ", lsl #" << Amt;
513 void ARMInstPrinter::printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum,
515 unsigned Imm = MI->getOperand(OpNum).getImm();
518 assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!");
519 O << ", lsl #" << Imm;
522 void ARMInstPrinter::printPKHASRShiftImm(const MCInst *MI, unsigned OpNum,
524 unsigned Imm = MI->getOperand(OpNum).getImm();
525 // A shift amount of 32 is encoded as 0.
528 assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!");
529 O << ", asr #" << Imm;
532 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
535 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
536 if (i != OpNum) O << ", ";
537 O << getRegisterName(MI->getOperand(i).getReg());
542 void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
544 const MCOperand &Op = MI->getOperand(OpNum);
551 void ARMInstPrinter::printCPSIMod(const MCInst *MI, unsigned OpNum,
553 const MCOperand &Op = MI->getOperand(OpNum);
554 O << ARM_PROC::IModToString(Op.getImm());
557 void ARMInstPrinter::printCPSIFlag(const MCInst *MI, unsigned OpNum,
559 const MCOperand &Op = MI->getOperand(OpNum);
560 unsigned IFlags = Op.getImm();
561 for (int i=2; i >= 0; --i)
562 if (IFlags & (1 << i))
563 O << ARM_PROC::IFlagsToString(1 << i);
566 void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
568 const MCOperand &Op = MI->getOperand(OpNum);
569 unsigned SpecRegRBit = Op.getImm() >> 4;
570 unsigned Mask = Op.getImm() & 0xf;
572 // As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as
573 // APSR_nzcvq, APSR_g and APSRnzcvqg, respectively.
574 if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) {
578 case 4: O << "g"; return;
579 case 8: O << "nzcvq"; return;
580 case 12: O << "nzcvqg"; return;
582 llvm_unreachable("Unexpected mask value!");
592 if (Mask & 8) O << 'f';
593 if (Mask & 4) O << 's';
594 if (Mask & 2) O << 'x';
595 if (Mask & 1) O << 'c';
599 void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
601 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
603 O << ARMCondCodeToString(CC);
606 void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI,
609 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
610 O << ARMCondCodeToString(CC);
613 void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
615 if (MI->getOperand(OpNum).getReg()) {
616 assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
617 "Expect ARM CPSR register!");
622 void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
624 O << MI->getOperand(OpNum).getImm();
627 void ARMInstPrinter::printPImmediate(const MCInst *MI, unsigned OpNum,
629 O << "p" << MI->getOperand(OpNum).getImm();
632 void ARMInstPrinter::printCImmediate(const MCInst *MI, unsigned OpNum,
634 O << "c" << MI->getOperand(OpNum).getImm();
637 void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
639 llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
642 void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
644 O << "#" << MI->getOperand(OpNum).getImm() * 4;
647 void ARMInstPrinter::printThumbSRImm(const MCInst *MI, unsigned OpNum,
649 unsigned Imm = MI->getOperand(OpNum).getImm();
650 O << "#" << (Imm == 0 ? 32 : Imm);
653 void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
655 // (3 - the number of trailing zeros) is the number of then / else.
656 unsigned Mask = MI->getOperand(OpNum).getImm();
657 unsigned CondBit0 = Mask >> 4 & 1;
658 unsigned NumTZ = CountTrailingZeros_32(Mask);
659 assert(NumTZ <= 3 && "Invalid IT mask!");
660 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
661 bool T = ((Mask >> Pos) & 1) == CondBit0;
669 void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
671 const MCOperand &MO1 = MI->getOperand(Op);
672 const MCOperand &MO2 = MI->getOperand(Op + 1);
674 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
675 printOperand(MI, Op, O);
679 O << "[" << getRegisterName(MO1.getReg());
680 if (unsigned RegNum = MO2.getReg())
681 O << ", " << getRegisterName(RegNum);
685 void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI,
689 const MCOperand &MO1 = MI->getOperand(Op);
690 const MCOperand &MO2 = MI->getOperand(Op + 1);
692 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
693 printOperand(MI, Op, O);
697 O << "[" << getRegisterName(MO1.getReg());
698 if (unsigned ImmOffs = MO2.getImm())
699 O << ", #" << ImmOffs * Scale;
703 void ARMInstPrinter::printThumbAddrModeImm5S1Operand(const MCInst *MI,
706 printThumbAddrModeImm5SOperand(MI, Op, O, 1);
709 void ARMInstPrinter::printThumbAddrModeImm5S2Operand(const MCInst *MI,
712 printThumbAddrModeImm5SOperand(MI, Op, O, 2);
715 void ARMInstPrinter::printThumbAddrModeImm5S4Operand(const MCInst *MI,
718 printThumbAddrModeImm5SOperand(MI, Op, O, 4);
721 void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
723 printThumbAddrModeImm5SOperand(MI, Op, O, 4);
726 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
727 // register with shift forms.
729 // REG IMM, SH_OPC - e.g. R5, LSL #3
730 void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
732 const MCOperand &MO1 = MI->getOperand(OpNum);
733 const MCOperand &MO2 = MI->getOperand(OpNum+1);
735 unsigned Reg = MO1.getReg();
736 O << getRegisterName(Reg);
738 // Print the shift opc.
739 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
740 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
741 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
742 if (ShOpc != ARM_AM::rrx)
743 O << " #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
746 void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
748 const MCOperand &MO1 = MI->getOperand(OpNum);
749 const MCOperand &MO2 = MI->getOperand(OpNum+1);
751 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
752 printOperand(MI, OpNum, O);
756 O << "[" << getRegisterName(MO1.getReg());
758 int32_t OffImm = (int32_t)MO2.getImm();
759 bool isSub = OffImm < 0;
760 // Special value for #-0. All others are normal.
761 if (OffImm == INT32_MIN)
764 O << ", #-" << -OffImm;
766 O << ", #" << OffImm;
770 void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
773 const MCOperand &MO1 = MI->getOperand(OpNum);
774 const MCOperand &MO2 = MI->getOperand(OpNum+1);
776 O << "[" << getRegisterName(MO1.getReg());
778 int32_t OffImm = (int32_t)MO2.getImm();
781 O << ", #-" << -OffImm;
783 O << ", #" << OffImm;
787 void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
790 const MCOperand &MO1 = MI->getOperand(OpNum);
791 const MCOperand &MO2 = MI->getOperand(OpNum+1);
793 O << "[" << getRegisterName(MO1.getReg());
795 int32_t OffImm = (int32_t)MO2.getImm() / 4;
798 O << ", #-" << -OffImm * 4;
800 O << ", #" << OffImm * 4;
804 void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI,
807 const MCOperand &MO1 = MI->getOperand(OpNum);
808 int32_t OffImm = (int32_t)MO1.getImm();
811 O << "#-" << -OffImm;
816 void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI,
819 const MCOperand &MO1 = MI->getOperand(OpNum);
820 int32_t OffImm = (int32_t)MO1.getImm() / 4;
823 O << "#-" << -OffImm * 4;
825 O << "#" << OffImm * 4;
828 void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
831 const MCOperand &MO1 = MI->getOperand(OpNum);
832 const MCOperand &MO2 = MI->getOperand(OpNum+1);
833 const MCOperand &MO3 = MI->getOperand(OpNum+2);
835 O << "[" << getRegisterName(MO1.getReg());
837 assert(MO2.getReg() && "Invalid so_reg load / store address!");
838 O << ", " << getRegisterName(MO2.getReg());
840 unsigned ShAmt = MO3.getImm();
842 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
843 O << ", lsl #" << ShAmt;
848 void ARMInstPrinter::printVFPf32ImmOperand(const MCInst *MI, unsigned OpNum,
850 const MCOperand &MO = MI->getOperand(OpNum);
853 O << (float)MO.getFPImm();
860 FPUnion.I = MO.getImm();
865 void ARMInstPrinter::printVFPf64ImmOperand(const MCInst *MI, unsigned OpNum,
867 const MCOperand &MO = MI->getOperand(OpNum);
872 // We expect the binary encoding of a floating point number here.
878 FPUnion.I = MO.getImm();
883 void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
885 unsigned EncodedImm = MI->getOperand(OpNum).getImm();
887 uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
888 O << "#0x" << utohexstr(Val);
891 void ARMInstPrinter::printImmPlusOneOperand(const MCInst *MI, unsigned OpNum,
893 unsigned Imm = MI->getOperand(OpNum).getImm();
897 void ARMInstPrinter::printRotImmOperand(const MCInst *MI, unsigned OpNum,
899 unsigned Imm = MI->getOperand(OpNum).getImm();
904 default: assert (0 && "illegal ror immediate!");
905 case 1: O << "8"; break;
906 case 2: O << "16"; break;
907 case 3: O << "24"; break;